CN116190246A - Double-sided electroplating structure of chip plastic package body and preparation method thereof - Google Patents
Double-sided electroplating structure of chip plastic package body and preparation method thereof Download PDFInfo
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- CN116190246A CN116190246A CN202211607885.2A CN202211607885A CN116190246A CN 116190246 A CN116190246 A CN 116190246A CN 202211607885 A CN202211607885 A CN 202211607885A CN 116190246 A CN116190246 A CN 116190246A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a double-sided electroplating structure of a chip plastic package body and a preparation method thereof. The preparation method comprises the following steps: preparing a chip plastic package body, and enabling the chip to be wrapped in a first plastic package layer; carrying out open pore treatment on the chip plastic package body to form a through hole and a blind hole for exposing an I/O port of the chip; the first conductive column is manufactured in the through hole through direct current electroplating or pulse electroplating synchronously, the second conductive column is manufactured in the blind hole, and the first rewiring layer connected with the first conductive column and the second conductive column is manufactured on the double sides of the chip plastic package body synchronously. The invention can realize the synchronous manufacture of the first conductive column and the second conductive column in the through hole and the blind hole of the chip plastic package body, and the synchronous manufacture of the first rewiring layer at the two sides of the chip plastic package body, thereby realizing the signal interconnection and the penetration between the functional chips. Compared with the prior art, the method shortens the process flow, improves the production efficiency, reduces the cost and improves the yield.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a double-sided electroplating structure of a chip plastic package body and the double-sided electroplating structure of the chip plastic package body prepared by the preparation method.
Background
With the development of the semiconductor field, the densification of microelectronic packaging technology has become a mainstream in new generation electronic products. Different packaging technologies have great differences in the aspects of manufacturing procedures and processes, and play a vital role in the performance of the chip after packaging. With the development of packaging technology and technology, chips are developed towards higher density, faster speed, smaller size, lower cost, and the like. The electroplating of the two sides of the chip plastic package body is a key link of the existing packaging technology, and the quality of the electroplating effect directly influences the performance and use of the chip.
At present, the process of electroplating two sides of the chip plastic package body is separated, namely, one side of the chip plastic package body is firstly subjected to electroplating treatment, and the other side of the chip plastic package body is then subjected to electroplating treatment.
Disclosure of Invention
The invention aims to provide a preparation method of a double-sided electroplating structure of a chip plastic package body, which can realize that a first conductive column, a second conductive column and a first rewiring layer are directly prepared through double-sided electroplating after a through hole and a blind hole are formed in the chip plastic package body, so that signal interconnection and penetration between functional chips are realized, the process flow is shortened, the production efficiency is improved, the cost is reduced, and the yield is correspondingly improved.
The second purpose of the invention is to provide a double-sided electroplating structure of the chip plastic package body, which is prepared by the preparation method, and the preparation method is relatively simple, the production cost is low, and the yield is high.
To achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a method for preparing a double-sided electroplating structure of a chip plastic package body is provided, which comprises the following steps:
s10, preparing a chip plastic package body, and enabling the chip to be wrapped in a first plastic package layer;
s20, carrying out hole opening treatment on the chip plastic package body to form a through hole penetrating through the chip plastic package body and a blind hole exposing an I/O port of the chip;
s30, manufacturing a first conductive column in the through hole synchronously through double-sided electroplating, manufacturing a second conductive column in the blind hole, and manufacturing a first rewiring layer connected with the first conductive column and the second conductive column synchronously on the double sides of the chip plastic package body;
wherein, the double-sided electroplating adopts direct current electroplating or pulse electroplating.
The invention can realize the synchronous manufacture of the first conductive column and the second conductive column in the through hole and the blind hole of the chip plastic package body and the synchronous manufacture of the first rewiring layer on the two sides of the chip plastic package body by opening the through hole and the blind hole and matching with pulse electroplating, thereby realizing the signal interconnection and the penetration between the functional chips. Compared with the existing single-sided electroplating, the method shortens the process flow, improves the production efficiency, reduces the cost and correspondingly improves the yield.
As a preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body, the through holes are X-shaped through holes or vertical through holes, and the preparation method is suitable for double-sided electroplating by adopting pulse electroplating.
Preferably, the through holes are X-shaped through holes, so that the double-sided electroplating effect can be further improved, and the product yield is improved.
As a preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body, the step S10 specifically comprises the following steps:
s10a, providing a carrier plate and a chip, and attaching the chip to the carrier plate;
s10b, adopting a plastic packaging material to carry out plastic packaging on the chip to form a first plastic packaging layer for coating the chip;
s10c, removing the carrier plate to obtain the chip plastic package body.
As another preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body,
the step S10 specifically includes the following steps:
s10a, providing a carrier plate and a chip, and attaching the chip to the carrier plate;
s10b, adopting a plastic packaging material to carry out plastic packaging on the chip to form a first plastic packaging layer for coating the chip;
s10c, removing the carrier plate;
and S10d, respectively preparing dielectric layers on two sides of the first plastic sealing layer to obtain the chip plastic sealing body.
Further, in S10a, a glue film is first attached to one side of the carrier, and then the front side (not limited to the front side, but also the back side) of the chip is fixed on the glue film by a chip mounter; wherein, the carrier plate material can be SUS, prepreg (BT), FR4, FR5, glass, PP, EMC, PI and the like; the adhesive film material includes, but is not limited to, any of temporary bonding adhesive, DAF film, PI film, dry film, ABF film, and ABF-like adhesive film.
Further, in S10b, the molding compound material includes, but is not limited to, any of EMC, ABF, PI, PP.
In step S10c, the carrier needs to be removed, and the adhesive film and the chip are separated.
Further, in S10d, dielectric layers are respectively prepared on two sides of the first molding layer, so as to obtain the chip molding body.
As a preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body, the step S20 specifically comprises the following steps: and a through hole is formed in the chip plastic package body along the thickness direction of the chip plastic package body at a position which avoids the chip, and a blind hole which enables the I/O port to be exposed is formed in the chip plastic package body at a position which corresponds to the I/O port of the chip.
Specifically, a drilling process is adopted to open a through hole penetrating up and down and a blind hole extending to an I/O port (output end) of the chip on the chip plastic package body, and the drilling process comprises any one of laser drilling, mechanical drilling and mask covering Plasma tapping.
As a preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body, the step S30 specifically comprises the following steps:
s30a, manufacturing first seed layers on the side walls of the through holes and the blind holes and on two sides of the chip plastic package body along the thickness direction of the chip plastic package body;
s30b, attaching a first photosensitive film on the first seed layers positioned on two sides of the chip plastic package body, and enabling the first photosensitive film to cover part of the first seed layers;
s30c, electroplating is synchronously carried out in the through hole, the blind hole and the first seed layers on the two sides of the chip plastic package body through double-sided electroplating, so that a first conductive column filled with the through hole, a second conductive column filled with the blind hole and a first rewiring layer which is positioned on the two sides of the chip plastic package body and connected with the first conductive column and the second conductive column are prepared.
Further, before the first seed layer is manufactured, the chip plastic package body after the opening is heated in a high vacuum state, the moisture and pollutants of the chip plastic package body are removed, and then the Ti-Cu seed layer with high adhesive force, excellent conductivity and uniform thickness is prepared on the two sides through magnetron sputtering. The magnetron sputtering Ti-Cu seed layer is a conventional technical means in the field, and is not described in detail. The first seed layer in the present invention is not limited to the ti—cu seed layer, and may be a Ti seed layer.
After the first seed layer is manufactured, a first photosensitive film is stuck on the first seed layer at two sides of the chip plastic package body, and then a graphical window is formed through exposure and development;
and preparing a first conductive column in the through hole, a second conductive column in the blind hole and a first rewiring layer in the patterned window by adopting pulse electroplating.
For the product prepared by the step S10-30, the oxidation prevention layers can be respectively manufactured on the sides, far away from the chip plastic package body, of the first rewiring layers on the two sides of the product, so that the oxidation prevention effect on the first rewiring layers can be achieved, and meanwhile, the electric conductivity of the first rewiring layers is improved.
Specifically, the oxidation prevention layer is prepared by adopting a nickel-palladium-gold process, and has good oxidation resistance and conductivity.
As a preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body, the preparation method further comprises the step S40, and specifically comprises the following steps:
s40a, attaching a second photosensitive film on the first rewiring layer at one side of the chip plastic package body, and enabling part of the first rewiring layer to be exposed out of the second photosensitive film; specifically, a patterned window which exposes a portion of the first rewiring layer to the second photosensitive film is formed on the second photosensitive film by an exposure development technique;
s40b, manufacturing a third conductive column at the exposed position (namely a graphical window) of the first rewiring layer through electroplating;
s40c, removing the residual first photosensitive film and the residual second photosensitive film, and etching the exposed first seed layer;
s40d, performing plastic packaging treatment on the first rewiring layer and the third conductive column by adopting plastic packaging materials to form a second plastic packaging layer for coating the first rewiring layer and the third conductive column, and enabling one end face, far away from the first rewiring layer, of the third conductive column to be exposed out of the second plastic packaging layer;
s40e, manufacturing a second seed layer on the second plastic sealing layer, and connecting the second seed layer with the third conductive column;
s40f, sticking a third photosensitive film on the second seed layer, and exposing part of the second seed layer to the third photosensitive film; specifically, a patterned window which enables the second seed layer to be partially exposed out of the third photosensitive film is formed on the third photosensitive film through an exposure and development technology;
s40g, manufacturing a second redistribution layer by electroplating on one side (namely a patterned window) of the second seed layer exposed on the third photosensitive film;
and S40h, removing the residual third photosensitive film and etching away the part of the second seed layer exposed out of the second redistribution layer.
The second seed layer and the first seed layer have the same preparation process and can be a Ti-Cu seed layer or a Ti seed layer.
As another preferable scheme of the preparation method of the double-sided electroplating structure of the chip plastic package body, the preparation method further comprises the step S50 of respectively manufacturing an anti-oxidation layer with conductivity on the exposed sides of the first redistribution layer and the second redistribution layer, wherein the anti-oxidation layer is a Ni-Pd-Au film prepared through a nickel-palladium-gold process.
On the other hand, a double-sided electroplating structure of the chip plastic package body manufactured according to the manufacturing method is provided, which comprises the following steps:
the chip plastic package body comprises a plurality of chips and a first plastic package layer for coating the chips; the chip plastic package body is provided with a plurality of through holes penetrating through the chip plastic package body and a plurality of blind holes exposing the I/O port of the chip along the thickness direction of the chip plastic package body;
the first seed layers are positioned on the side walls of the through holes, the side walls of the blind holes and the two sides of the chip plastic package body;
the first conductive column is filled in the through hole, the second conductive column is filled in the blind hole, and the first rewiring layer is positioned on the first seed layers at two sides of the chip plastic package body;
the first rewiring layer on one side of the chip plastic package body is connected with the I/O port of the chip through the second conductive column, and is connected with the first rewiring layer on the other side through the first conductive column.
In the invention, the number of chips is at least two.
The first conductive column of the through hole, the second conductive column in the blind hole and the first rewiring layers on two sides of the chip plastic package body are prepared through double-sided electroplating by adopting a pulse electroplating method, so that signal interconnection and penetration between chips are realized.
As a preferable scheme of the double-sided electroplating structure of the chip plastic package body, the through holes are X-shaped through holes or vertical through holes, and preferably X-shaped through holes.
As one of the preferable schemes of the double-sided electroplating structure of the chip plastic package body, the double-sided electroplating structure further comprises an anti-oxidation layer with conductivity, wherein the anti-oxidation layer is positioned on one side, away from the chip plastic package body, of the first rewiring layer on two sides of the chip plastic package body.
As a preferred scheme of the double-sided electroplating structure of the chip plastic package body, the double-sided electroplating structure of the chip plastic package body further comprises:
the third conductive column is positioned on one side of the first rewiring layer on one side of the chip plastic package body;
the second plastic sealing layer is positioned on one side of the first rewiring layer and coats the third conductive column, and the end face of the third conductive column is exposed out of the second plastic sealing layer;
and the second redistribution layer is positioned on one side of the second plastic sealing layer and connected with the third conductive post.
As a preferred scheme of the double-sided electroplating structure of the chip plastic package body, the double-sided electroplating structure of the chip plastic package body further comprises:
the dielectric layer is arranged on two sides of the first plastic sealing layer respectively, and the dielectric layer is positioned between the first plastic sealing layer and the first seed layer. The overall strength of the product can be improved by providing a dielectric layer.
As a second preferred scheme of the double-sided electroplating structure of the chip plastic package body, the double-sided electroplating structure further comprises an anti-oxidation layer with conductivity, wherein the anti-oxidation layer is positioned on one side of the second redistribution layer away from the chip plastic package body and one side of the first redistribution layer away from the second redistribution layer.
The invention has the beneficial effects that: according to the invention, through holes and blind holes are formed in the chip plastic package body, and pulse electroplating is matched, so that the first conductive columns and the second conductive columns can be synchronously prepared in the through holes and the blind holes of the chip plastic package body, and the first rewiring layers can be synchronously prepared on the two sides of the chip plastic package body, thereby realizing signal interconnection and penetration between functional chips. Compared with the existing single-sided electroplating, the method shortens the process flow, improves the production efficiency, reduces the production cost of the double-sided electroplating structure of the chip plastic package body, and correspondingly improves the yield.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a flowchart of a method for preparing a double-sided electroplating structure of a chip molding compound according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of an adhesive film attached to a carrier according to an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a chip attached to a carrier by an adhesive film according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a chip according to an embodiment of the invention after being adhered to a carrier by a plastic film for plastic packaging.
Fig. 5 is a schematic cross-sectional view of a chip molding package according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a chip molding package according to an embodiment of the invention after forming an X-shaped through hole and a blind hole.
Fig. 7 is a schematic cross-sectional view of a first seed layer according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of a first photosensitive film formed on a first seed layer and exposed to light for development according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of an embodiment of the present invention after preparing a first conductive pillar in an X-type through hole, preparing a second conductive pillar in a blind hole, and preparing a redistribution layer on a first seed layer on both sides of a chip molding.
Fig. 10 is a schematic cross-sectional view of a first redistribution layer with a second photosensitive film attached to the first redistribution layer to form a third conductive pillar according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of the first photosensitive film and the second photosensitive film after removing the residues according to the first embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of a first redistribution layer and a third conductive pillar connected thereto after plastic packaging and thinning according to an embodiment of the present invention.
Fig. 13 is a schematic cross-sectional view of a second plastic sealing layer after a second seed layer is formed on the second plastic sealing layer, a third photosensitive film is attached, and a second redistribution layer is formed according to an embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view of the third photosensitive film after removing the residual second seed layer and etching away the exposed second seed layer according to the first embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view of a double-sided electroplating structure of a chip molding compound according to an embodiment of the invention.
Fig. 16 is a schematic cross-sectional view of a double-sided electroplating structure of a chip molding compound according to a second embodiment of the invention.
Fig. 17 is a schematic cross-sectional view of a chip molding package according to a fifth embodiment of the invention.
Fig. 18 is a schematic cross-sectional view of a chip molding package according to a fifth embodiment of the invention after forming an X-shaped through hole and a blind hole.
Fig. 19 is a schematic cross-sectional view of a fifth embodiment of the invention after preparing a first seed layer.
Fig. 20 is a schematic cross-sectional view of a fifth embodiment of the present invention after a first photosensitive film is formed on a first seed layer and exposed to light for development.
Fig. 21 is a schematic cross-sectional view of a fifth embodiment of the present invention after preparing a first conductive pillar in an X-shaped through hole, preparing a second conductive pillar in a blind hole, and preparing a redistribution layer on a first seed layer on both sides of a chip molding.
Fig. 22 is a schematic cross-sectional view of a fifth embodiment of the present invention after a second photosensitive film is attached to a first redistribution layer on one side to prepare a third conductive pillar.
Fig. 23 is a schematic cross-sectional view of the fifth embodiment of the present invention after removing the residual first photosensitive film and second photosensitive film.
Fig. 24 is a schematic cross-sectional view of a fifth embodiment of the present invention after plastic packaging and thinning the first redistribution layer and the third conductive pillars connected thereto.
Fig. 25 is a schematic cross-sectional view of a fifth embodiment of the present invention after a second seed layer is formed on a second molding layer, a third photosensitive film is attached, and a second redistribution layer is formed.
Fig. 26 is a schematic cross-sectional view of a fifth embodiment of the invention after removing the residual third photosensitive film and etching away the exposed second seed layer.
Fig. 27 is a schematic cross-sectional view of a double-sided electroplating structure of a chip molding compound according to a fifth embodiment of the invention.
In the figure:
1. a carrier plate; 2. an adhesive film; 3. a chip; 41. a first plastic layer; 411. a through hole; 412. a blind hole; 42. a second plastic layer; 51. a first seed layer; 52. a second seed layer; 61. a first photosensitive film; 62. a second photosensitive film; 63. a third photosensitive film; 71. a first conductive pillar; 72. a second conductive post; 73. a third conductive post; 81. a first rewiring layer; 82. a second rewiring layer; 9. an oxidation preventing layer; 10. a dielectric layer.
Detailed Description
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to be limiting of the present patent; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, only for convenience in describing the present invention and simplifying the description, rather than indicating or implying that the apparatus or elements being referred to must have a specific orientation, be constructed and operated in a specific orientation, so that the terms describing the positional relationships in the drawings are merely for exemplary illustration and should not be construed as limiting the present patent, and that the specific meaning of the terms described above may be understood by those of ordinary skill in the art according to specific circumstances.
In the description of the present invention, unless explicitly stated and limited otherwise, the term "coupled" or the like should be interpreted broadly, as it may be fixedly coupled, detachably coupled, or integrally formed, as indicating the relationship of components; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between the two parts or interaction relationship between the two parts. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Example 1
As shown in fig. 1, the preparation method of the double-sided electroplating structure of the chip plastic package body in this embodiment is as follows:
step 2, fixing the back surfaces of the chips 3 on temporary bonding glue through a chip mounter (as shown in fig. 3);
step 4, removing the carrier plate 1, and removing the temporary bonding glue to obtain a chip plastic package (shown in figure 5);
step 5, performing hole opening treatment on the first plastic sealing layer 41 through a laser drilling process to form a plurality of X-shaped through holes 411 penetrating through the first plastic sealing layer 4 up and down and a plurality of blind holes 412 exposing the I/O ports of the chip 3 (as shown in fig. 6);
step 7, attaching a first photosensitive film 61 to the exposed side of the first seed layer 51, and forming a patterned window on the first photosensitive film 61 by exposure and development (as shown in fig. 8);
step 9, attaching a second photosensitive film 62 on the first redistribution layer 81 near the front side of the chip 3, exposing and developing the second photosensitive film 62 to form a patterned window, and then electroplating copper deposition to obtain a third conductive post 73 (copper post) connected with the first redistribution layer 81 in the patterned window (as shown in fig. 10);
step 11, plastic packaging is performed on the third conductive column 73 and the first redistribution layer 81 positioned below the third conductive column 73 by adopting an EMC plastic packaging material to form a second plastic packaging layer 42 which coats the third conductive column 73 and the first redistribution layer 81, and grinding treatment is performed on the second plastic packaging layer 42 so that the upper end face of the third conductive column 73 is exposed (refer to fig. 12);
step 13, removing the residual third photosensitive film 63 and etching away the exposed second seed layer 52 (refer to fig. 14);
in step 14, an oxidation preventing layer 9 is respectively plated on the surfaces of the exposed first redistribution layer 81 and the exposed second redistribution layer 82 by a nickel-palladium-gold process, so as to obtain the double-sided electroplating structure of the chip plastic package body as shown in fig. 15.
As shown in fig. 15; the double-sided electroplating structure of the chip plastic package body in the embodiment comprises:
the chip plastic package body comprises a plurality of chips 3 and a first plastic package layer 41 for coating the chips 3; the first plastic sealing layer 41 is provided with a plurality of through holes 411 penetrating through the first plastic sealing layer 41 and a plurality of blind holes 412 exposing the I/O ports of the chip 3 along the thickness direction thereof;
the first seed layers 51 are positioned on the side walls of the through holes 411, the side walls of the blind holes 412 and the two sides of the first plastic sealing layer 41;
the first conductive pillars 71 filled in the through holes 411, the second conductive pillars 72 filled in the blind holes 412, and the first redistribution layer on the first seed layer 51 on both sides of the first molding layer 41;
the first redistribution layer 81 on one side of the first plastic sealing layer 41 is connected to the I/O port of the chip 3 through the second conductive pillar 72, and is connected to the first redistribution layer 81 on the other side through the first conductive pillar 71.
In the present invention, the number of chips 3 is at least two.
The first conductive pillars 71 of the through holes 411, the second conductive pillars 72 in the blind holes 412, and the first redistribution layer 81 on both sides of the chip plastic package are manufactured by double-sided electroplating through a pulse electroplating method, so as to realize signal interconnection and penetration between the chips 3.
Further, the through hole 411 is an X-shaped through hole, and the efficiency of double-sided electroplating and the yield of products can be improved by adopting the X-shaped through hole.
Further, the double-sided electroplating structure of the chip plastic package body further comprises:
a third conductive pillar 73, the third conductive pillar 73 being located at one side of the first redistribution layer 81 at one side of the first molding layer 41;
a second molding layer 42, wherein the second molding layer 42 is located at one side of the first redistribution layer 81 and covers the third conductive pillars 73, and an end surface of the third conductive pillars 73 is exposed to the second molding layer 42;
a second seed layer 52 located on one side of the second molding layer 42 and connected to the third conductive pillars 73, and a second redistribution layer 82 located on the second seed layer 52.
Further, the double-sided electroplating structure of the chip plastic package further comprises an oxidation preventing layer 9 with conductivity, wherein the oxidation preventing layer 9 is positioned on the exposed side of the second redistribution layer 82 and on the exposed side of the first redistribution layer 81.
Example two
The preparation method of the double-sided electroplating structure of the chip plastic package body of the embodiment is basically the same as that of the first embodiment, and the difference is that the circuit structure of the embodiment is a single-layer circuit structure obtained by double-sided pulse electroplating.
Specifically, the preparation method of the double-sided electroplating structure of the chip plastic package body in the embodiment is as follows:
step 2, fixing the back surfaces of the chips 3 on temporary bonding glue through a chip mounter (as shown in fig. 3);
step 4, removing the carrier plate 1, and removing the temporary bonding glue to obtain a chip plastic package (shown in figure 5);
step 5, performing hole opening treatment on the first plastic sealing layer 41 through a laser drilling process to form a plurality of X-shaped through holes 411 penetrating through the first plastic sealing layer 4 up and down and a plurality of blind holes 412 exposing the I/O ports of the chip 3 (as shown in fig. 6);
step 7, attaching a first photosensitive film 61 to the exposed side of the first seed layer 51, and forming a patterned window on the first photosensitive film 61 by exposure and development (as shown in fig. 8);
step 9, removing the residual first photosensitive film 61 and etching away the exposed first seed layer 51;
Specifically, the double-sided electroplating structure of the chip plastic package body in the embodiment includes:
the chip plastic package body comprises a plurality of chips 3 and a first plastic package layer 41 for coating the chips 3; the first plastic sealing layer 41 is provided with a plurality of through holes 411 penetrating through the first plastic sealing layer 41 and a plurality of blind holes 412 exposing the I/O ports of the chip 3 along the thickness direction thereof;
the first seed layers 51 are positioned on the side walls of the through holes 411, the side walls of the blind holes 412 and the two sides of the first plastic sealing layer 41;
the first conductive pillars 71 filled in the through holes 411, the second conductive pillars 72 filled in the blind holes 412, and the first redistribution layer on the first seed layer 51 on both sides of the first molding layer 41;
the first redistribution layer 81 on one side of the first plastic sealing layer 41 is connected to the I/O port of the chip 3 through the second conductive pillar 72, and is connected to the first redistribution layer 81 on the other side through the first conductive pillar 71.
In the present invention, the number of chips 3 is at least two.
The first conductive pillars 71 of the through holes 411, the second conductive pillars 72 in the blind holes 412, and the first redistribution layer 81 on both sides of the chip plastic package are manufactured by double-sided electroplating through a pulse electroplating method, so as to realize signal interconnection and penetration between the chips 3.
Further, the through hole 411 is an X-shaped through hole, and the efficiency of double-sided electroplating and the yield of products can be improved by adopting the X-shaped through hole.
Further, the double-sided electroplating structure of the chip plastic package further comprises an oxidation preventing layer 9 with conductivity, wherein the oxidation preventing layer 9 is positioned on the exposed side of the second redistribution layer 82 and on the exposed side of the first redistribution layer 81.
Example III
The present embodiment is substantially the same as the first embodiment, except that the through hole formed in the first plastic layer is a vertical through hole, and specifically, the through hole is circular. In other embodiments, the vertical through hole is not limited to a circle, and may be a polygon.
The preparation method of the double-sided electroplating structure of the chip plastic package body in this embodiment is the same as that in the first embodiment, and detailed description thereof is omitted.
Example IV
The difference between the present embodiment and the first embodiment is that the third conductive pillar, the second molding layer, the second seed layer and the second redistribution layer are all located on one side of the first redistribution layer on the other side, and the specific preparation method may refer to the first embodiment and is not described again.
Example five
The preparation method of the double-sided electroplating structure of the chip plastic package of the present embodiment is basically the same as that of the first embodiment, except that the dielectric layer 10 is added.
Specifically, the preparation method of the double-sided electroplating structure of the chip plastic package body in the embodiment is as follows:
as shown in fig. 1, the preparation method of the double-sided electroplating structure of the chip plastic package body in this embodiment is as follows:
step 2, fixing the back surfaces of the chips 3 on temporary bonding glue through a chip mounter (as shown in fig. 3);
step 4, removing the carrier plate 1, preparing dielectric layers 10 on two sides of the first plastic sealing layer 41 respectively, and removing temporary bonding glue to obtain a chip plastic sealing body (as shown in fig. 17); the dielectric layer material can be ABF, P.P, EMC, PI, etc.;
step 5, performing hole opening treatment on the first plastic sealing layer 41 and the dielectric layer 10 through a laser drilling process to form a plurality of X-shaped through holes 411 penetrating the first plastic sealing layer 4 and the dielectric layer 10 up and down and a plurality of blind holes 412 exposing the I/O ports of the chip 3 (as shown in fig. 18);
step 7, attaching a first photosensitive film 61 to the exposed side of the first seed layer 51, and forming a patterned window on the first photosensitive film 61 by exposure and development (as shown in fig. 20);
step 9, attaching a second photosensitive film 62 on the first redistribution layer 81 near the front side of the chip 3, exposing and developing the second photosensitive film 62 to form a patterned window, and then electroplating copper deposition to obtain a third conductive post 73 (copper post) connected with the first redistribution layer 81 in the patterned window (as shown in fig. 22);
step 11, plastic packaging is performed on the third conductive column 73 and the first redistribution layer 81 positioned below the third conductive column 73 by adopting an EMC plastic packaging material to form a second plastic packaging layer 42 which coats the third conductive column 73 and the first redistribution layer 81, and grinding treatment is performed on the second plastic packaging layer 42 to expose the upper end face of the third conductive column 73 (refer to fig. 24);
step 13, removing the residual third photosensitive film 63 and etching away the exposed second seed layer 52 (refer to fig. 26);
in step 14, an oxidation preventing layer 9 is respectively plated on the surfaces of the exposed first redistribution layer 81 and the exposed second redistribution layer 82 by a nickel-palladium-gold process, so as to obtain the double-sided electroplating structure of the chip plastic package body as shown in fig. 27.
As shown in fig. 27; the double-sided electroplating structure of the chip plastic package body in the embodiment comprises:
the chip plastic package body comprises a plurality of chips 3, a first plastic package layer 41 for coating the chips 3 and dielectric layers 10 positioned on two sides of the first plastic package layer 41; the first plastic sealing layer 41 and the dielectric layer 10 are provided with a plurality of through holes 411 penetrating the first plastic sealing layer 41 and the dielectric layer 10 and a plurality of blind holes 412 exposing the I/O ports of the chip 3;
a first seed layer 51 located on the sidewall of the through hole 411, the sidewall of the blind hole 412, and both sides of the dielectric layer 10;
a first conductive post 71 filled in the via 411, a second conductive post 72 filled in the blind via 412, and a first re-wiring layer on the first seed layer 51 on both sides of the dielectric layer 10;
the first redistribution layer 81 on one side of the dielectric layer 10 is connected to the I/O port of the chip 3 through the second conductive pillar 72, and is connected to the first redistribution layer 81 on the other side through the first conductive pillar 71.
In the present invention, the number of chips 3 is at least two.
The first conductive pillars 71 of the through holes 411, the second conductive pillars 72 in the blind holes 412, and the first redistribution layer 81 on both sides of the chip plastic package are manufactured by double-sided electroplating through a pulse electroplating method, so as to realize signal interconnection and penetration between the chips 3.
Further, the through hole 411 is an X-shaped through hole, and the efficiency of double-sided electroplating and the yield of products can be improved by adopting the X-shaped through hole.
Further, the double-sided electroplating structure of the chip plastic package body further comprises:
a third conductive pillar 73, the third conductive pillar 73 being located at one side of the first redistribution layer 81 at one side of the first molding layer 41;
a second molding layer 42, wherein the second molding layer 42 is located at one side of the first redistribution layer 81 and covers the third conductive pillars 73, and an end surface of the third conductive pillars 73 is exposed to the second molding layer 42;
a second seed layer 52 located on one side of the second molding layer 42 and connected to the third conductive pillars 73, and a second redistribution layer 82 located on the second seed layer 52.
Further, the double-sided electroplating structure of the chip plastic package further comprises an oxidation preventing layer 9 with conductivity, wherein the oxidation preventing layer 9 is positioned on the exposed side of the second redistribution layer 82 and on the exposed side of the first redistribution layer 81.
It should be understood that the above description is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be apparent to those skilled in the art that various modifications, equivalents, variations, and the like can be made to the present invention. However, such modifications are intended to fall within the scope of the present invention without departing from the spirit of the present invention. In addition, some terms used in the specification and claims of the present application are not limiting, but are merely for convenience of description.
Claims (10)
1. The preparation method of the double-sided electroplating structure of the chip plastic package body is characterized by comprising the following steps of:
s10, preparing a chip plastic package body, and enabling the chip to be wrapped in a first plastic package layer;
s20, carrying out hole opening treatment on the chip plastic package body to form a through hole penetrating through the chip plastic package body and a blind hole exposing an I/O port of the chip;
s30, manufacturing a first conductive column in the through hole synchronously through double-sided electroplating, manufacturing a second conductive column in the blind hole, and manufacturing a first rewiring layer connected with the first conductive column and the second conductive column synchronously on the double sides of the chip plastic package body;
wherein, the double-sided electroplating adopts direct current electroplating or pulse electroplating.
2. The method for manufacturing a double-sided plating structure of a chip molding compound according to claim 1, wherein the through hole is an X-shaped through hole or a vertical through hole.
3. The method for manufacturing a double-sided electroplating structure of a chip plastic package according to claim 1, wherein the step S10 specifically comprises the following steps:
s10a, providing a carrier plate and a chip, and attaching the chip to the carrier plate;
s10b, adopting a plastic packaging material to carry out plastic packaging on the chip to form a first plastic packaging layer for coating the chip;
s10c, removing the carrier plate to obtain the chip plastic package body;
alternatively, the step S10 specifically includes the steps of:
s10a, providing a carrier plate and a chip, and attaching the chip to the carrier plate;
s10b, adopting a plastic packaging material to carry out plastic packaging on the chip to form a first plastic packaging layer for coating the chip;
s10c, removing the carrier plate;
and S10d, respectively preparing dielectric layers on two sides of the first plastic sealing layer to obtain the chip plastic sealing body.
4. The method for manufacturing a double-sided electroplating structure of a chip plastic package according to claim 1, wherein step S20 specifically comprises: and a through hole is formed in the chip plastic package body along the thickness direction of the chip plastic package body at a position which avoids the chip, and a blind hole which enables the I/O port to be exposed is formed in the chip plastic package body at a position which corresponds to the I/O port of the chip.
5. The method for manufacturing a double-sided electroplating structure of a chip plastic package according to claim 1, wherein the step S30 specifically comprises the following steps:
s30a, manufacturing first seed layers on the side walls of the through holes and the blind holes and on two sides of the chip plastic package body along the thickness direction of the chip plastic package body;
s30b, attaching a first photosensitive film on the first seed layers positioned on two sides of the chip plastic package body, and enabling the first photosensitive film to cover part of the first seed layers;
s30c, electroplating is synchronously carried out in the through hole, the blind hole and the first seed layers on the two sides of the chip plastic package body through double-sided electroplating, so that a first conductive column filled with the through hole, a second conductive column filled with the blind hole and a first rewiring layer which is positioned on the two sides of the chip plastic package body and connected with the first conductive column and the second conductive column are prepared.
6. The method for manufacturing a double-sided electroplating structure of a chip molding compound according to claim 5, further comprising step S40, specifically comprising the steps of:
s40a, attaching a second photosensitive film on the first rewiring layer at one side of the chip plastic package body, and enabling part of the first rewiring layer to be exposed out of the second photosensitive film;
s40b, manufacturing a third conductive column at the exposed position of the first rewiring layer through electroplating;
s40c, removing the residual first photosensitive film and the residual second photosensitive film, and etching the exposed first seed layer;
s40d, performing plastic packaging treatment on the first rewiring layer and the third conductive column by adopting plastic packaging materials to form a second plastic packaging layer which coats the first rewiring layer and the third conductive column, and enabling one end face, far away from the first rewiring layer, of the third conductive column to be exposed out of the second plastic packaging layer;
s40e, manufacturing a second seed layer on the second plastic sealing layer, and connecting the second seed layer with the third conductive column;
s40f, sticking a third photosensitive film on the second seed layer, and exposing part of the second seed layer to the third photosensitive film;
s40g, manufacturing a second redistribution layer on one side of the second seed layer exposed to the third photosensitive film through electroplating;
and S40h, removing the residual third photosensitive film and etching away the part of the second seed layer exposed out of the second redistribution layer to obtain the circuit structure.
7. The method of claim 6, further comprising the step of forming an oxidation preventing layer having conductivity on each of the exposed sides of the first and second redistribution layers S50.
8. A double-sided plating structure of a chip molding compound manufactured by the manufacturing method according to any one of claims 1 to 7, comprising:
the chip plastic package body comprises a plurality of chips and a first plastic package layer for coating the chips; the chip plastic package body is provided with a plurality of through holes penetrating through the chip plastic package body and a plurality of blind holes exposing the I/O port of the chip along the thickness direction of the chip plastic package body;
the first seed layers are positioned on the side walls of the through holes, the side walls of the blind holes and the two sides of the chip plastic package body;
the first conductive column is filled in the through hole, the second conductive column is filled in the blind hole, and the first rewiring layer is positioned on the first seed layers at two sides of the chip plastic package body;
the first rewiring layer on one side of the chip plastic package body is connected with the I/O port of the chip through the second conductive column, and is connected with the first rewiring layer on the other side through the first conductive column.
9. The dual-sided plating structure of a chip molding compound of claim 8, wherein the through-hole is an X-shaped through-hole or a vertical through-hole.
10. The double-sided plating structure of a chip molding compound of claim 8, further comprising:
the third conductive column is positioned on one side of the first rewiring layer on one side of the chip plastic package body;
the second plastic sealing layer is positioned on one side of the first rewiring layer and coats the third conductive column, and the end face of the third conductive column is exposed out of the second plastic sealing layer;
a second seed layer positioned at one side of the second plastic sealing layer and connected with the third conductive post, and a second redistribution layer positioned on the second seed layer;
and the oxidation prevention layer is positioned on one side of the second redistribution layer away from the chip plastic package body and one side of the first redistribution layer away from the second redistribution layer.
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| CN202211607885.2A CN116190246A (en) | 2022-12-14 | 2022-12-14 | Double-sided electroplating structure of chip plastic package body and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116682741A (en) * | 2023-08-01 | 2023-09-01 | 广东佛智芯微电子技术研究有限公司 | Fan-out type packaging structure of embedded chip and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116682741A (en) * | 2023-08-01 | 2023-09-01 | 广东佛智芯微电子技术研究有限公司 | Fan-out type packaging structure of embedded chip and preparation method thereof |
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