CN116169124A - Semiconductor test structure, failure positioning method and electronic equipment - Google Patents
Semiconductor test structure, failure positioning method and electronic equipment Download PDFInfo
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- CN116169124A CN116169124A CN202310171806.6A CN202310171806A CN116169124A CN 116169124 A CN116169124 A CN 116169124A CN 202310171806 A CN202310171806 A CN 202310171806A CN 116169124 A CN116169124 A CN 116169124A
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract
The invention provides a semiconductor test structure, a failure positioning method and electronic equipment. Specifically, in the test structure provided by the invention, before forming a conventional metal layer for electrically connecting and leading out a first conductive plug and a second conductive plug to a test pad, a layer of a plurality of polysilicon lines forming a gate region and the metal layers (a first metal layer and a third metal layer) respectively and electrically connecting and leading out the first conductive plugs in an active region to the upper layer in a blocking manner by taking the active region array subunit as a unit are newly added, so that after finding out the polysilicon line with short circuit through the third metal layer, only the limited first sub-metal lines in the active region corresponding to the polysilicon line are required to be tested, and the problem of short circuit between the two first conductive plugs corresponding to the active region array subunit in the active region can be accurately determined 。
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a semiconductor test structure, a failure positioning method, and an electronic device.
Background
In the semiconductor process, the manufacturing process can be divided into a front-end device process and a back-end metal interconnection process, wherein the back-end metal interconnection layer is used for leading out the front-end device for testing or working. In the semiconductor manufacturing process, in order to evaluate the design structure and monitor the process stability on the line, a complex product structure is extracted alone or the structure is used as a unit to be recombined into a repeated structure with large area and convenient for testing, a large number of corresponding electrical parameters are obtained through electrical testing of the test structures, and the electrical parameters are analyzed to find problems in advance and solve the problems, and the structure is called a test structure. The test structure is almost distributed over all layers in the manufacturing process, has various structures, and has the characteristics of easy test, easy failure analysis and the like.
In general, when performing failure analysis on a test structure, a conventional failure analysis flow includes: confirming the electrical property, positioning the failure position, and carrying out physical property analysis to find the root cause of failure; among them, the failure location is a very critical step, and at present, the means of failure location commonly used in the semiconductor industry can be roughly divided into: thermal emission microscopy (Thermal), photon radiation microscopy (EMMI), photoresistance change microscopy (OBIRCH), electron beam photoresistance change microscopy (EBIRCH), and the like.
However, as the semiconductor process technology is more advanced, the test structure used for testing is not only large in area and high in density, but also more complex, many test structures become very small in leakage caused by failure, and defects caused by failure are also very small, and in a conventional failure analysis flow, an on-line test of a common test structure is usually performed by using an on-line machine, and the test process needs to use a test pad, and if the common test structure is grinded first, manual testing needs to be performed after grinding, obviously, the former on-line test mode cannot be accurately determined to a failure position on the test structure, and the latter manual test mode increases the cost of positioning difficulty, engineering cost and the like.
Disclosure of Invention
The invention aims to provide a semiconductor test structure, a failure positioning method and electronic equipment, and aims to provide a new test structure for detecting whether leakage current exists between a grid electrode layer and a source electrode and a drain electrode in an active region, and a failure positioning method capable of accurately positioning a leakage current failure position between a grid electrode in the active region and conductive plugs positioned at two sides of the grid electrode and used for electrically connecting the source electrode and the drain electrode of the grid electrode based on the test structure, so as to finally solve the technical problems of low positioning precision, high positioning difficulty and high cost of the leakage current failure position in the prior art.
In order to solve the above technical problems, the present invention provides a semiconductor test structure, which specifically may include the following structures:
the active area comprises a plurality of active area units which are sequentially arranged at intervals along a first direction;
the grid electrode layer comprises a plurality of polysilicon lines, the polysilicon lines are sequentially arranged on the active region at intervals along a second direction perpendicular to the first direction and at least penetrate through the active region along the first direction so as to divide the active region into a plurality of active region array subunits which are arranged in a staggered mode along the first direction and the second direction;
the first conductive plugs are positioned on the active area units between the adjacent polysilicon lines, and two discrete first conductive plugs are respectively arranged on the active area unit corresponding to each active area array subunit divided into the active areas by the polysilicon lines;
the first metal layer comprises a plurality of first sub-metal wires, and each first sub-metal wire covers the surfaces of two corresponding first conductive plugs in each active area array subunit respectively;
the second metal layer comprises a plurality of second sub-metal lines, and each second sub-metal line covers the surfaces of all the first conductive plugs arranged on one active area unit along the second direction and extends to cover the other surfaces corresponding to the active area unit.
Further, the semiconductor test structure provided by the present invention may further include a plurality of first through holes, wherein the plurality of first through holes are specifically located between the first sub-metal lines and the second sub-metal lines covered on the surface thereof, for electrically connecting each of the first sub-metal lines and the second sub-metal lines corresponding thereto, respectively, and two discrete first through holes are included between each of the first sub-metal lines and the second sub-metal lines covered on the surface thereof.
Further, the semiconductor test structure provided by the invention may further include: the gate region and the active region are arranged in parallel in the direction along the first direction, and the polysilicon lines on the active region are sequentially arranged at intervals and also extend along the first direction to cover the gate region.
Further, the semiconductor test structure further includes a plurality of second conductive plugs on surfaces of the plurality of polysilicon lines extending into the gate region.
Further, the semiconductor test structure provided by the invention may further include: and the third metal layer is covered on the surface of the second conductive plug, and the fourth metal layer is covered on the surface of the third metal layer, wherein the third metal layer and the first metal layer, the fourth metal layer and the second metal layer are respectively at the same horizontal plane.
Further, the semiconductor test structure provided by the invention may further include: and the test pad is electrically connected with the first metal layer, the second metal layer, the third metal layer and the fourth metal layer respectively.
Further, the semiconductor test structure provided by the invention may further include a plurality of second through holes, where the second through holes are located on a part of the surface of the third metal layer extending along the second direction, so as to be used for electrically connecting the third metal layer and the fourth metal layer.
The second aspect is based on the same inventive concept as the semiconductor test structure provided by the present invention, and based on the test structure, the present invention further provides a failure positioning method, which is characterized in that it may at least include the following steps:
providing a planar sample having a semiconductor test structure as described above;
performing first grinding delamination treatment on the planar sample to remove a second metal layer and a fourth metal layer of the semiconductor test structure contained in the planar sample;
performing an electron beam current absorption technology or an active voltage contrast technology on the semiconductor test structure subjected to the first grinding delamination treatment to determine a first sub-metal line short-circuited with the polysilicon line;
performing a second polishing and delamination treatment on the semiconductor test structure to remove the determined first sub-metal line and expose two first conductive plugs under the first sub-metal line;
and performing morphology analysis on the plane sample or the section sample containing the two first conductive plugs exposed below the first sub-metal wire to determine the accurate position and failure mechanism of leakage failure.
Further, before the first polishing and delamination treatment is performed on the planar sample, the failure positioning method provided by the present invention may further include: and carrying out electrical failure analysis on the semiconductor test structure through the test pad.
In a third aspect, based on the same inventive concept as the failure positioning method described in the foregoing description of the present invention, the present invention further provides an electronic device, which may specifically include a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing the method steps of the failure positioning method in any one of the first aspects when executing the program stored in the memory.
In a fourth aspect, based on the same inventive concept as the failure positioning method described in the foregoing description of the present invention, the present invention further provides a computer-readable storage medium, in which a computer program is stored, which when executed by a processor, implements the method steps of the failure positioning method according to any one of the first aspects.
In a fifth aspect, based on the same inventive concept as the failure positioning method described in the above description of the present invention, the present invention also provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method steps of the failure positioning method according to any of the above first aspects.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. the invention provides a new test structure for testing whether a short circuit exists between a polycrystalline silicon grid electrode in an active region and conductive plugs (first conductive plugs) which are positioned at two sides of the polycrystalline silicon grid electrode and are used for electrically connecting a source electrode and a drain electrode, so as to cause the problem of leakage failure; specifically, in the semiconductor test structure provided by the invention, in an active region including a plurality of polysilicon lines serving as polysilicon gates and a plurality of first conductive plugs located on the active region, the active region is divided by using the polysilicon lines, so that the active region is divided into active region array subunits which are arranged in a staggered manner, then two first conductive plugs are respectively formed on the active region corresponding to each of the active region array subunits, then a first sub-metal line (the active region array subunits and the first sub-metal lines have a one-to-one correspondence), and finally a second sub-metal line is respectively arranged along the direction of each active region unit.
Obviously, in the semiconductor test structure provided by the invention, before forming the conventional metal layers (the second metal layer and the fourth metal layer) for electrically connecting the first conductive plug and the second conductive plug and leading out to the test pad, a layer of polysilicon lines for electrically connecting the gate region and the first conductive plug in the active region are newly added and formed in a manner of taking the array subunit of the active region as a unitAfter the polysilicon line with short circuit is found through the third metal layer, only the limited first sub-metal lines of the polysilicon line in the corresponding active area can be tested to accurately determine which of the active area array subunits corresponds to the two first conductive plugs with short circuit, namely, the test times and test range of the leakage failure position are reduced, the positioning accuracy of the leakage failure position is improved, and the positioning difficulty and cost are reduced 。
2. In the failure positioning method provided by the invention, the leakage failure position range can be greatly reduced by combining the Active Voltage Contrast (AVC) technology or the Electron Beam Absorption Current (EBAC) technology under the condition that the first conductive plug (namely the first metal layer) is not exposed by using the test structure provided by the invention, and the purpose of quickly and accurately determining the leakage failure position can be realized by further grinding only the reduced interval to expose the first conductive plug positioned below the reduced interval, namely, only manually testing and analyzing the area with the reduced leakage failure position range by an operator.
Drawings
FIG. 1 is a schematic diagram of a prior art layout of a test structure for determining whether a polysilicon gate and metal plugs in active regions on both sides thereof have a leakage defect due to shorting of the two;
FIG. 2 is a hotspot graph of hotspots located using an OBIRCH;
FIG. 3 is an SEM plan view of VC positioned to an anomalous first metal plug;
FIG. 4 is a SEM plan view of the results of a second electrical test for a first metal plug with a VC anomaly;
FIG. 5a is a schematic layout diagram of a semiconductor test structure including only a first conductive plug and a second conductive plug according to an embodiment of the present invention;
FIG. 5b is a schematic diagram of a layout of a test structure provided in an embodiment of the present invention, in which a first metal layer of a specific structure designed in the present invention is formed on the basis of the semiconductor test structure shown in FIG. 5 a;
FIG. 5c is a schematic layout diagram of a test structure with first and second vias formed on the structure shown in FIG. 5b according to an embodiment of the present invention;
FIG. 5d is a schematic diagram of a layout of a test structure provided in an embodiment of the present invention, wherein a second metal layer (i.e., the complete structure of a semiconductor test structure according to the present invention) is formed on the structure shown in FIG. 5 c;
fig. 6 is a flowchart illustrating a failure positioning method according to an embodiment of the present invention.
Detailed Description
As described in the background art, at present, as semiconductor process technologies are more advanced, test structures for testing are not only large in area and high in density, but also more complex, many test structures become very small in leakage caused by failure, and defects causing failure are also very small, in a conventional failure analysis flow, an on-line test of a conventional test structure is generally performed by using an on-line machine, a test pad is required in the test process, if the conventional test structure is grinded first, manual testing is required after grinding, obviously, a mode of the former on-line test cannot be accurately fixed to a failure position on the test structure, and a mode of the latter manual test after grinding increases cost of positioning difficulty, engineering cost and the like.
Fig. 1 is a schematic layout diagram of a test structure for determining whether a polysilicon gate and metal plugs in active regions on both sides thereof have a leakage defect due to shorting of the two. Wherein 100 is a polysilicon gate stripe, 120 is a first metal plug in the active region electrically connected to the active region, 130 is a second metal plug in the inactive region electrically connected to the polysilicon gate stripe 100, and 140a and 140b are metal layers for electrically connecting the first metal plug 120 and the second metal plug 130, respectively. The metal layers 140a and 140b are connected to external pads (not shown).
Currently, for the layout of the test structure shown in fig. 1, the second metal plug 130 of the polysilicon gate strip 100 is led to the test pad through the metal layer 140b, and the two first metal plugs 120 located in the active region are led to different test pads through the metal layer 140a, respectively, so as to monitor the leakage problem between the polysilicon gate strip 100 and the first metal plugs 120.
It is obvious that, in the test structure determined by the layout shown in fig. 1 in the prior art, the metal layer 140a and the metal layer 140b, which are located on the same horizontal plane, are led to different test pads, and are formed in slices in the second direction (which may also be understood as the X direction) defined by the present invention in the active area, that is, only one metal layer 140a is formed for all the areas included in each active area unit along the second direction, instead of the metal layer (the first metal layer and the third metal layer) for electrically connecting the first conductive plug and the second conductive plug and leading out to the test pad as in the semiconductor test structure provided by the present invention, a layer of a plurality of silicon lines for electrically connecting the gate region and the first conductive plug in the active area array sub-unit are formed in blocks respectively, that is, which is the design point different from the main design point proposed in the present invention.
Further in the prior art, for the test structure corresponding to the layout of fig. 1, the conventional analysis flow is to use the OBIRCH/EBIRCH gripping point first, but only the hot spot can be approximately located, for example, the size of the test structure corresponding to the test structure layout shown in fig. 1 is approximately 60um×120um, the number of polysilicon gate strips 100 and metal plugs included in the corresponding test structure is tens of thousands (approximately five hundred strips 100 and one hundred thousand strips 120), and such hot spot is not enough to find the leakage failure position at all. The measurement sample needs to be further processed to a CT layer (metal plug layer), a probe is pricked on a first metal plug of five hundred polysilicon gate strips near a hot spot by utilizing nano detection (nanoprobe) equipment, proper voltage is added on the probe, a secondary electron image is watched by using an SEM mode, and according to the principle of AVC, the first metal plug of the leakage of the polysilicon gate strips can display different voltage contrast with other first metal plugs in an SE M image, and the first metal plug of the leakage of the polysilicon gate strips is marked, so that the defect position is accurately positioned. However, the method has the advantages of large workload and low success rate, firstly, the hot spot position is inaccurate and needs to be tested for multiple times, and secondly, the contrast difference caused by VC is not obvious, and the method needs rich experience of engineers.
Taking a practical case as an example, fig. 2 is a hotspot graph of a hotspot located by using OBIRCH, in a test structure with a size of 60um x 120um, after a measured sample is ground to a metal plug layer after a distance from the edge of the structure is approximately measured, a needle of nanoprobe is pricked on a second metal plug of a polysilicon gate strip, and the AVC principle is utilized, with the hotspot as the center, and with SEM observation, repeated attempts are performed for a plurality of times until a first metal plug with VC abnormality is found. Fig. 3 is an SEM plan view of VC positioning to an anomalous first metal plug, and it can be seen that the VC difference is very weak, which is very demanding for engineers. Fig. 4 is a SEM plan view of the results of the re-electrical testing of the first metal plug for VC anomaly, showing that the first metal plug for VC anomaly did short circuit the polysilicon gate stripe, i.e., was located to the exact location where the leakage failure occurred. Next, TEM analysis is performed, and it is obvious that the failure analysis method adopted in the prior art has technical problems of great difficulty, long time consumption, high cost, difficult grasping of analysis precision, and the like.
Therefore, the invention provides a semiconductor test structure, a failure positioning method and electronic equipment, and aims to provide a new test structure for detecting whether leakage current exists between a grid layer and a source drain electrode in an active region, and a failure positioning method capable of accurately positioning the position of leakage current failure between a grid in the active region and conductive plugs positioned at two sides of the grid and used for electrically connecting the source drain electrode of the grid based on the test structure, so that the technical problems of low positioning precision, high positioning difficulty and high cost of the leakage current failure position in the prior art are finally solved.
The semiconductor test structure, the failure positioning method and the electronic equipment provided by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.
As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus. In describing embodiments of the present invention in detail, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of explanation, and the schematic drawings are only examples and should not limit the scope of the present invention herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Referring to fig. 5a to 5d, fig. 5a to 5d are schematic structural diagrams of a semiconductor test structure according to an embodiment of the present invention, in which fig. 5a is a schematic structural diagram of a test structure provided in an embodiment of the present invention, the test structure only includes a first conductive plug and a second conductive plug, and fig. 5b is a schematic structural diagram of a test structure provided in an embodiment of the present invention, in which a first metal layer of a special structure designed according to the present invention is formed on the basis of the semiconductor test structure of fig. 5 a; FIG. 5c is a schematic layout diagram of a test structure with first and second vias formed on the structure shown in FIG. 5b according to an embodiment of the present invention; fig. 5d is a schematic layout diagram of a test structure provided in an embodiment of the present invention, in which a second metal layer (i.e., a complete structure of a semiconductor test structure designed in the present invention) is formed on the structure shown in fig. 5 c.
In this embodiment of the present invention, the first direction may be understood as a Y direction, and the second direction may be understood as a second direction, where the first direction and the second direction are perpendicular to each other.
As shown in fig. 5a to 5d, the semiconductor test structure provided by the present invention may specifically include: an active region 1 including a plurality of active region units 11, the plurality of active region units 11 being sequentially arranged at intervals along a first direction;
a gate layer 12 including a plurality of polysilicon lines P1 to Pn, wherein the polysilicon lines P1 to Pn are sequentially arranged on the active region 1 at intervals along a second direction perpendicular to the first direction and at least penetrate through the active region 1 along the first direction, so as to divide the active region 1 into a plurality of active region array subunits a arranged in a staggered manner along the first direction and the second direction;
a plurality of first conductive plugs CT1 located on a plurality of active area units 11 between adjacent polysilicon lines P1 to Pn, and two discrete first conductive plugs CT1 are respectively disposed on the active area units 11 corresponding to each active area array subunit a divided into the active areas 1 by a plurality of polysilicon lines P1 to Pn;
the first metal layer M1 includes a plurality of first sub-metal lines M1.1, and each of the first sub-metal lines M1.1 covers the surfaces of two corresponding first conductive plugs CT1 in each of the active area array subcells a;
the second metal layer M2 includes a plurality of second sub-metal lines M2.2, and each of the second sub-metal lines M2.2 covers the surfaces of all the first conductive plugs CT1 disposed on one of the active area units 11 along the second direction and extends to cover the remaining surfaces corresponding to the active area units 11.
Further, referring to any of the schematic structural diagrams in fig. 5a to 5d, the semiconductor test structure provided by the present invention further includes:
the gate region 2 is arranged in parallel with the active region 1 along the first direction, and the polysilicon lines P1 to Pn sequentially arranged on the active region 1 at intervals also extend along the first direction to cover the gate region 2.
Further, referring specifically to fig. 5a, the semiconductor test structure provided by the present invention may further include a plurality of second conductive plugs CT2, where the second conductive plugs CT2 are located on the surfaces of the polysilicon lines extending into the gate region 2.
In this embodiment, the first conductive plug CT1 is mainly used for electrically guiding out the source and drain electrodes formed on each active area array subunit a in the active area 1, so as to determine whether there is leakage between the polysilicon line and the source and drain electrodes in the subsequent failure positioning analysis method, and the second conductive plug CT2 is used for electrically guiding out each polysilicon line, so as to implement electrical testing through CTI and CT 2.
Further, referring to fig. 5c in particular, the semiconductor test structure provided by the present invention may further include a plurality of first through holes Via1, in particular, the plurality of first through holes Via1 are located between the first sub-metal lines M1.1 and the second sub-metal lines M2.2 covered on the surface thereof, for electrically connecting each of the first sub-metal lines M1.1 and the second sub-metal lines M2.2 corresponding thereto, respectively, and two discrete first through holes Via1 are included between each of the first sub-metal lines M1.1 and the second sub-metal lines M2.2 covered on the surface thereof.
In this embodiment, since two first conductive plugs CT1 are formed in each of the active area array subunits a and the first sub-metal lines M1.1 are conductive, two first through holes Via1 are formed on the surface of each of the first sub-metal lines M1.1 corresponding to the two first conductive plugs CT1 for electrically and outwardly leading out the two first conductive plugs CT1, respectively, and then the second metal layer M2 is formed.
Still further, referring to fig. 5c and 5d, the gate region 2 of the semiconductor test structure according to the present invention may further include:
a third metal layer M3 covering the surface of the second conductive plug CT2 and a fourth metal layer M4 covering the surface of the third metal layer M3; and a plurality of second Via holes Via2, wherein the second Via holes Via2 are located on a part of the surface of the third metal layer M3 extending along the second direction (X direction) for electrically connecting the third metal layer M3 and the fourth metal layer M4.
Wherein the third metal layer M3 and the first metal layer M1, the fourth metal layer M4 and the second metal layer M2 are respectively at the same level.
In this embodiment, after the first conductive plug CT1 of the active region 1 and the second conductive plug CT2 of the gate region 2 are formed, a metal layer, that is, the first metal layer M1 in the active region 1 and the third metal layer M3 in the gate region 2, may be formed in both the active region 1 and the gate region 2 using a deposition process, and thus, the third metal layer M3 is in the same level as the first metal layer M1. After that, the first Via hole Via1 and the second Via hole Via2 are formed, and finally, the second metal layer M2 and the fourth metal layer M4 are formed, so that the fourth metal layer M4 and the second metal layer M2 are in the same level.
In addition, the semiconductor test structure provided by the invention can further comprise: test pads (not shown) electrically connected to the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4, respectively.
Obviously, when the semiconductor test structure provided by the invention is used for carrying out electrical test on the metal layers above M2, the test pads can be directly used for respectively carrying out on-line electrical test of each item through the first metal layer M1, the second metal layer M2 and other metal layers positioned on the first metal layer M1 and the second metal layer M2; in contrast, when the leakage failure problem caused by the short circuit exists between the polysilicon line in the active region and the first conductive plug, the semiconductor test structure provided by the invention is used for forming the conventional structureBefore the first conductive plug and the second conductive plug are electrically connected and led out to the metal layer (the second metal layer and the fourth metal layer) of the test pad, a layer of a plurality of polysilicon lines for connecting the gate region and the first conductive plugs in the active region are newly added, and are respectively and electrically connected in blocks in a mode of taking the active region array subunits as a unit and led out to the metal layer (the first metal layer and the third metal layer) on the upper layer, so that after the polysilicon line with short circuit is found out through the third metal layer, only the limited first sub-metal lines in the active region corresponding to the polysilicon line are required to be tested, the problem of short circuit of the two first conductive plugs corresponding to the active region array subunits in the active region can be accurately determined, namely, the test times and the test range of the leakage failure position are reduced, the positioning accuracy of the leakage failure position is improved, and the positioning difficulty and the cost are reduced 。
In addition, based on the semiconductor test structure corresponding to the layout shown in fig. 5a to 5d, the invention also provides a failure positioning method, and referring to fig. 6, fig. 6 is a flowchart of a failure positioning method provided in an embodiment of the invention.
As shown in fig. 6, the failure positioning method provided by the present invention at least includes the following steps:
step S601, providing a planar sample having the semiconductor test structure as described above;
step S602, performing a first polishing delamination treatment on the planar sample to remove the second metal layer and the fourth metal layer of the semiconductor test structure included in the planar sample;
step S603, performing an electron beam current absorption technique or an active voltage contrast technique on the semiconductor test structure after the first polishing delamination process to determine a first sub-metal line shorted to the polysilicon line;
step S604, further performing a second polishing and delamination process on the semiconductor test structure to remove the determined first sub-metal line and expose two first conductive plugs under the first sub-metal line;
in step S605, a topography analysis is performed on the planar sample or the cross-sectional sample containing the two first conductive plugs exposed under the first sub-metal line, so as to determine the exact location and failure mechanism of the leakage failure.
In this embodiment, a semiconductor test structure as shown in fig. 5d may be formed on a semiconductor material commonly used at present, for example, a silicon wafer, then a planar sample including the semiconductor test structure is formed, then a polishing delamination process is used to remove the second metal layer and the fourth metal layer on the top layer to expose the first through hole and the second through hole, so as to obtain a test structure corresponding to the layout shown in fig. 5c, then an electron beam absorption current technology or an active voltage contrast technology is used to perform an electrical analysis on the obtained test structure, so that a problem can be determined on the first conductive plug corresponding to the first sub-metal line through the bright spot area in the obtained image, and then a second polishing delamination process is further performed on the bright spot area to expose the first conductive plug covered under the bright spot area, and further, through a TEM planar sample analysis and a TEM cross-section sample analysis, the accurate position and failure of the transmission failure mechanism can be accurately determined.
In summary, 1, the present invention provides a new test structure for testing whether there is a short circuit between a polysilicon gate and conductive plugs (first conductive plugs) located on two sides of the polysilicon gate for electrically connecting source and drain electrodes in an active area, so as to cause leakage failure; specifically, in the semiconductor test structure provided by the invention, in an active region including a plurality of polysilicon lines serving as polysilicon gates and a plurality of first conductive plugs located on the active region, the active region is divided by using the polysilicon lines, so that the active region is divided into active region array subunits which are arranged in a staggered manner, then two first conductive plugs are respectively formed on the active region corresponding to each of the active region array subunits, then a first sub-metal line (the active region array subunits and the first sub-metal lines have a one-to-one correspondence), and finally a second sub-metal line is respectively arranged along the direction of each active region unit.
Obviously, in the semiconductor test structure provided by the invention, before the conventional metal layers (the second metal layer and the fourth metal layer) for electrically connecting and leading out the first conductive plug and the second conductive plug to the test pad are formed, a layer of a plurality of polysilicon lines forming a gate region and the first conductive plugs in the active region are respectively and electrically connected and led out to the metal layers (the first metal layer and the third metal layer) on the upper layer in a blocking manner by taking the active region array subunit as a unit is newly added, so that after the polysilicon lines with short circuit can be found through the third metal layer, only the limited first sub-metal lines in the active region corresponding to the polysilicon lines can be tested, the problem of short circuit of the two first conductive plugs corresponding to the active region array subunit in the active region can be accurately determined, namely, the test times and the test range of the leakage failure position are reduced, the positioning difficulty and the positioning failure cost are improved 。
2. In the failure positioning method provided by the invention, the leakage failure position range can be greatly reduced by combining the Active Voltage Contrast (AVC) technology or the Electron Beam Absorption Current (EBAC) technology under the condition that the first conductive plug (namely the first metal layer) is not exposed by using the test structure provided by the invention, and the purpose of quickly and accurately determining the leakage failure position can be realized by further grinding only the reduced interval to expose the first conductive plug positioned below the reduced interval, namely, only manually testing and analyzing the area with the reduced leakage failure position range by an operator.
In addition, the embodiment of the invention also provides electronic equipment which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus,
a memory for storing a computer program;
and the processor is used for realizing the method steps of the failure positioning method when executing the program stored in the memory.
For a specific implementation of each step of the method, reference may be made to the method embodiment shown in fig. 6, and details are not described herein.
In addition, other implementation manners of the application setting method implemented by the processor executing the program stored in the memory are the same as those mentioned in the foregoing method embodiment section, and will not be described herein again.
In yet another embodiment of the present invention, a computer readable storage medium is provided, where a computer program is stored, and the computer program implements the steps of the failure positioning method described above when executed by a processor.
In yet another embodiment of the present invention, a computer program product comprising instructions that, when executed on a computer, cause the computer to perform the failure location method described above is also provided.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g.,), or a semiconductor medium (e.g., solid state disk SolidStateDisk (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the apparatus, user terminal, computer readable storage medium and computer program product embodiments, the description is relatively simple, as it is substantially similar to the method embodiments, and relevant places are referred to in the section of the method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A semiconductor test structure, comprising:
the active area comprises a plurality of active area units which are sequentially arranged at intervals along a first direction;
the grid electrode layer comprises a plurality of polysilicon lines, the polysilicon lines are sequentially arranged on the active region at intervals along a second direction perpendicular to the first direction and at least penetrate through the active region along the first direction so as to divide the active region into a plurality of active region array subunits which are arranged in a staggered mode along the first direction and the second direction;
the first conductive plugs are positioned on the active area units between the adjacent polysilicon lines, and two discrete first conductive plugs are respectively arranged on the active area unit corresponding to each active area array subunit divided into the active areas by the polysilicon lines;
the first metal layer comprises a plurality of first sub-metal wires, and each first sub-metal wire covers the surfaces of two corresponding first conductive plugs in each active area array subunit respectively;
the second metal layer comprises a plurality of second sub-metal lines, and each second sub-metal line covers the surfaces of all the first conductive plugs arranged on one active area unit along the second direction and extends to cover the other surfaces corresponding to the active area unit.
2. The semiconductor test structure of claim 1, further comprising a plurality of first vias between the first sub-metal lines and the second sub-metal lines covered on the surface thereof for electrically connecting each of the first sub-metal lines and the second sub-metal lines corresponding thereto, respectively, and two discrete first vias are included between each of the first sub-metal lines and the second sub-metal lines covered on the surface thereof.
3. The semiconductor test structure of claim 1, wherein the semiconductor test structure further comprises: the gate region and the active region are arranged in parallel in the direction along the first direction, and the polysilicon lines on the active region are sequentially arranged at intervals and also extend along the first direction to cover the gate region.
4. The semiconductor test structure of claim 3, further comprising a plurality of second conductive plugs on a surface of the plurality of polysilicon lines extending into the gate region.
5. The semiconductor test structure of claim 4, wherein the semiconductor test structure further comprises: and the third metal layer is covered on the surface of the second conductive plug, and the fourth metal layer is covered on the surface of the third metal layer, wherein the third metal layer and the first metal layer, the fourth metal layer and the second metal layer are respectively at the same horizontal plane.
6. The semiconductor test structure of claim 5, wherein the semiconductor test structure further comprises: and the test pad is electrically connected with the first metal layer, the second metal layer, the third metal layer and the fourth metal layer respectively.
7. The semiconductor test structure of claim 5, further comprising a plurality of second vias on a portion of a surface of the third metal layer extending in the second direction for electrically connecting the third metal layer and a fourth metal layer.
8. The failure positioning method is characterized by comprising the following steps of:
providing a planar sample having the semiconductor test structure of any one of claims 1-7;
performing first grinding delamination treatment on the planar sample to remove a second metal layer and a fourth metal layer of the semiconductor test structure contained in the planar sample;
performing an electron beam current absorption technology or an active voltage contrast technology on the semiconductor test structure subjected to the first grinding delamination treatment to determine a first sub-metal line short-circuited with the polysilicon line;
performing a second polishing and delamination treatment on the semiconductor test structure to remove the determined first sub-metal line and expose two first conductive plugs under the first sub-metal line;
and performing morphology analysis on the plane sample or the section sample containing the two first conductive plugs exposed below the first sub-metal wire to determine the accurate position and failure mechanism of leakage failure.
9. The failure localization method of claim 8, wherein prior to the first polishing delamination process on the planar sample, the failure localization method further comprises: and carrying out electrical failure analysis on the semiconductor test structure through the test pad.
10. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for implementing the method steps of the failure positioning method according to any one of claims 8 to 9 when executing a program stored on a memory.
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