CN116169089A - Method for forming STI structure - Google Patents

Abstract

The application discloses a method for forming an STI structure, which comprises the following steps: forming a groove in the substrate, wherein the groove is annular in a top view; forming a linear oxide layer on the substrate and the groove; forming a hard mask layer on the substrate except the trench; forming an oxide layer, wherein the oxide layer fills the groove; flattening to remove the oxide layer, the hard mask layer and the linear oxide layer outside the groove, wherein the linear oxide layer and the oxide layer in the groove form an STI structure; the planarization process comprises a first stage and a second stage, wherein the polishing speed in the first stage is higher than that in the second stage, and the progress of the planarization process is monitored by the EPD technology in the process of the planarization process. According to the planarization treatment method and device, planarization treatment is carried out through the two-stage CMP process in the forming process of the STI structure, and the problem of unstable EPD grabbing caused by high-speed grinding is solved because the grinding speed in the second stage is greater than that in the second stage.

Description

Method for forming STI structure

Technical Field

The present disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a method for forming an STI structure.

Background

In the semiconductor integrated circuit fabrication industry, shallow trench isolation (shallow trench isolation, STI) structures can act as insulating isolation structures between Active Areas (AA) of semiconductor devices. Generally, the method of forming the STI structure includes: forming a Hard Mask (HM) layer on a substrate, etching by a photolithography process, forming annular grooves in the hard mask layer and the substrate from a top view, forming an oxide layer to fill the grooves, and performing planarization treatment on the oxide layer to form the STI structure.

In the related art, in the process of forming the STI structure, planarization is performed by a chemical mechanical planarization (chemical mechanical planarization, CMP) process, in the CMP process, the progress of the process is monitored by an end-point detect (EPD) technique, and the EPD technique uses the principle that the friction between different materials and the polishing pad of the CMP machine is different when polishing, so that the driving current of the machine is different, and in the process, the rotation speed of the machine is constant, the friction is increased, and the driving current is also increased. In the planarization of STI structures of some products (e.g., complementary metal oxide semiconductor (CIS) image sensor (complementary metal oxide semiconductor contact image sensor) devices), the planarization process is performed by a high-voltage (HD) CMP process.

However, the polishing rate of the planarization process by the HD CMP process is high, which results in unstable EPD gripping, easy gripping failure, abnormal film thickness, and even scratching of the wafer, and in EPD data with successful gripping, gaps exist in the polishing time between the wafers, which results in unstable EPD gripping, and differences in thickness between the wafers after polishing.

Disclosure of Invention

The application provides a method for forming an STI structure, which can solve the problem that data grabbing failure is easily caused by monitoring a process through an EPD technology due to a higher grinding speed in a planarization process in the method for forming the STI structure, and comprises the following steps:

forming a trench in a substrate, the trench being annular in shape from a top view;

forming a linear oxide layer on the substrate and the groove;

forming a hard mask layer on the substrate except the trench;

forming an oxide layer, wherein the oxide layer fills the groove;

flattening, namely removing the oxide layer, the hard mask layer and the linear oxide layer outside the groove, wherein the linear oxide layer and the oxide layer in the groove form an STI structure;

the planarization process comprises a first stage and a second stage, wherein the polishing speed in the first stage is larger than that in the second stage, and the progress of the planarization process is monitored through an EPD technology in the process of performing the planarization process.

In some embodiments, the first stage is planarized by an HD CMP process.

In some embodiments, the second stage is planarized by an LD CMP process.

In some embodiments, the forming a liner oxide layer over the substrate and the trench includes:

and forming the linear oxide layer on the substrate and the groove through a furnace tube oxidation process.

In some embodiments, the hard mask layer comprises a silicon nitride layer.

In some embodiments, the forming an oxide layer includes:

the oxide layer is formed by depositing a silicon dioxide layer by an HDP CVD process.

In some embodiments, the method is applied in the fabrication of CIS.

The technical scheme of the application at least comprises the following advantages:

in the forming process of the STI structure, after the oxide layer is filled in the groove, planarization treatment is carried out through a two-stage CMP process, and the grinding speed in the second stage is higher than that in the second stage, so that the problem of unstable EPD grabbing caused by high-speed grinding is solved, the consistency of product grinding is improved, and the yield of products is improved to a certain extent.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a method for forming an STI structure according to an exemplary embodiment of the present application;

fig. 2 to 5 are schematic views illustrating the formation of STI structures according to an exemplary embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.

Referring to fig. 1, a flow chart of a method for forming an STI structure according to an exemplary embodiment of the present application is shown, and as shown in fig. 1, the method may be applied to manufacture of a CIS, and the method includes:

in step S1, a trench is formed in a substrate, and the trench is annular in a plan view.

And S2, forming a linear oxide layer on the substrate and the groove.

Referring to fig. 2, a schematic cross-sectional view after formation of a linear oxide layer is shown. Illustratively, as shown in fig. 2, a trench 300 is formed in the substrate 210, the trench 300 is annular (which may be circular, elliptical, or rectangular annular) in a top view, a region surrounded by the trench 300 may be an active region of a CIS (which is used to form a cell device or a photodiode), and a linear oxide layer 221 may be formed on the substrate 210 and the trench 300 by a furnace tube oxidation process.

And step S3, forming a hard mask layer on the substrate except the groove.

Referring to fig. 3, a schematic cross-sectional view after forming a hard mask layer is shown. Illustratively, as shown in fig. 3, the hard mask layer 230 may include a silicon nitride (SiN) layer, step S3 including, but not limited to: the hard mask layer 230 is formed by depositing a silicon nitride layer through a chemical vapor deposition (chemical vapor deposition, CVD) process, removing the hard mask layer 230 on the surface of the trench 300 through a photolithography process, and leaving the hard mask layer 230 on the substrate 210 except for the trench 300.

And S4, forming an oxide layer, wherein the oxide layer fills the groove.

Referring to fig. 4, a schematic cross-sectional view after formation of an oxide layer is shown. Illustratively, as shown in FIG. 4, silicon dioxide (SiO) may be deposited by a high density plasma chemical vapor deposition (high density plasma chemical vapor deposition, HDP CVD) process ₂ ) The layers form an oxide layer 222, the oxide layer 222 filling the trench 300.

And S5, carrying out planarization treatment, namely removing the oxide layer, the hard mask layer and the linear oxide layer outside the groove, wherein the linear oxide layer and the oxide layer in the groove form an STI structure, the planarization treatment comprises a first stage and a second stage, the polishing speed in the first stage is higher than that in the second stage, and the progress of the planarization treatment is monitored by an EPD technology in the planarization treatment process.

Referring to fig. 5, a schematic cross-sectional view after planarization is performed. Illustratively, as shown in fig. 5, after the planarization process, the oxide layer 222, the hard mask layer 230, and the linear oxide layer 221 outside the trench 300 are removed, and the linear oxide layer 221 and the oxide layer 222 inside the trench 300 form an STI structure.

The first stage performs planarization by HD CMP, and the second stage performs planarization by low-voltage (LD) CMP.

In summary, in the embodiment of the present application, after the oxide layer is filled in the trench in the process of forming the STI structure, the planarization process is performed by the CMP process of two stages, and since the polishing speed in the second stage is greater than that in the second stage, the problem of unstable EPD gripping caused by high-rate polishing is solved, the uniformity of product polishing is improved, and the yield of products is improved to a certain extent.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (7)

1. A method for forming an STI structure, comprising:

forming a trench in a substrate, the trench being annular in shape from a top view;

forming a linear oxide layer on the substrate and the groove;

forming a hard mask layer on the substrate except the trench;

forming an oxide layer, wherein the oxide layer fills the groove;

flattening, namely removing the oxide layer, the hard mask layer and the linear oxide layer outside the groove, wherein the linear oxide layer and the oxide layer in the groove form an STI structure;

the planarization process comprises a first stage and a second stage, wherein the polishing speed in the first stage is larger than that in the second stage, and the progress of the planarization process is monitored through an EPD technology in the process of performing the planarization process.

2. The method of claim 1, wherein the first stage is planarized by an HD CMP process.

3. The method of claim 2, wherein the second stage is planarized by an LD CMP process.

4. The method of claim 3, wherein forming a liner oxide layer over the substrate and trench comprises:

and forming the linear oxide layer on the substrate and the groove through a furnace tube oxidation process.

5. The method of claim 4, wherein the hard mask layer comprises a silicon nitride layer.

6. The method of claim 5, wherein forming an oxide layer comprises:

the oxide layer is formed by depositing a silicon dioxide layer by an HDP CVD process.

7. The method according to claim 6, wherein the method is applied in the production of CIS.

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