CN1161571A

CN1161571A - Method of fabricating insulating layer with anti-reflecting layer

Info

Publication number: CN1161571A
Application number: CN 96118968
Authority: CN
Inventors: 冈田纪雄
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1995-12-04
Filing date: 1996-12-04
Publication date: 1997-10-08

Abstract

A method of manufacturing a semiconductor comprises the following steps. An insulating film 5 is deposited to cover a metallized interconnection 2 and a semiconductor substrate 1, and the insulating film is covered with an antireflection coating 10. Photoresist 11 is applied to the entire antireflection coating 10. With the photoresist 11 used as a mask, the insulating film 5 and the antireflection coating 10 are subjected selectively to anisotropic etching.

Description

The manufacture method of the insulating barrier of band anti-reflecting layer

The present invention relates to the manufacture method of interlayer insulating film, particularly band is as the manufacture method of the insulating barrier of the anti-reflecting layer that multilayer wiring is set.

In recent years, along with the growth that large scale integrated circuit (LS1) miniaturization is needed, become more and more important with the groove Wiring technique at the groove wiring technique that semiconductor substrate surface forms groove and wiring is set in groove inside, just must form the high accuracy interlayer dielectric in order to form the high accuracy groove.Here, become problem by the aluminium alloy that high light reflectivity is arranged as metal line.Japan special permission disclose flat 4-372157 and has disclosed the technology that antireflecting coating prevents that metal line is reflective is set on metal line, therefore, prevent to expose as the photoresist mistake of mask.Followingly the disclosed formation step that groove distributes of burying is described with reference to Fig. 8 to Figure 14.

Fig. 8 is a process chart, with metallochemistry vapor deposition method (below be called metal CVD), on Semiconductor substrate 1, form the 1st layer of metal line of forming by aluminium alloy etc. 2, form antireflecting coating 4 with barrier metal silicide, TiN etc. on the 1st layer of metal line 2, make mask with photoresist and select to remove the 1st layer of metal line 2 and antireflecting coating 4, then, on whole surface, form SiO ₂Deng interlayer dielectric 3.Subsequently, carry out chemical mechanical polishing (hereinafter referred to as CMP), make its complanation with the abrasive pastes that contain silica dioxide granule.

Then, as shown in Figure 9, photoresist is selected exposure, make mask with it, selective etching metal line 2 and antireflecting coating 3.

Then, as shown in figure 10, form SiO ₂Deng layer dielectric film 5, then, to its CMP, therefore, make surface planarization with the abrasive pastes that contain silica dioxide granule.

Then, as shown in figure 11, on the whole surface of layer dielectric film 5, form photoresist 6, with mask 7 it is selected exposure subsequently.

After this, as shown in figure 12, make mask selective etching layer dielectric film 5 with photoresist 6.

And, in order to improve the adhesive strength of metal line 2 and anti-reflection coating 3 and the cover layer metal line 9 that forms, on whole surface, form the adhesive linkage 8 of Ti/TiN and so on, metal line 9 forms by burying technology later on, it is formed on the whole surface, as shown in figure 13.

At last, as shown in figure 14, to metal line 9 and adhesive linkage 8 complanations, finish the groove burial wiring with CMP.

But, forming the groove burial wiring and can produce following problem, the light that is used to expose also passes the side of metal line 2, makes to want exposed areas 6a regional 6b in addition also to expose.

This be because, metal line 2 does not have such coating by the antireflecting coating 3 that forms it on its side, and, promptly use the fabulous anisotropic etch of selectivity, can not obtain accurate geometry vertical side edge yet.As a result, be used in of the hypotenuse reflection of the light of exposure, and use initial its regional 6b that is exposed that prevents that covers of mask to be exposed from metal line 2, the result, the interlayer dielectric 5a that keeps has been removed, and the width that makes metal line 9 is greater than design load, and with the adjacent wire short circuit.

For overcoming above-mentioned defective, the objective of the invention is, provide a usefulness to prevent and make the method for high accuracy multilayer wiring from the offside reflection light of metal line.

For realizing goal of the invention, the invention provides the manufacture method of semiconductor equipment, comprise the following steps:

On the dielectric film that forms, form antireflecting coating, to cover the step of Semiconductor substrate;

On antireflecting coating, form the step of photoresist;

The step that selection exposes and removes to photoresist;

Therefore, owing to form antireflecting coating on layer dielectric film, the unwanted part of layer dielectric film is not corroded, the present invention can not add other step and make high accuracy groove burial wiring.

Fig. 1 is explanation forms processing step by the burial wiring layer of embodiments of the invention a profile;

Fig. 2 is explanation forms processing step by the burial wiring layer of another embodiment of the present invention a profile;

Fig. 3 is explanation forms processing step by the burial wiring layer of another embodiment of the present invention a profile;

Fig. 4 is explanation forms processing step by the burial wiring layer of another embodiment of the present invention a profile;

Fig. 5 is explanation forms processing step by the burial wiring layer of another an embodiment of the present invention profile;

Fig. 6 is explanation forms processing step by the burial wiring layer of another embodiment of the present invention a profile;

Fig. 7 is explanation forms processing step by the burial wiring layer of another embodiment of the present invention a profile;

Fig. 8 is the profile of explanation by the formation processing step of the burial wiring layer of prior art;

Fig. 9 is explanation forms processing step by another routine burial wiring layer of prior art a profile;

Figure 10 is explanation forms processing step by the burial wiring layer of the another example of prior art a profile;

Figure 11 is explanation forms processing step by the burial wiring layer of the another example of prior art a profile;

Figure 12 is explanation forms processing step by the burial wiring layer of the another example of prior art a profile;

Figure 13 be explanation by prior art again the burial wiring layer of an example form the profile of processing step;

Figure 14 is explanation forms processing step by the burial wiring layer of the another example of prior art a profile;

Referring now to Fig. 1 to Fig. 7, embodiments of the invention is described.

At first, as shown in Figure 1, on the whole surface of Semiconductor substrate 1, form metal line 2 as the 1st wiring layer.And on metal line 2, form photoresist layer 4 as mask.

Then, as shown in Figure 2, photoresist 4 is selected exposure and removed it, make mask with photoresist 4, selectively the anisotropic etch metal line 2.

Then as shown in Figure 3, form as SiO with methods such as bias voltage ECR ₂The layer dielectric film 5 of interlayer insulating film, for example, SiO ₂And Si ₃N ₄Film, the about 2.2 μ m of its thickness.Make its whole surface and Semiconductor substrate 1 of covering metal wire 2, the abrasive pastes CMP processing layer dielectric film 5 with containing silica dioxide granule makes its thickness reduce to 1.5 μ m.After with the CMP planarization process, on the whole surface of layer dielectric film 5, form the TiN film of the thick 250 orders of magnitude as antireflecting coating 10 with sputter or CVD method.

Then, as shown in Figure 4, on the whole surface of antireflecting coating 10, form the thick photoresist 11 of several thousand dusts, select exposure with 7 pairs of photoresists of mask 11.

Subsequently, as shown in Figure 5, make mask, to dielectric film 5 and antireflecting coating 10 anisotropic etch selectively, with to layer dielectric film 5 flutes with photoresist.

After this, as shown in Figure 6, sputter refractory metal for example TiN and Ti forms the metal wiring layer 11 that thickness is respectively 1000 and the 3000 orders of magnitude, then, forms metal line 9 with CuCVD and inserts in the groove as the 2nd wiring layer.

At last, as shown in Figure 7, for basic abrasive pastes carry out CMP, continue to remove adhesive linkage 11 and interlayer dielectric 5 on antireflecting coating 10 and the metal line 9, only stay the copper metal line 9 in the groove, finish the groove burial wiring in order to aluminium oxide.

According to said method, on interlayer dielectric 5, form antireflecting coating 10, on antireflecting coating 10, form photoresist,, thereby can prevent from the rayed photoresist 11 of the offside reflection of metal line 2 owing to light reflects fully from antireflecting coating 10.And because the side of metal line 2 is not reflective, therefore, photoresist can overexposure, guarantees to form burial wiring by design size, prevents the adjacent wire short circuit.In addition, need not carry out the step that on metal line, forms antireflecting coating that prior art requires.The method that substitutes is, must carry out forming on layer dielectric film the step of antireflecting coating, thereby, needn't increase the quantity of processing step, just can form the high accuracy burial wiring.

The processing step of the 2nd wiring layer that is provided as burial wiring more than has been described.Press Fig. 1 to substantially the same step shown in Figure 7, carry out step shown in Figure 7 again, make the another kind of configuration that wherein has as the 3rd wiring layer of burial wiring.But, as shown in Figure 7, complanation has been carried out on its surface with CMP, therefore needn't after forming, interlayer dielectric shown in Figure 35 carry out CMP again.

Here, although form the 2nd metal wiring layer with copper CVD by present embodiment.Also can use aluminium CVD, methods such as reflow sputter or high temperature sputter form the 2nd metal wiring layer.In addition, although the SiO that forms with bias voltage ECR ₂Oxide-film is as interlayer dielectric, and much less, other CVD oxide-film also can be as layer dielectric film, and in addition, although form the metal line tack coat with TiN/Ti, other thin-film material also can be used, as long as can prevent electromigration and stress migration safely.

As mentioned above, form antireflecting coating on the interlayer insulating film owing to be used in, the part that do not need of layer dielectric film is not corroded, the present invention does not increase other step can constitute high accuracy groove burial wiring, and price almost equates with prior art manufactured goods price.

Claims

The preparation method of 1 semiconductor equipment may further comprise the steps:

On Semiconductor substrate, selectively form the step of the 1st metal line;

Form the step of the dielectric film that covers the 1st metal line and described Semiconductor substrate;

Form the step of antireflecting coating on the described dielectric film;

Form the step of photoresist on the described antireflecting coating;

Described photoresist is selected step of exposing;

Make mask with the photoresist of selecting exposure, select to remove described antireflecting coating and described dielectric film.
2 by the methods of claim 1, also comprise the step that forms the adhesive linkage of strong bond to described the 1st metal line, select to remove described layer dielectric film after, in abutting connection with the bottom and the side of remainder.
3 methods by claim 2 also comprise after described layer dielectric film removed in selection forming the step that the 2nd metal line is filled remaining space on described adhesive linkage.
The manufacture method of 4 semiconductor equipments in the groove that cuts in the dielectric film that forms, has burial wiring on Semiconductor substrate, may further comprise the steps:

For covering Semiconductor substrate, on the dielectric film that forms, form the step of antireflecting coating;

Form the step of photoresist on the described antireflecting coating;

The step of selecting exposure and removing photoresist;

Make mask with photoresist, select to remove described dielectric film and described antireflecting coating, the step of grooving in described dielectric film;

Form wiring to fill the step of described groove.
The manufacture method of 5 semiconductor equipments may further comprise the steps:

On Semiconductor substrate, form the step of insulating barrier; With

On described insulating barrier, form the step of antireflecting coating.
6 methods by claim 5 is characterized in that, form the described anti-reflecting layer that covers described insulating barrier fully.
7 methods by claim 5 also are included in the step that forms the photoresist layer on the described anti-reflecting layer.
8 methods by claim 5 also comprise:

Form the step of conductive layer on the described Semiconductor substrate; After this on described conductive layer, form described exhausted layer.
9 methods by claim 5 also comprise:

Form the step of photoresist on the described antireflecting coating.
10 methods by claim 9 also comprise:

Photoresist is selected step of exposing.
11 methods by claim 10 also comprise with the photoresist of described selection exposure and make the step that mask selects to remove described dielectric film and described antireflecting coating.