CN116155266A - Circuit with clock and data recovery circuit - Google Patents

Circuit with clock and data recovery circuit Download PDF

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Publication number
CN116155266A
CN116155266A CN202211161300.9A CN202211161300A CN116155266A CN 116155266 A CN116155266 A CN 116155266A CN 202211161300 A CN202211161300 A CN 202211161300A CN 116155266 A CN116155266 A CN 116155266A
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clock signal
signal
phase
ssc
generate
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高健凯
卓宜贤
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MediaTek Inc
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MediaTek Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/7073—Direct sequence modulation synchronisation

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

The present invention provides a circuit comprising a Phase Locked Loop (PLL) and a CDR circuit, wherein the CDR circuit comprises a phase detector, a loop filter, an SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal having SSC modulation and an SSC direction signal. The phase detector is used for comparing phases of an input signal and an output clock signal to generate a detection result, wherein the input signal has SSC modulation. The loop filter is used for filtering the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is used for generating control codes according to the filtered signals and the control signals so as to control the phase interpolator to adjust the phase of the clock signals to generate output clock signals. With this scheme, the static phase error between the input signal and the output clock signal can be reduced.

Description

Circuit with clock and data recovery circuit
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a clock and data recovery circuit with a spread spectrum clock synthesizer.
Background
In a digital based clock and data recovery (clock and data recovery, CDR) circuit of a serializer/deserializer (SerDes) having a spread spectrum clock (spread spectrum clocking, SSC), the CDR circuit receives an input signal from a previous stage and a reference clock signal to generate an output clock signal, wherein the reference clock signal is typically from a phase locked loop (Phase Locked Loop, PLL) of a transmitter of the SerDes. However, since a near-end (SSC) used in the reference clock signal is different from a far-end (far-end) SSC used in the input signal, there is a residual static phase error between the input signal and the output clock signal, thereby degrading the receiver performance.
Disclosure of Invention
It is therefore an object of the present invention to provide a CDR circuit with small static phase error between an input signal and an output clock signal, so as to solve the above-mentioned problems.
According to one embodiment of the invention, a circuit is disclosed that includes a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector (phase detector), a digital loop filter (digital loop filter), an SSC demodulator, a control code generator, and a phase interpolator (phase interpolator). The PLL is configured to generate a first clock signal having SSC modulation and an SSC direction signal. The phase detector is configured to compare a phase of an input signal with a phase of an output clock signal to generate a detection result, wherein the input signal has SSC modulation. The digital loop filter is configured to filter the detection result to produce a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code based on the filtered signal and the control signal. The phase interpolator is configured to adjust a phase of the first clock signal using the control code to generate an output clock signal.
According to one embodiment of the invention, a circuit is disclosed that includes a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a digital loop filter, a first phase interpolator, and a second phase interpolator. The PLL is configured to generate a first clock signal and a control signal having SSC modulation. The phase detector is configured to generate a detection result from an input signal and an output clock signal, wherein the input signal has SSC modulation. The digital loop filter is coupled to the phase detector for filtering the detection result to generate a filtered signal. The first phase interpolator is used for generating an output clock signal according to the filtered signal and the first clock signal. The second phase interpolator is used for eliminating SSC of the first clock signal or eliminating SSC component contributed by the first clock signal in the output clock signal according to the control signal.
Wherein the second phase interpolator is located between the phase detector and the first phase interpolator, the second phase interpolator is configured to adjust a phase of an output clock signal to generate an adjusted output clock signal, and the phase detector is configured to compare the phase of an input signal with the phase of the adjusted output clock signal to generate a detection result. Alternatively, the second phase interpolator is located between the PLL and the first phase interpolator, and the second phase interpolator is configured to adjust the phase of the first clock signal to produce a second clock signal, and the first phase interpolator is configured to adjust the phase of the second clock signal based on the filtered signal to produce the output clock signal.
The circuit provided by the application can reduce static phase errors between an input signal and an output clock signal.
These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures and the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a CDR circuit according to one embodiment of the present invention.
Fig. 2 shows a timing diagram of SSC direction signals, TXSSC, and related signals in accordance with one embodiment of the present invention.
Fig. 3 shows that the static phase error is halved.
FIG. 4 is a schematic diagram of a CDR circuit according to one embodiment of the present invention.
FIG. 5 is a schematic diagram of a CDR circuit according to one embodiment of the present invention.
Detailed Description
Certain terms are used throughout the following description and claims to refer to particular system components. As will be appreciated by those skilled in the art, manufacturers may refer to a component by different names. This application is not intended to distinguish between components that differ in name but not function. In the following description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to … …". The term "coupled" is intended to mean either an indirect electrical connection or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 1 is a schematic diagram of a CDR circuit 100 according to one embodiment of the present invention. As shown in fig. 1, CDR circuit 100 is a phase interpolator (phase interpolator, PI) based CDR circuit that includes a phase detector (in this embodiment, binary phase detector (bang-bang phase detector, BBPD) 110), a frequency converter 120, a digital loop filter 130, an SSC demodulator 140, a control code generator 150, and a phase interpolator 160. In this embodiment, CDR circuit 100 is used in a SerDes with SSC for high speed communication.
In operation of CDR circuit 100, BBPD 110 receives an input signal (digital input signal) Din from a previous stage and compares the phase of input signal Din with the phase of output clock signal CKout to produce a detection result, wherein input signal Din has SSC modulation, which may indicate phase information between input signal Din and output clock signal CKout (e.g., the phase of input signal Din leads the phase of output clock signal CKout, or the phase of input signal Din lags the phase of output clock signal CKout). The frequency converter 120 is an optional component, and the frequency converter 120 converts the frequency of the detection result to another frequency. Then, the digital loop filter 130 filters the detection result to generate a filtered signal to the control code generator 150, and the control code generator 150 generates a control code. Then, the phase interpolator 160 adjusts the phase of the clock signal CK1 using the control code generated by the control code generator 150 to generate the output clock signal CKout. Further, each of the clock signal CK1 and the output clock signal CKout may be a single-phase clock signal or a clock signal having a plurality of phases.
It should be noted that the operations of the BBPD 110, the frequency converter 120, the digital loop filter 130, and the phase interpolator 160 are known to those skilled in the art, and the present embodiment focuses on the SSC demodulator 140 and the control code generator 150, so the following description focuses on the SSC demodulator 140, and details of other components are omitted here.
In this embodiment, the PLL 102 of the transmitter generates the clock signal CK1 using the reference clock signal CKREF, wherein the clock signal CK1 is SSC modulated. Ideally, the SSC amplitude of the input signal Din is the same as the SSC amplitude of the clock signal CK 1. However, due to the frequency drift and the differential design method, the frequency and SSC amplitude of the input signal Din are not the same as those of the clock signal CK1, and a residual static phase error may exist between the input signal Din and the output clock signal CKout. Specifically, assuming that CDR circuit 100 uses a second order loop to track SSC, the static phase error between input signal Din and output clock signal CKout can be expressed as:
Figure BDA0003859259940000041
where "s" is the complex frequency parameter of the Laplace transform (Laplace transform), G(s) is the loop gain, and "A" is a constant, related to SSC amplitude. To suppress static phase errors, CDR circuit 100 includes SSC demodulator 140 to reduce the value "a" in the above equation.
The SSC demodulator 140 receives a SSC direction signal SSC dir from PLL 102, where SSC direction signal SSC dir indicates the direction of the frequency variation. Taking fig. 2 as an example, "TXSSC" represents the frequency of the clock signal CK1, wherein the frequency of the clock signal CK1 varies between a specific frequency (e.g., 5 GHz) and (1 ppm to 10000 ppm). Notably, the SSC amplitude provided herein is for illustration purposes, and in other embodiments, the SSC amplitude can be any other suitable value, such as 5000ppm. The SSC direction signal SSC dir may be a square wave in which a high level indicates that the frequency of the clock signal CK1 is decreasing and a low level indicates that the frequency of the clock signal CK1 is increasing. After receiving the SSC direction signal SSC dir, the SSC synthesizer within the SSC demodulator 140 can generate a control signal Vc having information of the SSC amplitude and frequency information opposite to the frequency of the TXSSC, wherein the synthesized SSC waveform of fig. 2 shows a frequency opposite to the frequency of the TXSSC. For example, in the first period T1, the frequency of the clock signal CK1 is changed from 5GHz to (1 ppm to 10000 ppm) 5GHz, and the ssc demodulator 140 may generate a control signal having information indicating the opposite direction (e.g., the opposite direction of the change in frequency or phase); in the second period T2, the frequency of the clock signal CK1 is changed from (1 ppm-10000 ppm) x 5GHz to 5GHz, and the ssc demodulator 140 may generate a control signal having information indicating the opposite direction.
In one embodiment, the SSC demodulator 140 can analyze the SSC direction signal SSC dir to generate frequency information of the clock signal CK1 and convert the frequency information to generate phase information of the clock signal CK1, wherein the phase information of the clock signal CK1 indicates that the phase of the clock signal CK1 will move forward or backward. The SSC demodulator 140 can then use the phase information to generate a control signal or the control code generator 150 can use the phase information to generate a control code.
The control code generator 150 receives the filtered signal from the digital loop filter 130 and the control signal from the SSC demodulator 140 to generate a control code to the phase interpolator 160 to adjust the phase of the clock signal CK1 to generate the output clock signal CKout. In the present embodiment, since the control code contains information of opposite directions of the frequency/phase change of the clock signal CK1, the SSC component of the clock signal CK1 can be eliminated by the phase interpolator 160, and the influence of the clock signal CK1 on the output clock signal CKout is close to that of the clock signal without spreading. For example, in the first period T1 shown in fig. 2, the frequency of the clock signal CK1 is decreasing, so the SSC demodulator 140 can generate a control signal, and the component of the control code contributed by the control signal is used by the phase interpolator 160 to advance the phase of the clock signal CK 1. Similarly, in the second period T2 shown in fig. 2, the frequency of the clock signal CK1 is increasing, so the SSC demodulator 140 can generate a control signal, and the component of the control code contributed by the control signal is used by the phase interpolator 160 to delay the phase of the clock signal CK 1.
Referring to fig. 3, the SSC amplitude is halved by eliminating the SSC component of the clock signal CK1 using the SSC demodulator 140 and the control code generator 150 to generate the output clock signal CKout, and the value "a" in the above equation is also reduced such that the static phase error is reduced by 50%. As shown in fig. 3, before the present application is used, the frequency difference between the input signal Din and the output clock signal CKout is 20000ppm. By using the SSC demodulator 140, the frequency difference between the input signal Din and the output clock signal CKout is 10000ppm or (-10000 ppm), and the SSC that the CDR circuit 100 needs to track is only a far-end SSC (i.e., the SSC of the input signal Din).
Fig. 4 is a schematic diagram of CDR circuit 400 according to one embodiment of the present invention. As shown in fig. 4, CDR circuit 400 is a PI-based CDR circuit that includes a phase detector (BBPD 410 in this embodiment), a frequency converter 420, a digital loop filter 430, and two phase interpolators 440 and 450. In the present embodiment, the CDR circuit 400 is used in a SerDes with SSC for high-speed communication.
In operation of CDR circuit 400, BBPD 410 receives an input signal (digital input signal) Din from a previous stage and compares the phase of input signal Din with the phase of output clock signal CKout to produce a detection result, wherein input signal Din has SSC modulation, which may indicate phase information between input signal Din and output clock signal CKout (e.g., the phase of input signal Din leads the phase of output clock signal CKout, or the phase of input signal Din lags the phase of output clock signal CKout). The frequency converter 420 is an optional component, and the frequency converter 420 converts the frequency of the detection result to another frequency. The digital loop filter 430 then filters the detection result to produce a filtered signal. Then, the phase interpolator 440 adjusts the phase of the clock signal CK1 using the filtered signal to generate the clock signal CK2, wherein the clock signal CK2 is used by the phase interpolator 450 to generate the output clock signal CKout. Further, each of the clock signal CK1, the clock signal CK2, and the output clock signal CKout may be a single-phase clock signal or a clock signal having a plurality of phases.
It should be noted that the operations of the BBPD 410, the frequency converter 420, the digital loop filter 430, and the phase interpolator 460 are known to those skilled in the art, and the present embodiment focuses on the phase interpolator 450, so the following description focuses on the phase interpolator 450, and details of other components are omitted here.
In this embodiment, the PLL 402 of the transmitter generates the clock signal CK1 using the reference clock signal CKREF, wherein the clock signal CK1 is SSC modulated. Ideally, the SSC amplitude of the input signal Din is the same as the SSC amplitude of the clock signal CK 1. However, due to the frequency drift and the differential design method, the frequency and the SSC amplitude of the input signal Din are not the same as those of the clock signal CK1, and a residual static phase error exists between the input signal Din and the output clock signal CKout, wherein the static phase error can be referred to the above equation (1).
In the present embodiment, since the clock signal CK1 has SSC modulation, the clock signal CK2 (which may also be referred to as an output clock signal before adjustment) generated by the phase interpolator 440 also has SSC modulation. To eliminate the SSC contributed by CK1 in the clock signal CK2, the PLL 402 generates a control signal Vc to the phase interpolator 450 to adjust the phase of the clock signal CK2 to generate an output clock signal, wherein the control signal Vc contains information about the opposite direction of the frequency/phase change of the clock signal CK 1. For example, in the first period T1 shown in fig. 2, the frequency of the clock signal CK1 is falling, and thus the PLL 402 may generate the control signal Vc to control the phase interpolator 450 to advance the phase of the clock signal CK 2. Similarly, in the second period T2 shown in fig. 2, the frequency of the clock signal CK1 is rising, and thus the PLL 402 can generate the control signal Vc to control the phase interpolator 450 to delay the phase of the clock signal CK 2.
In summary, by using the interpolator 450 to cancel the SSC component contributed by CK1 in the clock signal CK2 to generate the output clock signal CKout, the effect of CK1 on the clock signal CKout approaches that of the clock signal without spreading, SSC amplitude is halved, and the value "a" in the above equation (1) is also reduced, such that the static phase error is reduced by 50%. Furthermore, by using the interpolator 450, the SSC that the cdr circuit 400 needs to track is only a far-end SSC (i.e., the SSC of the input signal Din).
Fig. 5 is a schematic diagram of a CDR circuit 500 according to one embodiment of the present invention. As shown in fig. 5, CDR circuit 500 is a PI-based CDR circuit, including a phase detector (BBPD 510 in this embodiment), a frequency converter 520, a digital loop filter 530, and a phase interpolator 540. In the present embodiment, CDR circuit 500 is used in SerDes with SSC for high speed communication.
In operation of CDR circuit 500, BBPD 510 receives an input signal (digital input signal) Din from a previous stage and compares the phase of input signal Din with the phase of output clock signal CKout to produce a detection result, wherein input signal Din has SSC modulation, which may indicate phase information between input signal Din and output clock signal CKout (e.g., the phase of input signal Din leads the phase of output clock signal CKout, or the phase of input signal Din lags the phase of output clock signal CKout). The frequency converter 520 is an optional component, and the frequency converter 520 converts the frequency of the detection result to another frequency. The digital loop filter 530 then filters the detection result to produce a filtered signal. Then, the phase interpolator 540 adjusts the phase of the clock signal CK2 using the filtered signal to generate the output clock signal CKout. Further, each of the clock signal CK1, the clock signal CK2, and the output clock signal CKout may be a single-phase clock signal or a clock signal having a plurality of phases.
It should be noted that the operations of the BBPD 510, the frequency converter 520, the digital loop filter 530, and the phase interpolator 540 are well known to those skilled in the art, and the generation of the clock signal CK2 is emphasized in this embodiment, so the following description focuses on the phase interpolator 504, and details of other components are omitted here.
In this embodiment, the PLL 502 of the transmitter generates the clock signal CK1 using the reference clock signal CKREF, wherein the clock signal CK1 has SSC modulation. Ideally, the SSC amplitude of the input signal Din is the same as the SSC amplitude of the clock signal CK 1. However, due to the frequency drift and the differential design method, the frequency and the SSC amplitude of the input signal Din are not the same as those of the clock signal CK1, and a residual static phase error exists between the input signal Din and the output clock signal CKout, wherein the static phase error can be referred to the above equation (1).
In this embodiment, to eliminate the SSC of the clock signal CK1, the PLL 502 generates a control signal Vc to the phase interpolator 504 to adjust the phase of the clock signal CK1 to generate the clock signal CK2, wherein the control signal Vc includes information of the opposite direction of the frequency/phase change of the clock signal CK 1. For example, in the first period T1 shown in fig. 2, the frequency of the clock signal CK1 is falling, and thus the PLL 502 may generate the control signal Vc to control the phase interpolator 504 to advance the phase of the clock signal CK 1. Similarly, in the second period T2 shown in fig. 2, the frequency of the clock signal CK1 is rising, and thus the PLL 502 can generate the control signal Vc to control the phase interpolator 504 to delay the phase of the clock signal CK 1.
In summary, by eliminating the SSC of the clock signal CK1 using the interpolator 504 to generate the clock signal CK2, the SSC amplitude is halved and the value "a" in the above equation (1) is also reduced such that the static phase error is reduced by 50%. Furthermore, by using the interpolator 504, the SSC that the cdr circuit 500 needs to track is only the far-end SSC (i.e., the SSC of the input signal Din).
While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.
Those skilled in the art will readily observe that modifications and alterations of the apparatus and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the scope and metes of the appended claims.

Claims (11)

1. A circuit, comprising:
a phase locked loop for generating a first clock signal having Spread Spectrum Clock (SSC) modulation and a SSC direction signal; and
a Clock and Data Recovery (CDR) circuit comprising:
a phase detector for comparing a phase of an input signal with a phase of an output clock signal to generate a detection result, wherein the input signal has SSC modulation;
a digital loop filter coupled to the phase detector for filtering the detection result to generate a filtered signal;
the SSC demodulator is used for receiving the SSC direction signal and generating a control signal according to the SSC direction signal;
a control code generator for generating a control code based on the filtered signal and the control signal; and
and a phase interpolator for receiving the first clock signal and adjusting a phase of the first clock signal using the control code to generate the output clock signal.
2. The circuit of claim 1, wherein the SSC direction signal indicates a direction of frequency variation of the first clock signal and the control signal includes information of an opposite direction of frequency variation of the first clock signal.
3. The circuit of claim 2, wherein the SSC direction signal being a first voltage level indicates that the frequency of the first clock signal is rising; and the SSC direction signal being at a second voltage level indicates that the frequency of the first clock signal is decreasing.
4. The circuit of claim 1 wherein the phase interpolator uses the control code to cancel the SSC component of the first clock signal to produce the output clock signal.
5. The circuit of claim 1, wherein in response to the SSC direction signal indicating that the frequency of the first clock signal is decreasing, a component of the control code contributed by the control signal is used by the phase interpolator to advance the phase of the first clock signal to generate the output clock signal.
6. The circuit of claim 1, wherein in response to the SSC direction signal indicating that the frequency of the first clock signal is rising, a component of the control code contributed by the control signal is used by the phase interpolator to delay the phase of the first clock signal to generate the output clock signal.
7. The circuit of claim 1, wherein the SSC demodulator analyzes the SSC direction signal to obtain phase information of the first clock signal, wherein the phase information is used by the SSC demodulator to generate the control signal or the phase information is used by the control code generator to generate the control code.
8. A circuit, comprising:
a phase locked loop for generating a first clock signal having Spread Spectrum Clock (SSC) modulation and a control signal; and
a Clock and Data Recovery (CDR) circuit comprising:
a phase detector for generating a detection result from an input signal and an output clock signal, wherein the input signal has SSC modulation;
a digital loop filter coupled to the phase detector for filtering the detection result to generate a filtered signal;
a first phase interpolator for generating an output clock signal from the filtered signal and the first clock signal; and
and the second phase interpolator is used for eliminating SSC components of the first clock signal or eliminating SSC components contributed by the first clock signal in the output clock signal according to the control signal.
9. The circuit of claim 8, wherein the second phase interpolator is located between the phase detector and the first phase interpolator, the second phase interpolator is configured to receive the output clock signal, adjust a phase of the output clock signal based on the control signal to generate an adjusted output clock signal, and the phase detector is configured to compare the phase of the input signal and the phase of the adjusted output clock signal to generate the detection result.
10. The circuit of claim 8, wherein the second phase interpolator is located between the PLL and the first phase interpolator, and wherein the second phase interpolator is configured to receive the first clock signal, adjust a phase of the first clock signal based on the control signal to produce a second clock signal, and wherein the first phase interpolator is configured to adjust a phase of the second clock signal based on the filtered signal to produce the output clock signal.
11. A circuit according to claim 9 or 10, wherein the control signal comprises information of opposite direction of the frequency variation of the first clock signal.
CN202211161300.9A 2021-11-23 2022-09-22 Circuit with clock and data recovery circuit Pending CN116155266A (en)

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US17/902,917 2022-09-05
US17/902,917 US12003245B2 (en) 2022-09-05 Clock and data recovery circuit with spread spectrum clocking synthesizer

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