WO2006137030A1 - Phase-locked loop systems using static phase offset calibration - Google Patents

Phase-locked loop systems using static phase offset calibration Download PDF

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Publication number
WO2006137030A1
WO2006137030A1 PCT/IB2006/052017 IB2006052017W WO2006137030A1 WO 2006137030 A1 WO2006137030 A1 WO 2006137030A1 IB 2006052017 W IB2006052017 W IB 2006052017W WO 2006137030 A1 WO2006137030 A1 WO 2006137030A1
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WO
WIPO (PCT)
Prior art keywords
signal
phase
configured
error
static
Prior art date
Application number
PCT/IB2006/052017
Other languages
French (fr)
Inventor
Benedykt Mika
Ragu Sridhar
Ron Osgood
Rohini Abhyankar
Amrita Deshpande
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US69277205P priority Critical
Priority to US60/692,772 priority
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2006137030A1 publication Critical patent/WO2006137030A1/en

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Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation

Abstract

Consistent with one example embodiment, a phase-locked loop circuit (100) includes a phase detector (110) configured to compare the phase of a reference signal (172) and an input signal (105), and configured to provide an error signal (112, 114) in response to a difference in phase between the reference signal and the input signal. A static phase offset detector (180) is configured to receive the error signal and provide a static phase offset signal (186). A charge pump (120) is configured to sum the error signal and the static phase offset signal, and provide a charge signal (126). A loop filter (130) is configured to filter the charge signal and provide a loop filter signal (128). A voltage controlled oscillator (160) is configured to receive the loop filter signal and provide an output signal (162). And a divider (170) is configured to receive the output signal and divide the output signal, thereby providing the reference signal.

Description

PHASE-LOCKED LOOP SYSTEMS USING STATIC PHASE OFFSET CALIBRATION

The present invention relates generally to phase-locked loops and, more particularly, to phase locked loops using static phase offset calibration. A phase-locked loop (PLL) is a circuit that generates a periodic output signal having a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. PLL designers often have a major challenge with regard to the simultaneous achievement of fine output resolution (narrow channel spacing), fast lock time, and low jitter. This can be particularly difficult because the low loop bandwidth needed to reduce jitter and improve loop stability phase margin increases PLL locking time.

A PLL is typically used to generate an output signal after acquiring the frequency and the phase of an input signal for purposes of synchronization. Although the frequency of the output signal is ultimately locked onto the frequency of the input signal, there exists a static phase offset, also known as static offset error, between the input signal and the output signal. A Phase Frequency Detector (PFD) is used to compare the phase error and frequency between the input and output signals. The trains of the pulses generated by the PFD are proportional to the phase error and provided to a charge pump, the output of which is integrated in a loop filter, whose output controls a Voltage-Controlled Oscillator (VCO). The VCO generates the periodic output signal. If the clock edges from the VCO

(called the feedback edges) fall behind those of the input signal, the phase comparator causes the charge pump to change the control voltage, so that the oscillator speeds up. Likewise, if the feedback edges creep ahead of those of the reference clock, the phase comparator causes the charge pump to change the control voltage to slow down the oscillator. The low-pass filter smoothes out the abrupt control inputs from the charge pump, so that the system tends towards a state where the phase detector makes very few corrections.

PLLs may also include a divide by N circuit between the VCO and the feedback input to the phase comparator. The divide by N circuit sends through one out of every N pulses (N being an integer), where N is usually programmable. The effect of the divide by N circuit is that when the PLL locks, the VCO is going N times faster than the reference clock.

A PLL with a bang-bang charge pump supplies current pulses with fixed total charge, either positive or negative, to a capacitor acting as a low pass filter. A phase comparator for a bang-bang charge pump must always have a dead band where the phases of the reference and feedback clocks are close enough that the detector fires either both or neither of the charge pumps, for no total effect. Bang-bang control systems are simple, but are associated with significant minimum peak-to-peak jitter, because once in lock the phase offset hunts between the two extrema values of the dead band.

One desirable property of digital PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.

Another desirable property of digital PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called supply and substrate noise rejection. One challenge to the operation of phase-locked loops involves the fast locking onto an input signal over a wide bandwidth with precise tracking after lock is achieved, along with low static phase offset and jitter, and high substrate noise rejection. These and other limitations present challenges to the implementation of phase-locked loops.

Various aspects of the present invention are directed to methods and arrangements for locking the phase of an output signal to the phase of an input signal in a manner that addresses and overcomes the above-mentioned issues.

Consistent with one example embodiment, the present invention is directed to a phase-locked loop circuit having a detection circuit configured to provide an error signal in response to the input signal and feedback from the output signal, and configured to provide a static phase offset signal that indicates a static phase difference between the input signal and the feedback from the output signal. A control circuit is configured to maintain the output signal in a phase-locked relationship with the input signal as a function of the error signal and the static phase offset signal.

Consistent with another example embodiment, the present invention is directed to a phase-locked loop circuit having a phase detector configured to compare the phase of a reference signal and an input signal, and configured to provide an error signal in response to a difference in phase between the reference signal and the input signal. A static phase offset detector is configured to receive the error signal and provide a static phase offset signal. A charge pump is configured to sum the error signal and the static phase offset signal, and provide a charge signal. A loop filter is configured to filter the charge signal and provide a loop filter signal. A voltage controlled oscillator is configured to receive the loop filter signal and provide an output signal. And a divider is configured to receive the output signal and divide the output signal, thereby providing the reference signal.

Consistent with a further example embodiment, a method for reducing the static phase error between an input signal and an output signal in a phase-locked loop involves determining a phase error between the input signal and the output signal, the phase error indicated by a phase error up signal and a phase error down signal. A static phase offset is determined using the phase error up signal and the phase error down signal, the static phase offset indicated by a static offset error up signal and a static offset error down signal. The phase error up signal and the static offset error up signal, and the phase error down signal and the static offset error down signal, are summed in a charge pump of the phase-locked loop to reduce the static offset between the input and output signals. The above summary of the present invention is not intended to describe each embodiment or every implementation of the present invention. Advantages and attainments, together with a more complete understanding of the invention, will become apparent and appreciated by referring to the following detailed description and claims taken in conjunction with the accompanying drawings. The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:

FIG. 1 is block diagram of a phase locked loop using static phase offset calibration, according to an example embodiment of the present invention; FIG. 2 is a flow chart illustrating a method of reducing static phase error in a PLL according to an example embodiment of the present invention; and

FIG. 3 is block diagram of a memory module having a phase locked loop using static phase offset calibration according to an example embodiment of the present invention. While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

The present invention is believed to be applicable to a variety of circuits and approaches involving electronic communications, frequency multiplication, frequency tracking, signal synthesis, and other approaches using active feedback and/or control.

While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.

PLL frequency synthesizers are important building blocks in communication and computing systems. Frequency translation in radio -frequency (RF) transceiver circuits and clock generation in computing systems both typically use accurate, high performance PLL systems. One desirable property of digital PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. Consistent with one example embodiment, a phase-locked loop circuit includes a phase detector configured to compare the phase of a reference signal and an input signal, and configured to provide an error signal in response to a difference in phase between the reference signal and the input signal. A static phase offset detector is configured to receive the error signal and provide a static phase offset signal. A charge pump is configured to sum the error signal and the static phase offset signal, and provide a charge signal. A loop filter is configured to filter the charge signal and provide a loop filter signal. A voltage controlled oscillator is configured to receive the loop filter signal and provide an output signal. And a divider is configured to receive the output signal and divide the output signal, thereby providing the reference signal. A simplified PLL block diagram is shown in Figure 1, illustrating a PLL system 100 including a primary loop 150 and a secondary loop 140 in accordance with the present invention. The primary loop 150 is an example embodiment of a PLL, and the secondary loop 140 provides static phase offset calibration to the PLL in accordance with the present invention. The primary loop 150 includes a phase frequency detector (PFD) 110, a charge pump 120, a low pass filter (LPF) 130, a voltage controlled oscillator 160, and a frequency divide circuit 170.

The secondary loop 140 includes a static phase offset detector 180, a LPF 182 and a voltage to current converter (V-I) 184. The PFD 100 is configured to compare the phase of a reference signal 172 and an input signal 105, and configured to provide an up-error signal 112 and a down-error signal 114 in response to a difference in phase between the reference signal 172 and the input signal 105. Static phase offset detector 180 is configured to receive the error signals 112, 114 and provide a static phase offset signal 186, which may be filtered through a LPF 182 and converted from a voltage signal to a current signal using the V-I 184. The static phase offset detector 180 may be implemented, for example, using a high frequency XOR function in one implementation, or using two symmetrical high frequency counters with an overflow terminal connected to the PFD. The LPF 182 may be implemented, for example, using passive RC circuitry. The charge pump 120 is configured to sum the error signals 112, 114 and the static phase offset signal 186, and provide a charge signal 126. The charge pump 120 includes an up-summer 122 and a down-summer 124. The static phase offset signal 186 is separated into a static phase up portion 187 and a static phase down portion 188, and summed with the up-error signal 112 and the down-error signal 114 respectively using the up-summer 122 and the down-summer 124. The up-summer 122 and the down-summer 124 may be implemented on a line 123, 125 respectively of the charge pump 120, the lines 123, 125 receiving the current from the charge pump 120 up and down sources, as well as the current from the static phase up portion 187 and the static phase down portion 188 respectively. The LPF 130 is configured to filter the charge signal 126 and provide a loop filter signal 128. The VCO 160 is configured to receive the loop filter signal 128 and provide an output signal 162. The divider circuitry 170 is configured to receive the output signal 162 and divide the output signal, thereby providing the reference signal 172.

Referring now to Figure 2, a method 200 of reducing the static phase error between an input signal and an output signal in a phase-locked loop in accordance with an example embodiment involves determining a phase error 210 between the input signal and the output signal, the phase error indicated by a phase error up signal and a phase error down signal. A static phase offset 220 is determined using the phase error up signal and the phase error down signal, the static phase offset indicated by a static offset error up signal and a static offset error down signal. The phase error up signal and the static offset error up signal are summed 230, and the phase error down signal and the static offset error down signal are summed 240 in the charge pump of the phase-locked loop. Summing the static offset error up and down signals in the charge pump provides for calibration of the static phase error in accordance with the present invention. The static phase error is improved without the use of delay circuitry in the primary PLL feedback loop, thereby eliminating a noise source within the primary loop, while improving the static phase offset.

Figure 3 is block diagram of a memory module 300 having a phase locked loop 320 using static phase offset calibration according to an example embodiment of the present invention. The memory module 300 includes memory 310 clocked by the output of the phase-locked loop 320. The phase locked loop 320 receives a clock-in signal 330 from a backplane 340, which is part of a computer 350 with a processor 360. Use of the phase- locked loop 320 in accordance with the present invention provides a self-calibrating frequency doubling clock generator that does not require programmable delay circuitry in the phase-locked loop 320 feedback circuitry, thereby improving performance capabilities of the memory module 300.

The various embodiments described above and shown in the figures are provided by way of illustration only and should not be construed to limit the invention. Based on the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the present invention without strictly following the exemplary embodiments and applications illustrated and described herein. For instance, applications other than frequency multiplication may be amenable to implementation using similar approaches. In addition, one or more of the above example embodiments and implementations may be implemented with a variety of approaches, including digital and/or analog circuitry and/or software-based approaches. The above example embodiments and implementations may also be integrated with a variety of circuits, devices, systems and approaches including those for use in connection with memory transfer, communications, guidance control, and frequency tracking. These approaches are implemented in connection with various example embodiments of the present invention. Such modifications and changes do not depart from the true scope of the present invention that is set forth in the following claims.

Claims

CLAIMS What is claimed is:
1. A phase-locked loop circuit (100) providing an output signal (162) that is phase-locked to an input signal (105), the circuit comprising: a detection circuit (110, 140) configured to provide an error signal (112, 114) in response to the input signal and feedback from the output signal, and configured to provide a static phase offset signal (186) that indicates a static phase difference between the input signal and the feedback from the output signal; and a control circuit (110, 120, 130, 160, 170) configured to maintain the output signal in a phase-locked relationship with the input signal as a function of the error signal and the static phase offset signal.
2. The circuit of claim 1 , wherein the control circuit comprises a charge pump (120) configured to sum the error signal and the static phase offset signal.
3. The circuit of claim 1, wherein the control circuit comprises a voltage controlled oscillator (160) configured to adjust the frequency of the output signal in accordance with the function of the error signal and the static phase offset signal.
4. The circuit of claim 1 , wherein the control circuit comprises a voltage controlled oscillator configured to multiply the frequency of the input signal, and wherein the feedback from the output signal is coupled through a divider circuit (170) to the detection circuit.
5. A phase-locked loop circuit (100) comprising: a phase detector (110) configured to compare the phase of a reference signal (172) and an input signal (105), and configured to provide an error signal (112, 114) in response to a difference in phase between the reference signal and the input signal; a static phase offset detector (180) configured to receive the error signal and provide a static phase offset signal (186); a charge pump (120) configured to sum the error signal and the static phase offset signal, and provide a charge signal (126); a loop filter (130) configured to filter the charge signal and provide a loop filter signal (128); a voltage controlled oscillator (160) configured to receive the loop filter signal and provide an output signal (162); and a divider (170) configured to receive the output signal and divide the output signal, thereby providing the reference signal (172).
6. The circuit of claim 5, wherein the static phase offset detector is configured to adjust the error signal in response to a temperature change of the phase-locked loop circuit.
7. The circuit of claim 5, wherein the static phase offset detector is configured to continuously adjust the static phase offset signal in response to continuous sensing of the error signal.
8. The circuit of claim 5, wherein the phase-locked loop is configured to reduce static offset error without using a programmable delay of the reference signal.
9. The circuit of claim 5, wherein the phase-locked loop circuit is used in a dual in-line memory module.
10. The circuit of claim 5, wherein the phase-locked loop circuit is used in a double data rate dual in-line memory module.
11. A memory module configured to store data in a computing environment, the memory module comprising: a clock- in signal comprising a signal frequency; and a phase- locked loop circuit coupled to the clock- in signal and configured to double the signal frequency of the clock- in signal thereby providing a frequency doubled clock signal, the phase-locked loop circuit comprising: a phase detector configured to compare the phase of a reference signal and the clock- in signal, and configured to provide an error signal in response to a difference in phase between the reference signal and the input signal; a static phase offset detector configured to receive the error signal and provide a static phase offset signal; a charge pump configured to sum the error signal and the static phase offset signal, and provide a charge signal; a loop filter configured to filter the charge signal and provide a loop filter signal; a voltage controlled oscillator configured to receive the loop filter signal and provide the frequency doubled clock signal; and a divider configured to divide the frequency doubled clock signal in half, thereby providing the reference signal.
12. The circuit of claim 11 , wherein the static phase offset detector is configured to adjust the error signal in response to a temperature change of the phase-locked loop circuit.
13. The circuit of claim 11, wherein the static phase offset detector is configured to continuously adjust the static phase offset signal in response to continuous sensing of the error signal.
14. The circuit of claim 11 , wherein the phase-locked loop is configured to reduce static offset error without using a programmable delay of the reference signal.
15. A method for reducing the static phase error between an input signal and an output signal in a phase-locked loop, comprising: determining a phase error between the input signal and the output signal, the phase error indicated by a phase error up signal and a phase error down signal; determining a static phase offset using the phase error up signal and the phase error down signal, the static phase offset indicated by a static offset error up signal and a static offset error down signal; summing the phase error up signal and the static offset error up signal in a charge pump of the phase-locked loop; and summing the phase error down signal and the static offset error down signal in the charge pump of the phase- locked loop.
16. The method of claim 15, comprising adjusting the static phase offset in response to a temperature change of the phase-locked loop circuit.
17. The method of claim 15, comprising continuously adjusting the static phase offset in response to continuously determining the phase error.
PCT/IB2006/052017 2005-06-21 2006-06-21 Phase-locked loop systems using static phase offset calibration WO2006137030A1 (en)

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US60/692,772 2005-06-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101867368A (en) * 2009-04-20 2010-10-20 索尼公司 Clock data recovery circuit and multiplied-frequency clock generation circuit

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US6043715A (en) * 1997-09-02 2000-03-28 Lucent Technologies Inc. Phase-locked loop with static phase offset compensation
US20010015677A1 (en) * 2000-02-07 2001-08-23 Samsung Electronics Co., Ltd. Phase locked loop for stable clock generation in applications of wide band channel clock recovery and operation method thereof
US6385265B1 (en) * 1998-08-04 2002-05-07 Cypress Semiconductor Corp. Differential charge pump
US6466078B1 (en) * 2001-05-04 2002-10-15 Cypress Semiconductor Corp. Reduced static phase error CMOS PLL charge pump
US6611161B1 (en) * 2001-11-06 2003-08-26 National Semiconductor Corporation Charge pump circuit for a high speed phase locked loop

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Publication number Priority date Publication date Assignee Title
US6043715A (en) * 1997-09-02 2000-03-28 Lucent Technologies Inc. Phase-locked loop with static phase offset compensation
US6385265B1 (en) * 1998-08-04 2002-05-07 Cypress Semiconductor Corp. Differential charge pump
US20010015677A1 (en) * 2000-02-07 2001-08-23 Samsung Electronics Co., Ltd. Phase locked loop for stable clock generation in applications of wide band channel clock recovery and operation method thereof
US6466078B1 (en) * 2001-05-04 2002-10-15 Cypress Semiconductor Corp. Reduced static phase error CMOS PLL charge pump
US6611161B1 (en) * 2001-11-06 2003-08-26 National Semiconductor Corporation Charge pump circuit for a high speed phase locked loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101867368A (en) * 2009-04-20 2010-10-20 索尼公司 Clock data recovery circuit and multiplied-frequency clock generation circuit

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