CN116154064A - High-light-efficiency light-emitting diode epitaxial wafer, preparation method and LED - Google Patents
High-light-efficiency light-emitting diode epitaxial wafer, preparation method and LED Download PDFInfo
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract
The invention provides a high-light-efficiency light-emitting diode epitaxial wafer, a preparation method and an LED, comprising a substrate, and a composite buffer layer, a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer which are sequentially deposited on the substrate; wherein the composite buffer layer comprises a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer which are sequentially deposited on the substrate, wherein the first buffer layer is SiO 2 A layer of AlO as the second buffer layer a N 1‑a A third buffer layer of Al b Ga 1‑b O c N 1‑c The invention improves the light extraction efficiency of the light-emitting diode, reduces the defect density of the GaN epitaxial layer, improves the crystal quality of the GaN epitaxial layer, reduces the non-radiative recombination efficiency of defects and improvesLuminous efficiency of the light emitting diode.
Description
Technical Field
The invention belongs to the technical field of light-emitting diode epitaxial wafers, and particularly relates to a high-light-efficiency light-emitting diode epitaxial wafer, a preparation method and an LED.
Background
Group III nitrides are used in blue light, ultraviolet light emitting systems, and the structures of gallium nitride (GaN), aluminum nitride (AlN) and wurtzite of indium nitride (InN) form a continuous alloy system with direct band gaps ranging from 1.9 eV of indium nitride to 3.4 eV of gallium nitride to 6.2 eV of aluminum nitride, so that group III nitrides are largely formed into optical devices with application wavelengths extending from red to ultraviolet, which have higher radiation resistance characteristics than GaAs and Si, and which correspond to a wider application space.
The light efficiency of the GaN light emitting diode mainly comprises two parts, namely Light Extraction Efficiency (LEE) and Internal Quantum Efficiency (IQE), the internal quantum efficiency of the GaN blue light emitting diode is already more than 70%, so the light efficiency is mainly limited by the light extraction efficiency, a GaN or AlN layer with a certain thickness is generally grown on a substrate in advance at a lower temperature, the larger the refractive index difference of materials is, the smaller the critical angle of total reflection is, the angle of total reflection at the interface of air/sapphire and sapphire/AlN is the smallest, namely the probability of total reflection at the place is the largest, the probability of light escape is smaller, and the luminous efficiency of the light emitting diode is reduced.
At present, a low-temperature AlN layer and a GaN layer are generally adopted as a buffer layer, the crystal quality is poor, most of the buffer layer is made of amorphous or polycrystalline materials, light absorption is easy, the total reflection angle of an air/sapphire interface and a sapphire/AlN interface is minimum, namely, the probability of total reflection of light at the buffer layer is maximum, the probability of light escape is smaller, and the luminous efficiency of the light-emitting diode is further reduced.
Disclosure of Invention
In order to solve the technical problems, the invention provides a high-light-efficiency light-emitting diode epitaxial wafer, a preparation method and an LED.
In a first aspect, an embodiment of the present invention provides a high light efficiency light emitting diode epitaxial wafer, including a substrate, and a composite buffer layer, a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer sequentially deposited on the substrate;
wherein the composite buffer layer comprises a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer which are sequentially deposited on the substrate, wherein the first buffer layer is SiO 2 A layer of AlO as the second buffer layer a N 1-a A third buffer layer of Al b Ga 1-b O c N 1-c And the fourth buffer layer is a GaN layer.
Compared with the prior art, the beneficial effects of this application are: siO of the present invention 2 The layers can effectively improve the light extraction efficiency, and due to the different refractive indexes of the materials of the epitaxial layers, the total reflection phenomenon is very easy to occur in the epitaxial layer structure, so that the light extraction efficiency of the LED is reduced, the refractive index of the sapphire substrate is n=1, the refractive index of the air is 1.81, the total reflection angle of the sapphire/air interface is 33 degrees, the light emitted by the LED has small escape probability, and SiO 2 Refractive index of layer 1.47, siO 2 The total reflection angle of the air interface is 43 DEG, compared with the sapphire/air interface, the probability of light escape is much higher, the light extraction efficiency of the light emitting diode is improved, and the deposited AlO is formed a N 1-a Layer and Al b Ga 1-b O c N 1-c The layer, through introducing O atom and Ga atom, can on one hand reduce the lattice mismatch of substrate and GaN epitaxial layer effectively, release the stress that deposits the epitaxial layer and accumulate, on the other hand GaN epitaxial layer transition refractive index 2.43 to AlO a N 1-a Refractive index of layer 2 to SiO 2 The refractive index of the layer is 1.47, effectively reducing GaN and Al b Ga 1-b O c N 1-c layer/AlO a N 1-a layer/SiO 2 Light rays of adjacent interfaces of the layers are totally reflected, the light emitting efficiency of the buffer layer is improved, the finally deposited GaN layer provides a nucleation center with the same orientation as the substrate, the stress generated by lattice mismatch between the GaN epitaxial layer and the substrate and the thermal stress generated by thermal expansion coefficient mismatch are released,further growth provides a smooth nucleation surface, the contact angle of nucleation growth is reduced, so that island-shaped GaN grains can be connected into a plane in a smaller thickness, the island-shaped GaN grains are converted into two-dimensional epitaxial growth, the crystal quality of a GaN epitaxial layer is improved, the non-radiative recombination efficiency of defects is reduced, and the luminous efficiency of the light-emitting diode is improved.
Preferably, the SiO 2 The thickness of the layer ranges from 10nm to 50nm, and the AlO a N 1-a The thickness of the layer ranges from 10nm to 100nm, and the Al b Ga 1-b O c N 1-c The thickness range of the layer is 10 nm-100 nm, and the thickness range of the GaN layer is 10 nm-100 nm.
Preferably, the AlO a N 1-a The component of O in the layer ranges from 0.01 to 0.5, and the Al b Ga 1-b O c N 1-c The Al component of the layer ranges from 0.01 to 0.5, and the O component ranges from 0.01 to 0.5.
Preferably, the first semiconductor layer comprises an undoped GaN layer and an N-type GaN layer which are sequentially deposited on the composite buffer layer, and the second semiconductor layer comprises an electron blocking layer and a P-type GaN layer which are sequentially deposited on the multiple quantum well layer.
In a second aspect, the embodiment of the present invention further provides a method for preparing a high light efficiency light emitting diode epitaxial wafer, including the following steps:
providing a substrate;
sequentially depositing a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer on the substrate to form a composite buffer layer, wherein the first buffer layer is SiO 2 A layer of AlO as the second buffer layer a N 1-a A third buffer layer of Al b Ga 1-b O c N 1-c The fourth buffer layer is a GaN layer;
depositing a first semiconductor layer on the composite buffer layer;
depositing a multiple quantum well layer on the first semiconductor layer;
a second semiconductor layer is deposited over the multiple quantum well layer.
Preferably, the step of depositing a first buffer layer on the substrate comprises:
sputtering to form SiO in PECVD 2 The layer is sputtered at a power of 1 KW-10 KW, a sputtering temperature of 100 ℃ to 800 ℃, a sputtering pressure of 1 torr-50 torr, and carrier gases are N 2 Sputtering atmosphere O 2 /SiH 4 。
Preferably, the AlO a N 1-a Layer and the Al b Ga 1-b O c N 1-c The growth atmosphere of the layers is N 2 /NH 3 /O 2 The growth atmosphere of the GaN layer is N 2 /NH 3 。
Preferably, the AlO a N 1-a Layer of the Al b Ga 1-b O c N 1-c The growth pressure range of the layer and the GaN layer is 50-500 torr, and the growth temperature range is 500-1000 ℃.
Preferably, in the step of depositing the first semiconductor layer on the composite buffer layer, an undoped GaN layer and an N-type GaN layer are sequentially deposited on the composite buffer layer to form the first semiconductor layer;
and in the step of depositing the second semiconductor layer on the multiple quantum well layer, an electron blocking layer and a P-type GaN layer are sequentially deposited on the multiple quantum well layer to form the second semiconductor layer.
In a third aspect, an embodiment of the present invention further provides an LED, including the above-mentioned high-light-efficiency light emitting diode epitaxial wafer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a structural diagram of a high light efficiency led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for preparing a high-light-efficiency led epitaxial wafer according to an embodiment of the present invention.
Reference numerals illustrate:
embodiments of the present invention will be further described below with reference to the accompanying drawings.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
Example 1
As shown in fig. 1, a first embodiment of the present invention provides a high-light-efficiency light-emitting diode epitaxial wafer, which comprises a substrate 1, and a composite buffer layer 2, a first semiconductor layer, a multiple quantum well layer 5 and a second semiconductor layer sequentially deposited on the substrate 1;
wherein the composite buffer layer 2 comprises a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer which are sequentially deposited on the substrate 1, wherein the first buffer layer is SiO 2 Layer 21, the second buffer layer is AlO a N 1-a Layer 22, the third buffer layer is Al b Ga 1-b O c N 1-c Layer 23, the fourth buffer layer is GaN layer 24.
Specifically, by SiO 2 The layer 21 can effectively improve the light extraction efficiency, and due to the different refractive indexes of the epitaxial layers, the total reflection phenomenon is very easy to occur in the epitaxial layer structure, so that the light extraction efficiency of the LED is reduced, the refractive index of the sapphire substrate is n=1, the refractive index of the air is 1.81, the total reflection angle of the sapphire/air interface is 33 degrees, the light emitted by the LED has small escape probability, and SiO 2 Refractive index of layer 21, 1.47, siO 2 The total reflection angle of the air interface is 43 DEG, compared with the sapphire/air interface, the probability of light escape is much higher, the light extraction efficiency of the light emitting diode is improved, and the deposited AlO is formed a N 1-a Layer 22 and Al b Ga 1-b O c N 1-c The layer 23, by introducing O atoms and Ga atoms, can effectively reduce lattice mismatch between the substrate and the GaN epitaxial layer on one hand, release stress accumulated by the deposited epitaxial layer, and transition refractive index of the GaN epitaxial layer on the other hand is 2.43 to AlO a N 1-a Layer 22 refractive index 2 to SiO 2 The refractive index of the layer 21 is 1.47, effectively reducing GaN and Al b Ga 1-b O c N 1-c Layer 23/AlO a N 1-a Layer 22/SiO 2 The light of the adjacent interfaces of the layers 21 is totally reflected, the light-emitting efficiency of the buffer layer is improved, the finally deposited GaN layer 24 provides a nucleation center which is the same as the orientation of the substrate 1, the stress generated by lattice mismatch between the GaN epitaxial layer and the substrate 1 and the thermal stress generated by thermal expansion coefficient mismatch are released, the further growth provides a flat nucleation surface, the contact angle of nucleation growth is reduced, so that island-shaped GaN crystal grains can be connected into a plane in a smaller thickness, the island-shaped GaN crystal grains are converted into two-dimensional epitaxial growth, the crystal quality of the GaN epitaxial layer is improved, the non-radiative recombination efficiency of defects is reduced, and the light-emitting efficiency of the light-emitting diode is improved.
In the present embodiment, the SiO 2 The thickness of the layer 21 ranges from 10nm to 50nm, the AlO a N 1-a The thickness of the layer 22 ranges from 10nm to 100nm, the Al b Ga 1-b O c N 1-c The thickness of the layer 23 ranges from 10nm to 100nm, and the thickness of the GaN layer 24 ranges from 10nm to 100 nm.
In the present embodiment, the AlO a N 1-a The composition of O in layer 22 ranges from 0.01 to 0.5, the Al b Ga 1-b O c N 1-c The composition of Al in the layer 23 ranges from 0.01 to 0.5, and the composition of O ranges from 0.01 to 0.5.
In this embodiment, the first semiconductor layer includes an undoped GaN layer 3 and an N-type GaN layer 4 sequentially deposited on the composite buffer layer 2, and the second semiconductor layer includes an electron blocking layer 6 and a P-type GaN layer 7 sequentially deposited on the multiple quantum well layer 5.
For convenience of subsequent photoelectric testing and understanding, experimental group one, experimental group two, experimental group three, experimental group four, experimental group five, experimental group six, experimental group seven, experimental group eight, experimental group nine and control group are introduced in the present application;
the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth experimental groups are all high-light-efficiency led epitaxial wafers as described in embodiment one, which include the composite buffer layer 2 in embodiment one, and the control group is a led epitaxial wafer in the prior art, which has the same structure as embodiment one, but differs from embodiment one in that: the control group used a 35nm AlGaN buffer layer instead of the composite buffer layer 2 of example one;
specifically, siO in experiment group I 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.1 and the composition of O was in the range of 0.05.
SiO in experiment group II 2 Layer 21 has a thickness of 50nm, alO a N 1-a Layer 22 has a thickness of 100nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.1 and the composition of O was in the range of 0.05.
SiO in experiment group III 2 Layer 21 has a thickness of 10nm and AlO a N 1-a Layer 22 has a thickness of 10nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.1 and the composition of O was in the range of 0.05.
SiO in experiment group IV 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c The thickness of layer 23 is 100nm, the thickness of GaN layer 24 is 100nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The Al component of layer 23 is 0.1, O componentThe range is 0.05.
SiO in experiment group five 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 10nm, gaN layer 24 has a thickness of 10nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.1 and the composition of O was in the range of 0.05.
SiO in experiment group six 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O component of layer 22 is 0.5, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.1 and the composition of O was in the range of 0.05.
SiO in experiment group seven 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O component of layer 22 is 0.01, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.1 and the composition of O was in the range of 0.05.
SiO in experimental group eight 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.5 and the composition of O was in the range of 0.01.
SiO in experiment group nine 2 Layer 21 has a thickness of 20nm and AlO a N 1-a Layer 22 has a thickness of 35nm, al b Ga 1-b O c N 1-c Layer 23 has a thickness of 50nm, gaN layer 24 has a thickness of 60nm, alO a N 1-a The O composition of layer 22 was 0.05, al b Ga 1-b O c N 1-c The composition of Al in layer 23 was 0.01 and the composition of O was in the range of 0.5.
And carrying out photoelectric tests on the high-light-efficiency light-emitting diode epitaxial wafers in the first experimental group, the second experimental group, the third experimental group, the fourth experimental group, the fifth experimental group, the sixth experimental group, the seventh experimental group, the eighth experimental group, the ninth experimental group and the control group, wherein the test results are shown in table 1:
TABLE 1
As can be seen from table 1, the light efficiency of the led epitaxial wafer with high light efficiency provided by the control group is used as a reference, so that the light efficiency is improved by 0%, the light efficiency of the control group is improved by 5%, the light efficiency of the control group is improved by 3.5%, the light efficiency of the control group is improved by 2.8%, the light efficiency of the control group is improved by four, the light efficiency of the control group is improved by 3.2%, the light efficiency of the control group is improved by five, the light efficiency of the control group is improved by 2%, the light efficiency of the control group is improved by six, the light efficiency of the control group is improved by 3.5%, the light efficiency of the control group is improved by seven, the light efficiency of the control group is improved by 1.8%, the light efficiency of the control group is improved by eight, the light efficiency of the control group is improved by 3.5%, the light efficiency of the control group is improved by nine, and the light efficiency of the control group is improved by 1.8%.
Therefore, compared with the control group, the light efficiency of the high-light-efficiency light-emitting diode epitaxial wafer provided by the experimental group I is improved by 5% to the maximum.
Example two
As shown in fig. 2, a second embodiment of the present invention provides a method for preparing a high-light-efficiency light emitting diode epitaxial wafer, which includes the following steps:
s01, providing a substrate 1;
specifically, the substrate 1 may be a sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate is adopted as the substrate 1 in the embodiment, but the sapphire is the most commonly used GaN-based LED substrate material at present, the sapphire substrate has the advantages of mature preparation process, lower price, easy cleaning and processing,has good stability at high temperature.
S02, sequentially depositing a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer on the substrate 1to form a composite buffer layer 2, wherein the first buffer layer is SiO 2 Layer 21, the second buffer layer is AlO a N 1-a Layer 22, the third buffer layer is Al b Ga 1-b O c N 1-c A layer 23, wherein the fourth buffer layer is a GaN layer 24;
specifically, siO is first formed by sputtering in PECVD 2 Layer 21, sputtering power 5 KW, sputtering temperature 400 ℃, sputtering pressure 20 torr, carrier gas N 2 ，SiO 2 Sputtering atmosphere O of layer 21 2 /SiH 4 Sputtering SiO in PECVD 2 After the layer 21, the substrate 1 and SiO 2 Layer 21 is transferred to MOCVD at H 2 The atmosphere is treated at the high temperature of 1200 ℃ under the pressure of 100torr, and the AlO is continuously deposited a N 1-a Layer 22, al b Ga 1-b O c N 1-c Layer 23, gaN layer 24;
wherein the AlO is a N 1-a Layer 22, the Al b Ga 1-b O c N 1-c The growth pressure ranges of the layer 23 and the GaN layer 24 are 50-500 torr, and the growth temperature ranges are 500-1000 ℃;
specifically, alO a N 1-a Layer 22, al b Ga 1-b O c N 1-c The growth temperature of the layer 23 and the GaN layer 24 is 820 ℃, alO a N 1-a Layer 22, al b Ga 1-b O c N 1-c The growth atmosphere of layer 23 is N 2 /NH 3 /O 2 GaN layer 24 growth atmosphere N 2 /NH 3 ，AlO a N 1-a Layer 22, al b Ga 1-b O c N 1-c The growth pressure of the layer 23 and the GaN layer 24 was 100 torr.
S03, depositing a first semiconductor layer on the composite buffer layer 2;
specifically, step S03 includes sequentially depositing an undoped GaN layer 3 and an N-type GaN layer 4 on the composite buffer layer to form a first semiconductor layer;
therefore, it is first necessary to deposit the undoped GaN layer 3 on the composite buffer layer 2;
specifically, the growth temperature of the undoped GaN layer 3 is 1050-1200 ℃, the growth pressure is 100-600 torr, the thickness is 1 um-5 um, wherein the growth temperature of the undoped GaN layer 3 is 1100 ℃, the growth pressure is 150 torr, the growth thickness is 2 um-3 um, the growth temperature of the undoped GaN layer 3 is higher, the pressure is lower, the crystal quality of the prepared GaN is better, meanwhile, the compressive stress is released through stacking faults along with the increase of the thickness of the GaN, line defects are reduced, the crystal quality is improved, reverse leakage current is reduced, the consumption of Ga source materials by improving the thickness of the GaN layer is larger, the epitaxial cost of an LED is greatly improved, and therefore, the conventional undoped GaN of an LED epitaxial wafer is usually grown by 2 um-3 um, the production cost is saved, and the GaN material has higher crystal quality;
then, depositing an N-type GaN layer 4 on the undoped GaN layer 3;
specifically, the growth temperature of the N-type GaN layer 4 is 1050-1200 ℃, the growth pressure is 100-600 torr, the thickness is 2-3 um, and the Si doping concentration is 1E 19-5E 19atoms/cm 3 Wherein the growth temperature of the N-type GaN layer 4 is 1120 ℃, the growth pressure is 100torr, the growth thickness is 2 um-3 um, and the doping concentration of Si is 2.5E19 atoms/cm 3 Firstly, the N-type GaN layer 4 provides sufficient electrons for LED luminescence, secondly, the resistivity of the N-type GaN layer 4 is higher than that of the transparent electrode on the p-GaN, so that the resistivity of the N-type GaN layer 4 can be effectively reduced due to sufficient Si doping, and finally, the stress can be effectively released due to sufficient thickness of the N-type GaN layer 4, so that the luminous efficiency of the light-emitting diode is improved.
S04, depositing a multi-quantum well layer 5 on the first semiconductor layer;
the step S04 is to deposit a multiple quantum well layer 5 on the N-type GaN layer 4, wherein the multiple quantum well layer 5 is an InGaN quantum well layer and an AlGaN quantum barrier layer which are alternately stacked, the stacking cycle number is 6-12, the growth temperature of the InGaN quantum well layer is 790-810 ℃, the thickness is 2-5 nm, the growth pressure is 50-300 torr, the in component is 0.01-0.3, the growth temperature of the AlGaN quantum barrier layer is 800-900 ℃, the thickness is 5-15 nm, the growth pressure is 50-300 torr, and the Al component is 0.01-0.1;
specifically, the number of stacking cycles of the InGaN quantum well layer and the AlGaN quantum barrier layer is 10, wherein the growth temperature of the InGaN quantum well layer is 795 ℃, the thickness of the InGaN quantum well layer is 3.5nm, the growth pressure is 200torr, the in component is 0.22, the growth temperature of the AlGaN quantum barrier layer is 855 ℃, the thickness of the AlGaN quantum well layer is 9.8nm, the growth pressure is 200torr, the Al component is 0.05, the multiple quantum well layer 5 is an electron and hole recombination region, and the overlapping degree of the electron and hole wave functions can be obviously increased by reasonable structural design, so that the luminous efficiency of the LED device is improved.
S05, depositing a second semiconductor layer on the multiple quantum well layer 5;
an electron blocking layer 6 and a P-type GaN layer 7 are sequentially deposited on the multi-quantum well layer 5 to form a second semiconductor layer;
therefore, firstly, an electron blocking layer 6 is required to be deposited on the multiple quantum well layer 5, the electron blocking layer 6 is an AlInGaN layer, the thickness of the electron blocking layer is 10 nm-40 nm, the growth temperature is 900-1000 ℃, the growth pressure is 100-300 torr, wherein the Al component is 0.005-0.1, and the in component is 0.01-0.2;
specifically, the thickness of the electron blocking layer 6 is 15nm, wherein the concentration of the Al component gradually increases along the growth direction of the epitaxial layer, gradually changes from 0.01 to 0.05, the growth temperature is 965 ℃ and the growth pressure is 200torr, so that the electron overflow can be effectively limited, the blocking of holes can be reduced, the injection efficiency of the holes to the quantum well is improved, the auger recombination of carriers is reduced, and the luminous efficiency of the light-emitting diode is improved;
then, a P-type GaN layer 7 is deposited on the electron blocking layer 6, the growth temperature of the P-type GaN layer 7 is 900-1050 ℃, the thickness is 10-50 nm, the growth pressure is 100-600 torr, and the doping concentration of Mg is 1E 19-1E 21 atoms/cm 3 ；
Specifically, the growth temperature of the P-type GaN layer 7 is 985 ℃, the thickness is 15nm, the growth pressure is 200torr, and the Mg doping concentration is 2E20 atoms/cm 3 Too high a doping concentration of Mg would damage the crystal quality, whereas the doping concentrationThe lower hole concentration is influenced, and meanwhile, for the LED structure containing the V-shaped pits, the higher growth temperature of the P-type GaN layer 7 is favorable for combining the V-shaped pits, so that the LED epitaxial wafer with a smooth surface is obtained.
Further, in other embodiments of the present invention, an LED is provided, including the high light efficiency LED epitaxial wafer according to embodiment one.
In conclusion, the invention uses SiO 2 The layer 21 can effectively improve the light extraction efficiency, and due to the different refractive indexes of the epitaxial layers, the total reflection phenomenon is very easy to occur in the epitaxial layer structure, so that the light extraction efficiency of the LED is reduced, the refractive index of the sapphire substrate is n=1, the refractive index of the air is 1.81, the total reflection angle of the sapphire/air interface is 33 degrees, the light emitted by the LED has small escape probability, and SiO 2 Refractive index of layer 21, 1.47, siO 2 The total reflection angle of the air interface is 43 DEG, compared with the sapphire/air interface, the probability of light escape is much higher, the light extraction efficiency of the light emitting diode is improved, and the deposited AlO is formed a N 1-a Layer 22 and Al b Ga 1-b O c N 1-c The layer 23, by introducing O atoms and Ga atoms, can effectively reduce lattice mismatch between the substrate and the GaN epitaxial layer on one hand, release stress accumulated by the deposited epitaxial layer, and transition refractive index of the GaN epitaxial layer on the other hand is 2.43 to AlO a N 1-a Layer 22 refractive index 2 to SiO 2 The refractive index of the layer 21 is 1.47, effectively reducing GaN and Al b Ga 1-b O c N 1-c Layer 23/AlO a N 1-a Layer 22/SiO 2 The light total reflection of the adjacent interfaces of the layers 21 improves the light-emitting efficiency of the buffer layer, the finally deposited GaN layer 24 provides nucleation centers which are the same as the substrate orientation, releases the stress generated by lattice mismatch between the GaN epitaxial layer and the substrate 1 and the thermal stress generated by thermal expansion coefficient mismatch, further growth provides a flat nucleation surface, reduces the contact angle of nucleation growth to enable island-shaped GaN crystal grains to be connected into planes in a smaller thickness, and is converted into two-dimensional epitaxial growth, thereby improving the crystal quality of the GaN epitaxial layer, reducing the non-radiative recombination efficiency of defects and improving the efficiency ofLuminous efficiency of the light emitting diode.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. The high-light-efficiency light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a composite buffer layer, a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer which are sequentially deposited on the substrate;
wherein the composite buffer layer comprises a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer which are sequentially deposited on the substrate, wherein the first buffer layer is SiO 2 A layer of AlO as the second buffer layer a N 1-a A third buffer layer of Al b Ga 1-b O c N 1-c And the fourth buffer layer is a GaN layer.
2. The high light efficiency led epitaxial wafer of claim 1, wherein said SiO 2 The thickness of the layer ranges from 10nm to 50nm, and the AlO a N 1-a The thickness of the layer ranges from 10nm to 100nm, and the Al b Ga 1-b O c N 1-c The thickness range of the layer is 10 nm-100 nm, and the thickness range of the GaN layer is 10 nm-100 nm.
3. The high light efficiency led epitaxial wafer of claim 1, wherein said AlO a N 1-a The component of O in the layer ranges from 0.01 to 0.5, and the Al b Ga 1-b O c N 1-c The Al component of the layer ranges from 0.01 to 0.5, and the O component ranges from 0.01 to 0.5.
4. The high light efficiency led epitaxial wafer of any one of claims 1-3 wherein said first semiconductor layer comprises an undoped GaN layer, an N-type GaN layer deposited sequentially on said composite buffer layer, and said second semiconductor layer comprises an electron blocking layer, a P-type GaN layer deposited sequentially on said multiple quantum well layer.
5. A method for preparing the high-light-efficiency light-emitting diode epitaxial wafer according to any one of claims 1to 4, comprising the following steps:
providing a substrate;
sequentially depositing a first buffer layer, a second buffer layer, a third buffer layer and a fourth buffer layer on the substrate to form a composite buffer layer, wherein the first buffer layer is SiO 2 A layer of AlO as the second buffer layer a N 1-a A third buffer layer of Al b Ga 1-b O c N 1-c The fourth buffer layer is a GaN layer;
depositing a first semiconductor layer on the composite buffer layer;
depositing a multiple quantum well layer on the first semiconductor layer;
a second semiconductor layer is deposited over the multiple quantum well layer.
6. The method of claim 5, wherein the step of depositing a first buffer layer on the substrate comprises:
sputtering to form SiO in PECVD 2 The layer is sputtered at a power of 1 KW-10 KW, a sputtering temperature of 100 ℃ to 800 ℃, a sputtering pressure of 1 torr-50 torr, and carrier gases are N 2 Sputtering atmosphere O 2 /SiH 4 。
7. The method for preparing a high light efficiency light emitting diode epitaxial wafer according to claim 5, wherein the AlO a N 1-a Layer and the Al b Ga 1-b O c N 1-c The growth atmosphere of the layers is N 2 /NH 3 /O 2 The growth atmosphere of the GaN layer is N 2 /NH 3 。
8.The method for preparing a high light efficiency light emitting diode epitaxial wafer according to claim 5, wherein the AlO a N 1-a Layer of the Al b Ga 1-b O c N 1-c The growth pressure ranges of the layers and the GaN layers are 50-500 torr, and the growth temperature ranges are 500-1000 ℃.
9. The method of claim 5, wherein in the step of depositing the first semiconductor layer on the composite buffer layer, an undoped GaN layer and an N-type GaN layer are sequentially deposited on the composite buffer layer to form the first semiconductor layer;
and in the step of depositing the second semiconductor layer on the multiple quantum well layer, an electron blocking layer and a P-type GaN layer are sequentially deposited on the multiple quantum well layer to form the second semiconductor layer.
10. An LED comprising a high light efficiency light emitting diode epitaxial wafer as claimed in any one of claims 1to 4.
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