CN116153917A - Fan-out type packaging structure and preparation method thereof - Google Patents

Fan-out type packaging structure and preparation method thereof Download PDF

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Publication number
CN116153917A
CN116153917A CN202310208563.9A CN202310208563A CN116153917A CN 116153917 A CN116153917 A CN 116153917A CN 202310208563 A CN202310208563 A CN 202310208563A CN 116153917 A CN116153917 A CN 116153917A
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layer
fan
chip set
top surface
heat dissipation
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朱文文
陈彦亨
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202310208563.9A priority Critical patent/CN116153917A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
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Abstract

The invention provides a fan-out type packaging structure and a preparation method thereof, wherein the fan-out type packaging structure comprises: the semiconductor device comprises a first solder layer, a first wiring layer, a second chip set, a conductive through hole column, a second wiring layer, a heat dissipation piece, a second solder layer and a third chip set, wherein the heat dissipation piece is arranged at a position between the second wiring layer and the third chip set, and the second solder layer is not arranged. According to the invention, the heat dissipation piece is arranged between the second wiring layer and the third chip set, so that the heat dissipation benefit of the fan-out type packaging structure is improved under the condition of occupying a small space, and the fan-out type packaging structure is beneficial to the application of the fan-out type packaging structure in high-density and high-power scenes; meanwhile, the structural design of the graphene soaking plate and the multi-layer lamination and heat dissipation array is utilized, so that the heat dissipation efficiency of the fan-out type packaging structure is further improved; in addition, the working efficiency of a single chip is improved by matching with the position design of the heat dissipation piece in the filling layer; finally, through the use of the double-layer rewiring layer, the fan-out type packaging structure can package chips and components of different types at a system level, and the functional integration and the application flexibility of the packaging structure are improved.

Description

Fan-out type packaging structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a fan-out type packaging structure and a preparation method thereof.
Background
With the rapid development of modern electronic technology, the integration degree and the assembly density of electronic components are continuously improved, and the work power consumption and the heating value of the electronic components are rapidly increased while powerful use functions are provided. High temperatures can have deleterious effects on the stability, reliability and lifetime of electronic components, such as excessive temperatures melting semiconductor solder joints, damaging circuit connection interfaces, increasing the resistance of conductors and causing mechanical stress damage. Therefore, ensuring the timely discharge of heat generated by the heat-generating electronic components has become an important aspect of microelectronic product system assembly. For portable electronic products (such as notebook computers and the like) with higher integration level and assembly density, heat dissipation even becomes a technical bottleneck problem of the whole product.
However, in the prior art, a heat dissipation structure is often arranged in the chip packaging layer, and the heat dissipation channel is far away from the outside, so that the heat dissipation efficiency inside the chip is greatly reduced, and meanwhile, the additionally arranged heat dissipation structure often occupies a large space, is unfavorable for the small-size high-density design requirement of the packaging structure, and simultaneously limits the application of multi-chip multifunctional integration in the same packaging structure.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art, and is not to be construed as merely illustrative of the background art section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a fan-out package structure and a method for manufacturing the same, which are used for solving the problems of low heat dissipation efficiency and large occupied space in the fan-out package structure in the prior art.
To achieve the above object, the present invention provides a fan-out type package structure, including: the semiconductor device comprises a first solder layer, a first wiring layer, a second chip set, a conductive through hole column, a second wiring layer, a heat dissipation piece, a second solder layer and a third chip set;
the first wiring layer comprises a first bottom surface and a first top surface, the first wiring layer is arranged on the first solder layer, and the first bottom surface is in effective electrical connection with the first solder layer;
a plurality of conductive via posts are arranged on the first wiring layer, and the conductive via posts are in effective electrical connection with the first top surface; the second chip set is arranged among the conductive through hole columns, and the second chip set is electrically connected with the first top surface;
the second wiring layer comprises a second bottom surface and a second top surface, the second bottom surface is arranged on the conductive through hole column, and the second bottom surface is in effective electric connection with the conductive through hole column;
the heat dissipation piece is arranged on the second top surface, and the second solder layer is arranged at a position of the second top surface where the heat dissipation piece is not arranged;
the third chip set is arranged on the second solder layer, and the third chip set is in effective electrical connection with the second wiring layer through the second solder layer.
Optionally, the heat dissipation element is a vapor chamber.
Optionally, the soaking plate is a graphene substrate.
Optionally, the graphene substrate is composed of a multi-layer graphene stack or/and a graphene heat dissipation matrix.
Optionally, the fan-out package structure further includes a first chipset disposed on the first bottom surface at a position where the first solder layer is not disposed, and the first chipset is electrically connected to the first bottom surface.
Optionally, the fan-out package structure further includes a first package layer covering the plurality of conductive via posts and the second chipset.
Optionally, the fan-out package structure further includes a filler layer, and the filler layer wraps the second solder layer and the heat sink.
Optionally, the fan-out package structure further includes a second package layer, and the second package layer wraps the second solder layer and the third chipset.
Optionally, discrete devices are disposed on the second wiring layer at positions where the second solder layer and the heat sink are not disposed.
The invention also provides a preparation method of the fan-out type packaging structure, which is used for preparing any one of the fan-out type packaging structures, and comprises the following steps:
providing a first temporary substrate; forming a first separation layer on the first temporary substrate;
forming a second wiring layer on the first separation layer, wherein the second wiring layer comprises a second bottom surface and a second top surface which are opposite to each other, and the first separation layer is contacted with the second top surface; forming a plurality of conductive via posts on the second bottom surface;
disposing a second chipset between the conductive via posts;
providing a first encapsulation layer covering the conductive via post and the second chipset;
forming a first wiring layer on the first packaging layer, wherein the first wiring layer comprises a first bottom surface and a first top surface which are opposite to each other, and the first top surface is in effective electric connection with the conductive through hole column and the second chip set; a first solder layer is arranged on the first bottom surface and is in effective electric connection with the first solder layer, and a first chip set is arranged at a position on the first bottom surface, where the first solder layer is not arranged, and is in effective electric connection with the first chip set;
the first temporary substrate is debonded from the second top surface through the first separation layer; filling a protective supporting layer to wrap the first solder layer and the first chip set; setting a second separation layer on the surface of the protection supporting layer, and setting a second temporary substrate on the surface of the second separation layer;
an opening is arranged on the second top surface, and a heat dissipation piece is arranged on the second top surface through the opening;
a second solder layer is arranged at a position on the second top surface, where the heat dissipation element is not arranged, a third chip set is arranged on the second solder layer, the third chip set and the second solder layer form effective electric connection, a filling layer is filled between the third chip set and the second top surface of the second wiring layer, and the filling layer fills gaps among the second solder layer, the heat dissipation element and the third chip set;
and the second temporary substrate is de-bonded with the protective supporting layer through the second separation layer, and the protective supporting layer is removed.
As described above, the fan-out type packaging structure and the preparation method thereof have the following beneficial effects:
according to the invention, the heat dissipation piece is arranged between the second wiring layer and the third chip set, so that the heat dissipation benefit of the fan-out type packaging structure is improved under the condition of occupying a small space, and the fan-out type packaging structure is beneficial to the application of the fan-out type packaging structure in high-density and high-power scenes;
according to the invention, the structural design of the graphene soaking plate and the multi-layer lamination and heat dissipation array thereof is utilized, so that the heat dissipation efficiency of the fan-out type packaging structure is further improved;
the invention improves the working efficiency of a single chip by matching with the position design of the heat dissipation piece in the filling layer;
the fan-out type packaging structure can package chips and components of different types at a system level through the use of the double-layer rewiring layer, and the functional integration and the application flexibility of the packaging structure are improved.
Drawings
Fig. 1 is a schematic structural diagram of a fan-out package according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of a fan-out package structure with a graphene substrate as a heat sink according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a fan-out package structure with a second package layer according to a first embodiment of the invention.
Fig. 4 is a schematic structural diagram of a fan-out package structure with a discrete device disposed on a second wiring layer according to a first embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a fan-out package structure with a second package layer on a graphene substrate as a heat sink according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a fan-out package structure with a second package layer and discrete devices, in which a heat dissipation element is a graphene substrate according to a first embodiment of the present invention.
Fig. 7 is a schematic structural diagram showing a first separation layer disposed on a first temporary substrate in step 1 according to a second embodiment of the present invention.
Fig. 8 is a schematic structural diagram showing the formation of the second wiring layer and the conductive via post in step 2 according to the second embodiment of the present invention.
Fig. 9 is a schematic diagram showing a structure of the second chipset in step 3 according to the second embodiment of the present invention.
Fig. 10 is a schematic structural diagram showing the arrangement of the first encapsulation layer in step 4 in the second embodiment of the present invention.
Fig. 11 is a schematic structural diagram showing the arrangement of the first wiring layer, the first solder layer and the first chipset in step 5 in the second embodiment of the present invention.
Fig. 12 is a schematic structural diagram showing the filling of the protective supporting layer, the setting of the second separation layer and the second temporary substrate in step 6 in the second embodiment of the present invention.
Fig. 13 is a schematic diagram showing a structure of the second top surface with the opening in step 7 according to the second embodiment of the present invention.
Fig. 14 is a schematic structural diagram showing the arrangement of the heat sink in step 8 in the second embodiment of the present invention.
Fig. 15 is a schematic structural diagram showing the arrangement of the second solder layer, the filling layer and the third chip set in step 9 in the second embodiment of the present invention.
Fig. 16 is a schematic diagram showing the structure of the debonding and removal of the protective support layer in step 10 according to the second embodiment of the present invention.
Description of element reference numerals
11. A first solder layer; 12. a first chipset; 13. a first wiring layer; 131. a first bottom surface; 132. a first top surface; 14. a conductive via post; 15. a second chipset; 16. a second wiring layer; 161. a second bottom surface; 162. a second top surface; 17. a heat sink; 171. a graphene substrate; 18. a second solder layer; 19. a third chip set;
21. a first encapsulation layer; 22. a filling layer; 23. a second encapsulation layer; 24. a discrete device;
31. a first temporary substrate; 32. a first separation layer; 33. a protective support layer; 34. an opening; 35. a second temporary substrate; 36. and a second separation layer.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the schematic drawings showing the structure of the apparatus are not partially enlarged to general scale, and the schematic drawings are merely examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Embodiment one:
as shown in fig. 1, the present invention provides a fan-out package structure, the fan-out package structure includes: a first solder layer 11, a first wiring layer 13, a second chip set 15, a conductive via post 14, a second wiring layer 16, a heat sink 17, a second solder layer 18, a third chip set 19;
the first wiring layer 13 includes a first bottom surface 131 and a first top surface 132, the first wiring layer 13 is disposed on the first solder layer 11, and the first bottom surface 131 is in effective electrical connection with the first solder layer 11;
a plurality of conductive via posts 14 disposed on the first wiring layer 13, the conductive via posts 14 forming an operative electrical connection with the first top surface 132; the second chip set 15 is disposed between the plurality of conductive via posts 14, the second chip set 15 forming an electrical connection with the first top surface 132;
the second wiring layer 16 includes a second bottom surface 161 and a second top surface 162, the second bottom surface 161 being disposed on the conductive via post 14, the second bottom surface 161 being in operative electrical connection with the conductive via post 14;
the heat sink 17 is disposed on the second top surface 162, and the second solder layer 18 is disposed on the second top surface 162 where the heat sink 17 is not mounted;
the third chip set 19 is disposed on the second solder layer 18, and the third chip set 19 is electrically connected to the second wiring layer 16 through the second solder layer 18.
According to the invention, the heat dissipation element 17 is arranged between the second wiring layer 16 and the third chip set 19, so that the space of the fan-out type packaging structure is fully utilized, the heat transfer and heat dissipation paths of the heat dissipation element 17 are optimized, the heat dissipation efficiency of the fan-out type packaging structure is greatly improved, the structural rigidity is improved, and the efficiency of a single chip is improved; the invention omits a wafer substrate which is needed to be used by an intermediate layer through the arrangement of the conductive through hole column 14, improves the efficiency of the preparation process and saves the preparation cost.
Specifically, the first wiring layer 13 and the second wiring layer 16 each include a plurality of dielectric layers and a plurality of wiring layers laminated in order, and conductive vias between adjacent two wiring layers.
In one embodiment, the material of the wiring layer includes, but is not limited to, copper, aluminum, titanium.
In one embodiment, the material of the first solder layer 11 and/or the second solder layer 18 is copper, nickel, tin, silver.
In one embodiment, the line width and line spacing of each line layer of the first wiring layer 13 gradually decrease from the first top surface 132 to the first bottom surface 131.
In one embodiment, the line width and line spacing of each of the second wiring layers 16 gradually decrease from the second top surface 162 to the second bottom surface 161.
In one embodiment, the heat sink 17 is a vapor chamber.
In one embodiment, as shown in fig. 2, the vapor chamber is a graphene substrate 171.
According to the invention, the graphene substrate 171 is arranged as the heat dissipation piece 17, so that the characteristics of light weight and high heat conductivity of graphene are utilized, the high heat dissipation efficiency is realized, the weight of the whole device is reduced, and the portability of the device is improved.
In one embodiment, the graphene substrate 171 is composed of a multi-layer graphene stack or/and a graphene heat dissipation matrix.
According to the invention, through the structural design of graphene lamination or matrix, the heat dissipation efficiency of the heat dissipation piece 17 is further improved.
In one embodiment, the graphene stack has a thickness of 0.5 mm-2 mm.
In one embodiment, the fan-out package structure further includes a first chipset 12, where the first chipset 12 is disposed on the first bottom surface 131 and the first solder layer 11 is not disposed, and the first chipset 12 is electrically connected to the first bottom surface 131.
In one embodiment, the first chipset 12 is an IPD (integrated passive device), the second chipset 15 is an SoC (system on a chip), and the third chipset 19 is a DDR (double rate synchronous dynamic random access memory), and the chip types thereof cooperate with each other to achieve efficient electrical connection and information transfer.
Specifically, an effective electrical connection is formed between the first chipset 12 and the first bottom surface 131 of the first wiring layer 13 through the first connection layer.
Specifically, an effective electrical connection is formed between the second chipset 15 and the first top surface 132 of the first wiring layer 13 through the second connection layer.
Specifically, the bonding surface of the first chipset 12 is facing up, the bonding surface of the second chipset 15 may be facing up or down, and the bonding surface of the third chipset 19 is facing down.
In one embodiment, first chipset 12, second chipset 15, or/and third chipset 19 each comprise a plurality of chips or/and components.
In one embodiment, the chips and components in the first chipset 12, the second chipset 15, or/and the third chipset 19 are SMT (surface mount).
In one embodiment, the fan-out package structure further includes a first encapsulation layer 21, the first encapsulation layer 21 covering the plurality of conductive via posts 14 and the second chipset 15.
In one embodiment, the fan-out package structure further includes a filler layer 22, the filler layer 22 encasing the second solder layer 18 and the heat sink 17.
According to the invention, the heat dissipation piece 17 is arranged in the filling layer 22, so that the space of the fan-out type packaging structure is fully utilized, the heat dissipation efficiency of a heat dissipation path is improved, the structural rigidity is ensured, and the effect optimization of a single chip is realized.
In one embodiment, the material of the filler layer 22 includes, but is not limited to, an epoxy layer, a polyimide layer, and a silicone layer.
In one embodiment, as shown in fig. 3, the fan-out package structure further includes a second package layer 23, where the second package layer 23 wraps the second solder layer 18 and the third chipset 19.
In one embodiment, the first encapsulation layer 21 and the second encapsulation layer 23 are integrally formed to achieve better encapsulation effect and improve process efficiency.
In one embodiment, the material of the first encapsulation layer 21 and/or the second encapsulation layer 23 is an epoxy resin, including but not limited to a thermosetting epoxy resin or a thermoplastic epoxy resin.
In one embodiment, as shown in fig. 4, discrete devices 24 are provided on the second wiring layer 16 at positions where the second solder layer 18 and the heat sink 17 are not provided.
The discrete device 24 is arranged on the second top surface 162 of the second wiring layer 16, so that the fan-out type packaging structure can be used for electric connection of circuits such as current control and voltage stabilization, and the functional integration of the fan-out type packaging structure is improved.
In one embodiment, the discrete device 24 may also be disposed on the first bottom surface 131 of the first wiring layer 13 where the first solder layer 11 and the first chipset 12 are not disposed, thereby further improving the overall functional integration.
In one embodiment, as shown in fig. 5, the fan-out type package structure provides the second package layer 23 when the graphene substrate 171 is used as the heat sink 17, and improves the heat dissipation efficiency of the device on the premise of ensuring the package reliability of the device.
In one embodiment, as shown in fig. 6, the fan-out type packaging structure simultaneously sets the second packaging layer 23 and the discrete device 24 when the graphene substrate 171 is used as the heat dissipation member 17, so that the functional integration and the heat dissipation efficiency of the device are improved on the premise of ensuring the packaging reliability of the device, which is beneficial to expanding the application scene of the fan-out type packaging structure and improving the use flexibility.
Embodiment two:
the invention provides a preparation method of a fan-out type packaging structure, which is used for preparing the fan-out type packaging structure of any one of the first embodiment, and comprises the following steps:
step 1: providing a first temporary substrate 31, forming a first separation layer 32 on the first temporary substrate 31;
step 2: forming a second wiring layer 16 on the first separation layer 32, the second wiring layer 16 including a second bottom surface 161 and a second top surface 162 opposite to each other, the first separation layer 32 being in contact with the second top surface 162; forming a plurality of conductive via posts 14 on the second bottom surface 161;
step 3: a second chipset 15 is disposed between the conductive via posts 14;
step 4: a first encapsulation layer 21 is provided covering the conductive via post 14 and the second chipset 15;
step 5: forming a first wiring layer 13 on the first packaging layer 21, wherein the first wiring layer 13 comprises a first bottom surface 131 and a first top surface 132 which are opposite to each other, and the first top surface 132 is effectively electrically connected with the conductive through hole column 14 and the second chip set 15; the first solder layer 11 is disposed on the first bottom surface 131 and is in effective electrical connection with the first solder layer 11, and the first chipset 12 is disposed on the first bottom surface 131 at a position where the first solder layer 11 is not disposed and is in effective electrical connection with the first chipset 12;
step 6: the first temporary substrate 31 is debonded from the second top surface 162 through the first separation layer 32; filling the protective support layer 33 to wrap the first solder layer 11 and the first chip set 12; a second separation layer 36 is arranged on the surface of the protection supporting layer 33, and a second temporary substrate 35 is arranged on the surface of the second separation layer 36;
step 7: providing an opening 34 on the second top surface 162;
step 8: the heat sink 17 is disposed on the second top surface 162 through the opening 34;
step 9: a second solder layer 18 is arranged on the second top surface 162 at a position where the heat dissipation element 17 is not arranged, a third chip set 19 is arranged on the second solder layer 18, the third chip set 19 and the second solder layer 18 form effective electric connection, a filling layer 22 is filled between the third chip set 19 and the second top surface 162 of the second wiring layer 16, and the filling layer 22 fills the gaps among the second solder layer 18, the heat dissipation element 17 and the third chip set 19;
step 10: the second temporary substrate 35 is de-bonded to the protective support layer 33 through the second separation layer 36, and the protective support layer 33 is removed.
The method for manufacturing the fan-out package structure of the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the sequence of the method for manufacturing the fan-out package structure of the present invention, and those skilled in the art may vary depending on the actual manufacturing steps.
First, as shown in fig. 7, step 1 is performed to provide a first temporary substrate 31, and a first separation layer 32 is formed on the first temporary substrate 31.
Then, as shown in fig. 8, step 2 is performed to form a second wiring layer 16 on the first separation layer 32, the second wiring layer 16 including a second bottom surface 161 and a second top surface 162 which are opposite to each other, the first separation layer 32 being in contact with the second top surface 162; a plurality of conductive via posts 14 are formed on the second bottom surface 161.
Next, as shown in fig. 9, step 3 is performed to dispose a second chip set 15 between the conductive via posts 14.
In one embodiment, after the first encapsulation layer 21 is disposed to cover the plurality of conductive via posts 14 and the second chipset 15, the first encapsulation layer 21 is polished until the conductive via posts 14 are exposed.
Then, as shown in fig. 10, step 4 is performed, and a first encapsulation layer 21 is provided to cover the conductive via post 14 and the second chipset 15.
Next, as shown in fig. 11, step 5 is performed, forming a first wiring layer 13 on the first packaging layer 21, where the first wiring layer 13 includes a first bottom surface 131 and a first top surface 132 opposite to each other, and the first top surface 132 is effectively electrically connected to the conductive via post 14 and the second chipset 15; the first solder layer 11 is disposed on the first bottom surface 131 and is electrically connected to the first solder layer 11, and the first chipset 12 is disposed on the first bottom surface 131 where the first solder layer 11 is not disposed and is electrically connected to the first chipset 12.
Then, as shown in fig. 12, step 6 is performed in which the first temporary substrate 31 is debonded from the second top surface 162 through the first separation layer 32; filling the protective support layer 33 to wrap the first solder layer 11 and the first chip set 12; a second separation layer 36 is disposed on the surface of the protective supporting layer 33, and a second temporary substrate 35 is disposed on the surface of the second separation layer 36.
The invention plays a role of protection and increases the structural strength by arranging the protection support layer 33 to wrap the first solder layer 11 and the first chip set 12.
Next, as shown in fig. 13, step 7 is performed to provide the opening 34 on the second top surface 162.
In one embodiment, the opening 34 is made by a laser.
Then, as shown in fig. 14, step 8 is performed to dispose the heat sink 17 on the second top surface 162 through the opening 34.
Next, as shown in fig. 15, step 9 is performed, in which the second solder layer 18 is disposed on the second top surface 162 at a position where the heat spreader 17 is not disposed, the third chip set 19 is disposed on the second solder layer 18, the third chip set 19 is electrically connected with the second solder layer 18, a filling layer 22 is filled between the third chip set 19 and the second top surface 162 of the second wiring layer 16, and the filling layer 22 fills the gaps among the second solder layer 18, the heat spreader 17 and the third chip set 19.
In one embodiment, the first solder layer 11 and/or the second solder layer 18 may be distributed only on the periphery of the soldered object by using a conventional flip chip bonding (FCOB), or the whole second top surface 162 may be covered with solder balls by using a controlled collapse chip bonding (C4), or the solder caps may be formed on the solder columns by using an ultra fine pitch dedicated chip bonding (C2). C2 can obtain smaller solder unit spacing, namely larger solder unit density, namely IO port (input/output port) density on the premise of not being easy to short circuit; but the solder bump is in the form of a solder cap, and the surface tension is insufficient to achieve self-alignment with the solder column, so the self-alignment capability of the solder bump of C2 is lower than that of C4. The practitioner needs to weigh the solder-mounting method selected according to the requirements on the density of the IO ports and the position accuracy of the solder.
Finally, as shown in fig. 16, step 10 is performed, and the second temporary substrate 35 is de-bonded from the protective support layer 33 through the second separation layer 36, and the protective support layer 33 is removed.
In one embodiment, the material of the first and second temporary substrates 31 and 35 may be one of glass, metal, semiconductor, polymer, or ceramic. Preferably, the materials of the first temporary substrate 31 and the second temporary substrate 35 are glass, so that the cost is low, the separation layer is easy to form on the surfaces of the first temporary substrate 31 and the second temporary substrate 35, and the difficulty of the subsequent debonding process can be reduced.
In one embodiment, the materials of the first separation layer 32, the second separation layer 36 are polymers. Specifically, the materials of the first and second separation layers 32, 36 are respectively coated on the first and second temporary substrates 31, 35 by a spin coating process.
In summary, according to the fan-out type packaging structure and the preparation method thereof, the heat dissipation piece is arranged between the second wiring layer and the third chip set, so that the heat dissipation benefit of the fan-out type packaging structure is improved under the condition of occupying a small space, and the fan-out type packaging structure is beneficial to being applied to high-density and high-power scenes; meanwhile, the structural design of the graphene soaking plate and the multi-layer lamination and heat dissipation array is utilized, so that the heat dissipation efficiency of the fan-out type packaging structure is further improved; in addition, the working efficiency of a single chip is improved by matching with the position design of the heat dissipation piece in the filling layer; finally, through the use of the double-layer rewiring layer, the fan-out type packaging structure can package chips and components of different types at a system level, and the functional integration and the application flexibility of the packaging structure are improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A fan-out package structure, the fan-out package structure comprising: the semiconductor device comprises a first solder layer, a first wiring layer, a second chip set, a conductive through hole column, a second wiring layer, a heat dissipation piece, a second solder layer and a third chip set;
the first wiring layer comprises a first bottom surface and a first top surface, the first wiring layer is arranged on the first solder layer, and the first bottom surface is in effective electrical connection with the first solder layer;
a plurality of conductive via posts are arranged on the first wiring layer, and the conductive via posts are in effective electrical connection with the first top surface; the second chip set is arranged among the conductive through hole columns, and the second chip set is electrically connected with the first top surface;
the second wiring layer comprises a second bottom surface and a second top surface, the second bottom surface is arranged on the conductive through hole column, and the second bottom surface is in effective electric connection with the conductive through hole column;
the heat dissipation piece is arranged on the second top surface, and the second solder layer is arranged at a position of the second top surface where the heat dissipation piece is not arranged;
the third chip set is arranged on the second solder layer, and the third chip set is in effective electrical connection with the second wiring layer through the second solder layer.
2. The fan-out package structure of claim 1, wherein the heat sink is a vapor chamber.
3. The fan-out package structure of claim 2, wherein the soaking plate is a graphene substrate.
4. The fan-out package structure of claim 3, wherein the graphene substrate is comprised of a multi-layer graphene stack or/and a graphene heat dissipation matrix.
5. The fan-out package structure of claim 1, further comprising a first chipset disposed on the first bottom surface at a location where the first solder layer is not disposed, the first chipset being in operative electrical connection with the first bottom surface.
6. The fan-out package structure of claim 1, further comprising a first encapsulation layer covering the plurality of conductive via posts and the second chipset.
7. The fan-out package structure of claim 1, further comprising a filler layer surrounding the second solder layer and the heat sink.
8. The fan-out package structure of claim 1, further comprising a second encapsulation layer surrounding the second solder layer and the third chipset.
9. The fan-out package structure of claim 1, wherein discrete devices are disposed on the second routing layer at locations where the second solder layer and the heat spreader are not disposed.
10. A method for manufacturing the fan-out package structure according to any one of claims 1 to 9, comprising:
providing a first temporary substrate; forming a first separation layer on the first temporary substrate;
forming a second wiring layer on the first separation layer, wherein the second wiring layer comprises a second bottom surface and a second top surface which are opposite to each other, and the first separation layer is contacted with the second top surface; forming a plurality of conductive via posts on the second bottom surface;
disposing a second chipset between the conductive via posts;
providing a first encapsulation layer covering the conductive via post and the second chipset;
forming a first wiring layer on the first packaging layer, wherein the first wiring layer comprises a first bottom surface and a first top surface which are opposite to each other, and the first top surface is in effective electric connection with the conductive through hole column and the second chip set; a first solder layer is arranged on the first bottom surface and is in effective electric connection with the first solder layer, and a first chip set is arranged at a position on the first bottom surface, where the first solder layer is not arranged, and is in effective electric connection with the first chip set;
the first temporary substrate is debonded from the second top surface through the first separation layer; filling a protective supporting layer to wrap the first solder layer and the first chip set; setting a second separation layer on the surface of the protection supporting layer, and setting a second temporary substrate on the surface of the second separation layer;
an opening is arranged on the second top surface, and a heat dissipation piece is arranged on the second top surface through the opening;
a second solder layer is arranged at a position on the second top surface, where the heat dissipation element is not arranged, a third chip set is arranged on the second solder layer, the third chip set and the second solder layer form effective electric connection, a filling layer is filled between the third chip set and the second top surface of the second wiring layer, and the filling layer fills gaps among the second solder layer, the heat dissipation element and the third chip set;
and the second temporary substrate is de-bonded with the protective supporting layer through the second separation layer, and the protective supporting layer is removed.
CN202310208563.9A 2023-03-06 2023-03-06 Fan-out type packaging structure and preparation method thereof Pending CN116153917A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310208563.9A CN116153917A (en) 2023-03-06 2023-03-06 Fan-out type packaging structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310208563.9A CN116153917A (en) 2023-03-06 2023-03-06 Fan-out type packaging structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116153917A true CN116153917A (en) 2023-05-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310208563.9A Pending CN116153917A (en) 2023-03-06 2023-03-06 Fan-out type packaging structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116153917A (en)

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