CN116153851A - Filling method of asymmetric large-aspect-ratio groove and preparation method of semiconductor device - Google Patents

Filling method of asymmetric large-aspect-ratio groove and preparation method of semiconductor device Download PDF

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Publication number
CN116153851A
CN116153851A CN202111392291.XA CN202111392291A CN116153851A CN 116153851 A CN116153851 A CN 116153851A CN 202111392291 A CN202111392291 A CN 202111392291A CN 116153851 A CN116153851 A CN 116153851A
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Prior art keywords
asymmetric
layer
silicon
deep trench
filling
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CN202111392291.XA
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陈东石
涂芝娟
蔡艳
汪巍
余明斌
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Shanghai Industrial Utechnology Research Institute
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Shanghai Industrial Utechnology Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention provides a filling method of an asymmetric large-aspect-ratio groove and a preparation method of a semiconductor device, comprising the following steps: 1) Etching an asymmetric deep trench in the silicon substrate; 2) Forming a hard mask layer, and performing a first thermal oxidation process to generate a first silicon oxide layer; 3) Forming a polysilicon layer, wherein the polysilicon layer forms a first seal over the asymmetric deep trench opening; 4) Etching the polysilicon layer to form an opening; 5) And performing a second thermal oxidation process, and closing the opening based on volume change to form a second seal in the process of oxidizing the polysilicon layer to form a second silicon dioxide layer, so as to control the seal height of the pore surrounded by the second silicon dioxide layer. The invention can effectively fill the asymmetric high-aspect-ratio groove and control the top sealing position of the hole by adopting the traditional polysilicon deposition process and the polysilicon thermal oxidation process, solves the problem of filling the asymmetric high-aspect-ratio silicon groove which cannot be solved by more advanced equipment, and greatly reduces the filling cost.

Description

Filling method of asymmetric large-aspect-ratio groove and preparation method of semiconductor device
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a filling method of an asymmetric large-aspect-ratio groove and a preparation method of a semiconductor device.
Background
The development trend of integrated circuits is shallow junction, shallow step and advanced process, and the aspect ratio of the silicon trench is usually not greater than 2, and the silicon trenches are all symmetrical silicon trenches. The asymmetric silicon trenches and the "V" shaped silicon trenches are filled with devices to below 65nm node, such as High Aspect Ratio Process (HARP) devices, cha rp process technology devices, flow Chemical Vapor Deposition (FCVD) technology devices, and the like. There is currently no method for asymmetric high aspect ratio silicon trenches that can control well the position of the top of the aperture.
The thick silicon technology of the silicon photoelectron technology introduces a silicon groove with a large depth-to-width ratio, the depth-to-width ratio of the silicon groove can reach more than 10, and the top position of the hole formed by filling is required to be controllable. The filling problems faced by thick silicon optoelectronics have not been solved by conventional integrated circuit filling.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for filling an asymmetric high aspect ratio trench and a method for manufacturing a semiconductor device, which are used for solving the problems of difficult filling of an asymmetric high aspect ratio silicon trench and difficult control of the top position of a void in the prior art.
To achieve the above and other related objects, the present invention provides a method for filling an asymmetric high aspect ratio trench, the method comprising: 1) Providing a silicon substrate, etching a deep trench in the silicon substrate, and etching the silicon substrate to enable the silicon substrate height of the first side of the deep trench to be smaller than the silicon substrate height of the second side of the deep trench so as to form an asymmetric deep trench; 2) Forming a hard mask layer on the surface of the silicon substrate, performing a first thermal oxidation process on the silicon substrate, and generating a first silicon oxide layer on the side wall and the bottom of the asymmetric deep trench; 3) Forming a polysilicon layer in the asymmetric deep trench and on the hard mask layer, wherein the polysilicon layer gradually seals above the asymmetric deep trench opening to form a first seal along with the growth of the polysilicon layer; 4) Etching the polysilicon layer to gradually thin the polysilicon layer until the first seal is opened, so as to form an opening with a width; 5) And carrying out a second thermal oxidation process on the polycrystalline silicon layer based on the opening to oxidize the polycrystalline silicon layer to form a second silicon dioxide layer, wherein in the process of oxidizing the polycrystalline silicon layer to form the second silicon dioxide layer, the volume of the second silicon dioxide layer is enlarged relative to that of the polycrystalline silicon layer so as to seal the opening to form a second seal, and thus the seal height of the pore surrounded by the second silicon dioxide layer is controlled.
Optionally, in step 3), a polysilicon layer is formed in the asymmetric deep trench and on the substrate surface to a thickness of 20% -80% of the width of the asymmetric deep trench.
Optionally, the method of forming the polysilicon layer in the asymmetric deep trench and on the substrate surface in step 3) includes one of a chemical vapor deposition process, a polysilicon epitaxy process, and a combination of the chemical vapor deposition process and the polysilicon epitaxy process.
Optionally, the polysilicon layer thickness thinned by etching in step 4) controls the seal height of the aperture surrounded by the second silicon oxide layer in step 5).
Optionally, step 4) etching is performed to obtain a polysilicon layer in the asymmetric deep trench, wherein a distance between a top surface of the polysilicon layer in the asymmetric deep trench and a top surface of the hard mask on a first side of the asymmetric deep trench is smaller than or equal to a width of the asymmetric deep trench.
Optionally, in step 4), the width of the opening is less than or equal to the thickness increased by oxidizing the polysilicon layer on both sides of the asymmetric deep trench to form a silicon oxide layer.
Optionally, the width of the opening is 0.2-0.4 microns.
Optionally, the aspect ratio of the deep trench in step 1) is greater than or equal to 10.
The invention also provides a preparation method of the semiconductor device, which comprises the filling method of the asymmetric large-aspect-ratio groove.
Optionally, the semiconductor device comprises one of a silicon photonic device and a MEMS device.
As described above, the method for filling the asymmetric large-aspect-ratio groove and the method for manufacturing the semiconductor device have the following beneficial effects:
the filling method of the asymmetric high-aspect-ratio groove can control the top sealing position of the pore formed by filling in an effective range, solves the problem of filling the thick silicon optoelectronic isolation groove, particularly solves the problem of filling the asymmetric high-aspect-ratio groove, can be widely applied to products similar to silicon photon technology, can be widely applied to the production of special process products of integrated circuits and the process development of MEMS products, and has wide application prospect.
The invention can effectively fill the asymmetric high-aspect-ratio groove and control the top sealing position of the hole by adopting the traditional polysilicon deposition process and the polysilicon thermal oxidation process, solves the problem of filling the asymmetric high-aspect-ratio silicon groove which cannot be solved by more advanced equipment, and greatly reduces the filling cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some of the embodiments of the present application.
Fig. 1 to 7 are schematic structural views showing steps of a method for filling an asymmetric trench with a large aspect ratio according to an embodiment of the present invention.
Description of element reference numerals
10. Asymmetric deep trench
101. First side of asymmetric deep trench
102. Second side of asymmetric deep trench
103. Hard mask layer
104. Pores of the material
105. First seal
106. An opening
107. Second seal
12. First silicon oxide layer
21. Silicon substrate
31. Polysilicon layer
32. Second silicon dioxide layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 7, the present embodiment provides a filling method of an asymmetric high aspect ratio trench, the filling method including the following steps:
as shown in fig. 1-2, step 1) is first performed to provide a silicon substrate 21, a deep trench is etched in the silicon substrate 21, and the silicon substrate 21 is etched to make the height of the silicon substrate 21 at the first side of the deep trench smaller than the height of the silicon substrate 21 at the second side of the deep trench, so as to form an asymmetric deep trench 10.
In one embodiment, a deep trench is etched in the silicon substrate 21 through a first photolithography-etching step, where the aspect ratio of the deep trench is greater than or equal to 10, for example, the aspect ratio of the deep trench may be 10, 12, 15, etc. Then, the silicon substrate 21 on the first side 101 of the deep trench is etched by a second photolithography-etching process, so that the silicon substrate 21 on the first side 101 of the deep trench is lower than the silicon substrate 21 on the second side 102 of the deep trench, so as to form an asymmetric deep trench 10, as shown in fig. 2.
In one embodiment, the substrate 21 height of the deep trench first side 101 can be 0.1-100 microns less than the substrate 21 height of the deep trench second side 102, e.g., the substrate 21 height of the deep trench first side 101 is 0.2 microns or 0.5 microns less than the substrate 21 height of the deep trench second side 102, etc. In other embodiments, the difference between the substrate 21 height of the first side 101 and the substrate 21 height of the second side 102 can be set according to different substrate 21 thicknesses and device requirements, and is not limited to the examples listed herein.
As shown in fig. 3 to 4, step 2) is performed to form a hard mask layer 103 on the surface of the silicon substrate 21, and a first thermal oxidation process is performed on the silicon substrate 21 to generate a first silicon oxide layer 12 on the sidewall and the bottom of the asymmetric deep trench 10.
In one embodiment, a hard mask layer 103 is formed on the surface of the silicon substrate 21 by a chemical vapor deposition process, and the hard mask layer 103 is used for protecting the surface of the silicon substrate 21 and isolating gases such as oxygen, so as to avoid defects such as oxidation on the surface of the silicon substrate 21 caused by a subsequent oxidation process. The hard mask may be, for example, silicon nitride, silicon oxide, or a laminate of silicon nitride and silicon oxide, or may be a high-temperature resistant polymer material, etc., but is not limited to the above-mentioned examples.
In one embodiment, the silicon substrate 21 is placed in an oxygen-containing atmosphere, and then the silicon substrate 21 is oxidized at a high temperature, for example, 900-1000 ℃ or the like, so as to form the first silicon oxide layer 12 on the sidewall and the bottom of the asymmetric deep trench 10, where the top surface of the silicon substrate 21 is protected by the hard mask, so that the silicon oxide layer is not formed, and the surface quality of the silicon substrate 21 is ensured.
As shown in fig. 5, step 3) is then performed to form a polysilicon layer 31 in the asymmetric deep trench 10 and on the hard mask layer 103, and as the polysilicon layer 31 grows, the polysilicon layer 31 gradually closes over the asymmetric deep trench 10 opening to form a first seal 105.
Specifically, the polysilicon layer 31 is formed on the bottom and the sidewall of the asymmetric deep trench 10 and on the surface of the hard mask layer 103, and at the same time, the polysilicon layer 31 is also laterally grown, so that the first seal 105 is gradually formed over the opening of the asymmetric deep trench 10 while the deposition thickness is gradually increased.
In one embodiment, the thickness of the polysilicon layer 31 formed in the asymmetric deep trench 10 and on the substrate surface is 20% -80% of the width of the asymmetric deep trench 10.
In one embodiment, the step 3) method of forming the polysilicon layer 31 in the asymmetric deep trench 10 and on the substrate surface includes one of a chemical vapor deposition process, a polysilicon epitaxy process, and a combination of the chemical vapor deposition process and the polysilicon epitaxy process. In this embodiment, the method for forming the polysilicon layer 31 in the asymmetric deep trench 10 and on the substrate surface is a combination of a chemical vapor deposition process and a polysilicon epitaxy process, so as to improve the quality of the polysilicon layer 31, thereby improving the quality of the second silicon oxide layer formed by subsequent oxidation.
As shown in fig. 6, step 4) is performed, and the polysilicon layer 31 is etched to gradually thin the polysilicon layer 31 until the first seal 105 is opened, so as to form an opening 106 having a width.
In one embodiment, in the subsequent thermal oxidation process, oxygen may be introduced into the pores 104 through the openings 106, so as to ensure that the polysilicon layer 31 in the asymmetric deep trench 10 can be fully oxidized to form a silicon oxide layer, and meanwhile, the efficiency of thermal oxidation may be effectively improved. By setting the width of the opening 106, on the one hand, the efficiency of thermal oxidation can be ensured, and on the other hand, the polysilicon layer 31 can be ensured to form a seal at the original opening 106 after thermal oxidation. In one embodiment, the width of the opening 106 is 0.2 to 0.4 microns.
In one embodiment, step 4) the distance between the top surface of the polysilicon layer 31 within the asymmetric deep trench 10 and the top surface of the hard mask on the first side of the asymmetric deep trench 10 after etching is less than or equal to the width of the asymmetric deep trench 10.
In one embodiment, step 4) the width of the opening 106 is less than or equal to the increased thickness of the polysilicon layer 31 on both sides of the asymmetric deep trench 10 by oxidizing it to form a silicon oxide layer.
As shown in fig. 7, finally, step 5) is performed, based on the opening 106, a second thermal oxidation process is performed on the polysilicon layer 31 to oxidize the polysilicon layer 31 to form a second silicon dioxide layer 32, and in the process of oxidizing the polysilicon layer 31 to form the second silicon dioxide layer 32, the volume of the second silicon dioxide layer 32 is increased relative to the polysilicon layer 31, so as to seal the opening 106 to form a second seal 107, thereby controlling the seal height of the aperture 104 surrounded by the second silicon dioxide layer 32.
In this embodiment, the thickness of the polysilicon layer 31 that is thinned by etching in step 4) can control the seal height of the aperture 104 surrounded by the second silicon oxide layer 32 in step 5).
The embodiment also provides a preparation method of the semiconductor device, which comprises the filling method of the asymmetric large-aspect-ratio groove.
In one embodiment, the semiconductor device comprises one of a silicon photonic device and a MEMS device.
As described above, the method for filling the asymmetric large-aspect-ratio groove and the method for manufacturing the semiconductor device have the following beneficial effects:
the filling method of the asymmetric high-aspect-ratio groove can control the top sealing position of the hole 104 formed by filling in an effective range, solves the problem of filling the thick silicon optoelectronic isolation groove, particularly solves the problem of filling the asymmetric high-aspect-ratio groove, can be widely applied to products similar to silicon photon technology, can be widely applied to the production of special process products of integrated circuits and the process development of MEMS products, and has wide application prospect.
The invention can effectively fill the asymmetric high aspect ratio groove and control the top sealing position of the hole 104 by adopting the traditional polysilicon deposition process and the polysilicon thermal oxidation process, solves the problem of filling the asymmetric high aspect ratio silicon groove which cannot be solved by more advanced equipment, and greatly reduces the filling cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method for filling an asymmetric high aspect ratio trench, the method comprising:
1) Providing a silicon substrate, etching a deep trench in the silicon substrate, and etching the silicon substrate to enable the silicon substrate height of the first side of the deep trench to be smaller than the silicon substrate height of the second side of the deep trench so as to form an asymmetric deep trench;
2) Forming a hard mask layer on the surface of the silicon substrate, performing a first thermal oxidation process on the silicon substrate, and generating a first silicon oxide layer on the side wall and the bottom of the asymmetric deep trench;
3) Forming a polysilicon layer in the asymmetric deep trench and on the hard mask layer, wherein the polysilicon layer gradually seals above the asymmetric deep trench opening to form a first seal along with the growth of the polysilicon layer;
4) Etching the polysilicon layer to gradually thin the polysilicon layer until the first seal is opened, so as to form an opening with a width;
5) And carrying out a second thermal oxidation process on the polycrystalline silicon layer based on the opening to oxidize the polycrystalline silicon layer to form a second silicon dioxide layer, wherein in the process of oxidizing the polycrystalline silicon layer to form the second silicon dioxide layer, the volume of the second silicon dioxide layer is enlarged relative to that of the polycrystalline silicon layer so as to seal the opening to form a second seal, and thus the seal height of the pore surrounded by the second silicon dioxide layer is controlled.
2. The method for filling an asymmetric high aspect ratio trench as claimed in claim 1, wherein: in the step 3), the thickness of the polysilicon layer formed in the asymmetric deep groove and on the surface of the substrate is 20% -80% of the width of the asymmetric deep groove.
3. The method for filling an asymmetric high aspect ratio trench as claimed in claim 1, wherein: step 3) the method for forming the polysilicon layer in the asymmetric deep trench and on the surface of the substrate comprises one of a chemical vapor deposition process, a polysilicon epitaxy process and a combination of the chemical vapor deposition process and the polysilicon epitaxy process.
4. The method for filling an asymmetric high aspect ratio trench as claimed in claim 1, wherein: and controlling the sealing height of the pore surrounded by the second silicon dioxide layer in the step 5) through the thickness of the polysilicon layer which is thinned by the etching in the step 4).
5. The method for filling an asymmetric high aspect ratio trench as claimed in claim 1, wherein: step 4), the distance between the top surface of the polysilicon layer positioned in the asymmetric deep trench and the top surface of the hard mask at the first side of the asymmetric deep trench after etching is smaller than or equal to the width of the asymmetric deep trench.
6. The method for filling an asymmetric high aspect ratio trench as claimed in claim 1, wherein: and 4) the width of the opening is smaller than or equal to the thickness increased by oxidizing the polysilicon layers at the two sides of the asymmetric deep groove to form a silicon oxide layer.
7. The method for filling an asymmetric high aspect ratio trench as claimed in claim 6, wherein: the width of the opening is 0.2-0.4 micrometers.
8. The method for filling an asymmetric high aspect ratio trench as claimed in claim 1, wherein: the depth-to-width ratio of the deep trench in the step 1) is greater than or equal to 10.
9. A method for manufacturing a semiconductor device, characterized in that the method comprises the method for filling an asymmetric high aspect ratio trench as claimed in any one of claims 1 to 8.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: the semiconductor device includes one of a silicon photonic device and a MEMS device.
CN202111392291.XA 2021-11-19 2021-11-19 Filling method of asymmetric large-aspect-ratio groove and preparation method of semiconductor device Pending CN116153851A (en)

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