CN116150073A - PCIe channel splitting automatic identification circuit and method - Google Patents

PCIe channel splitting automatic identification circuit and method Download PDF

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Publication number
CN116150073A
CN116150073A CN202310430855.7A CN202310430855A CN116150073A CN 116150073 A CN116150073 A CN 116150073A CN 202310430855 A CN202310430855 A CN 202310430855A CN 116150073 A CN116150073 A CN 116150073A
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test signal
pcie
pwm test
duty cycle
signal
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CN202310430855.7A
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CN116150073B (en
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李健健
郑晓晖
朱越奇
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Guangdong Hongjun Microelectronics Technology Co.,Ltd.
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Hangzhou Hongjun Microelectronics Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides an automatic identification circuit and method for PCIe channel splitting, and relates to the field of PCIe channel splitting. The PCIe channel splitting automatic identification circuit comprises a main board, a CPU and PCIe equipment, wherein the main board is in communication connection with the CPU, and the main board is also in communication connection with the PCIe equipment through a first connector and a second connector; the main board is used for generating a first PWM test signal and a second PWM test signal, receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal, and determining a split state of the PCIe port according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal; the CPU is used for configuring the PCIe port according to the split state of the PCIe port. The PCIe channel splitting automatic identification circuit and the PCIe channel splitting automatic identification method have the advantages of high configuration efficiency and low cost.

Description

PCIe channel splitting automatic identification circuit and method
Technical Field
The application relates to the field of PCIe channel splitting, in particular to an automatic identification circuit and method for PCIe channel splitting.
Background
PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard originally named "3GIO" and was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards.
The server CPU typically has multiple PCIe ports, each typically a link width of x16, that typically support multiple channel splitting modes of operation, e.g., the PCIe ports may be split into x8+x8link width modes of operation, etc.
When the channel is split, the PCIe port of the server CPU needs to be configured, and the current common configuration mode is to configure the PCIe port of the server CPU in a manual mode, but the configuration efficiency is low and the labor cost is high.
In summary, in the prior art, when the PCIe port of the server CPU is configured in a working mode, there are problems of low configuration efficiency and high labor cost.
Disclosure of Invention
The invention aims to provide an automatic identification circuit and method for PCIe channel splitting, which are used for solving the problems of low configuration efficiency and high labor cost in the prior art that the PCIe port of a server CPU is configured with a working mode.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, an embodiment of the present application provides a PCIe lane splitting automatic identification circuit, where the PCIe lane splitting automatic identification circuit includes a motherboard, a CPU, and a PCIe device, where the motherboard includes a first connector and a second connector, where the PCIe device includes an x4 lane splitting device and/or an x8 lane splitting device, and where the x4 lane splitting device includes an inverter, where the x8 lane splitting device includes a frequency divider, where the motherboard is communicatively connected to the CPU, and where the motherboard is further communicatively connected to the PCIe device through the first connector and the second connector; wherein,
The main board is used for generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector;
the main board is further used for receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal, and determining a split state of the PCIe port according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal;
the CPU is used for configuring the PCIe port according to the split state of the PCIe port.
Optionally, the main board further includes a first output circuit, a first feedback circuit, a second output circuit, a second feedback circuit and a power module, the first output circuit and the first feedback circuit are all electrically connected with the first connector, the second output circuit and the second feedback circuit are all electrically connected with the second connector, and the first feedback circuit and the second feedback circuit are all electrically connected with the power module.
Optionally, where the PCIe device comprises an x8 lane splitting device:
When the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an undetached state;
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x8 split state;
and when the duty ratio of the first feedback signal and the second feedback signal is 100%, determining that the PCIe port is in an unused state.
Optionally, where the PCIe device comprises an x4 lane splitting device:
when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal, and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining the PCIe port as x4+x4+x4+x4 split state;
determining that the PCIe port is in a x4+x4+x8 or x8+x4+x4 split state when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal or when the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal.
Optionally, where the PCIe device includes an x4 lane splittable device and an x8 lane splittable device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x4+x4 split state;
and when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal and the duty ratio of the second feedback signal is equal to the duty ratio of the second PWM test signal, determining that the PCIe port is in a x4+x4+x8 split state.
Optionally, the duty ratio of the first PWM test signal and the second PWM test signal is different, and the motherboard is configured to send the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector simultaneously or sequentially.
Optionally, the duty ratio of the first PWM test signal and the second PWM test signal is the same, and the motherboard is configured to send the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector sequentially.
Optionally, the power module includes resistance and power, the one end of resistance is connected the power, the other end of resistance respectively with first feedback circuit, the second feedback circuit electricity is connected.
Optionally, the main board further comprises a logic unit, wherein the logic unit comprises a CPLD, an FPGA or an MCU, and the logic unit main board is in communication connection with the PCIe device through the first connector and the second connector; wherein,
the logic unit is configured to generate a first PWM test signal and a second PWM test signal, and receive the first feedback signal and the second feedback signal, so as to determine a PCIe port split state according to duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal, and the second feedback signal.
On the other hand, the embodiment of the application also provides a PCIe channel splitting automatic identification method, which is applied to a motherboard in the PCIe channel splitting automatic identification circuit, where the PCIe channel splitting automatic identification circuit includes a motherboard, a CPU, and a PCIe device, the motherboard includes a first connector and a second connector, the PCIe device includes an x4 channel splitting device and/or an x8 channel splitting device, the x4 channel splitting device includes a reverser, the x8 channel splitting device includes a frequency divider, the motherboard is in communication connection with the CPU, and the motherboard is also in communication connection with the PCIe device through the first connector and the second connector; the method comprises the following steps:
Generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector;
receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal;
determining a PCIe port split state according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal, so that the CPU configures the PCIe port according to the PCIe port split state.
Optionally, the main board further includes a first output circuit, a first feedback circuit, a second output circuit, a second feedback circuit, and a power module, where the first output circuit and the first feedback circuit are electrically connected to the first connector, the second output circuit and the second feedback circuit are electrically connected to the second connector, and the first feedback circuit and the second feedback circuit are electrically connected to the power module;
where the PCIe device comprises a x8 lane splitting device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an undetached state;
When the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100%; or when the duty cycle of the first feedback signal is equal to 100%, and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an x8+x8 split state;
and when the duty ratio of the first feedback signal and the second feedback signal is 100%, determining that the PCIe port is in an unused state.
Optionally, where the PCIe device comprises an x4 lane splitting device:
when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal, and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining the PCIe port as x4+x4+x4+x4 split state;
determining that the PCIe port is in a x4+x4+x8 or x8+x4+x4 split state when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal or when the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal.
Optionally, where the PCIe device includes an x4 lane splittable device and an x8 lane splittable device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x4+x4 split state;
and when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal and the duty ratio of the second feedback signal is equal to the duty ratio of the second PWM test signal, determining that the PCIe port is in a x4+x4+x8 split state.
Optionally, the step of generating a first PWM test signal and a second PWM test signal and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector includes:
generating a first PWM test signal and a second PWM test signal with different duty ratios, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector simultaneously or sequentially.
Optionally, the step of generating a first PWM test signal and a second PWM test signal and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector includes:
generating a first PWM test signal and a second PWM test signal with the same duty ratio, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector successively.
Compared with the prior art, the application has the following beneficial effects:
the embodiment of the application provides a PCIe channel splitting automatic identification circuit and a method, wherein the PCIe channel splitting automatic identification circuit comprises a main board, a CPU and PCIe equipment, the main board comprises a first connector and a second connector, the PCIe equipment comprises x4 channel splitting equipment and/or x8 channel splitting equipment, the x4 channel splitting equipment comprises a reverser, the x8 channel splitting equipment comprises a frequency divider, the main board is in communication connection with the CPU, and the main board is also in communication connection with the PCIe equipment through the first connector and the second connector; the main board is used for generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to PCIe equipment through a first connector and a second connector; the main board is further used for receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal, and determining a split state of the PCIe port according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal; the CPU is used for configuring the PCIe port according to the split state of the PCIe port. Because the mainboard is additionally arranged, the split state of the PCIe port is determined by utilizing the duty ratio of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal, the automatic identification of the split of the PCIe channel is realized, the automatic configuration of the PCIe port for the CPU is realized, and the effects of high configuration efficiency and low labor cost are achieved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a first PCIe lane splitting provided in an embodiment of the present application.
Fig. 2 is a schematic diagram of a second PCIe lane splitting provided in an embodiment of the present application.
Fig. 3 is a schematic diagram of a third PCIe lane splitting provided in an embodiment of the present application.
Fig. 4 is a schematic diagram of a fourth PCIe lane splitting provided in an embodiment of the present application.
Fig. 5 is a schematic diagram of a module of a PCIe lane splitting automatic identification circuit according to an embodiment of the present application.
Fig. 6 is a schematic communication diagram of a CPU and a motherboard according to an embodiment of the present application.
Fig. 7 is a first interaction schematic diagram of a motherboard and PCIe devices provided in an embodiment of the present application.
Fig. 8 is a second interaction schematic diagram of a motherboard and PCIe device according to an embodiment of the present application.
Fig. 9 is a third interaction schematic diagram of a motherboard and PCIe device according to an embodiment of the present application.
Fig. 10 is a fourth interaction schematic diagram of a motherboard and PCIe device according to an embodiment of the present application.
Fig. 11 is an exemplary flowchart of a PCIe lane splitting automatic identification method provided in an embodiment of the present application.
In the figure: 110-a motherboard; 120-CPU;130-PCIe device.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As described in the background, in the server CPU of the prior art, PCIe ports are generally of link width x16, and can support multiple channel splitting operation modes. Generally, the x16 slot of the PCIe port has a total length of 89mm, 164 pins, a bayonet near the outside end of the motherboard, dividing 16x into front and rear groups, 22 pins in the shorter slot, which is mainly used for power supply, 142 pins in the longer slot, which is mainly used for data transmission, and has a high bandwidth brought by 16 channels.
For example, referring to fig. 1, it may be considered that PCIe ports with link width of x16 are divided into 4 groups of slots, if x16 channels are allocated in slot 0, and no channels are allocated in slots 1, 2 and 3, the PCIe ports in fig. 1 operate in a mode of x16 link width, and no channel splitting is performed substantially.
Referring to fig. 2, in the second mode of operation, the x8 channel may be allocated in slot 0, the x8 channel may be allocated in slot 2, and no channels may be allocated in slots 1 and 3, where the PCIe port in fig. 2 operates in a mode of x8+x8link width.
Referring to fig. 3, in a third mode of operation, the x8 channel may be allocated in slot 0, the x4 channel may be allocated in slot 2, the x4 channel may be allocated in slot 3, and the channel may not be allocated in slot 1, where the PCIe port in fig. 3 operates in a mode of x8+x4+x4 link width. Of course, in practical application, the working mode of the PCIe port may also be x4+x4+x8 link width, which is not limited herein.
Referring to fig. 4, in a fourth mode of operation, x4 channels may be allocated in slot 0, slot 1, slot 2 and slot 3 respectively, at this point the PCIe port of FIG. 4 is operating mode is x4+x4+x4 +x4link width.
For the server CPU, the PCIe port may be connected to a plurality of PCIe devices of different types, such as GPU (graphics processing unit) cards, NVMe (non-volatile memory controller interface specification) solid state disk, raid (Redundant Arrays of Independent Disks) cards, network cards, OCP network cards, etc., where the PCIe link width requirements of each device are different, for example, GPU cards often need a PCIe link width of x16, and NVMe SDD is a PCIe link width of x 4. Alternatively, a PCIe card would normally need to be inserted into a PCIe slot of a host or server, the slot specifications and configuration being the same as the card. However, in some scenarios, PCIe cards may also be mounted to a wider slot in the face of, for example, a shortage of slots. For example, in the case where a PCIe x8 slot is already occupied, a PCIe x8 card may be placed into a PCIe x16 slot, but the card will always run in PCIe x8 mode, or a PCIe x4 card may be placed into a PCIe x16 slot, the card running in PCIe x4 mode.
Based on the above, when the PCIe port channel splitting is required, the PCIe port needs to be configured, for example, when the working mode of the PCIe port is x8+x8link width, the PCIe port needs to be configured, so as to implement the channel splitting. According to the conventional method, a default PCIe split is set in the BIOS according to different configurations, and the PCIe channel split is manually adjusted, so that the PCIe channel split is realized by manual adjustment in the BIOS. However, thousands to tens of thousands of servers are often deployed in a large data center, and modern general-purpose servers are flexible in configuration, and each model usually has a plurality of different configurations, and each PCIe port of each configured CPU is used in a different manner, so that the split requirement of each configuration possible PCIe is different. The existing manual method is adopted to realize configuration, automatic deployment cannot be achieved, deployment efficiency is low, and manpower is wasted.
In view of this, this application provides an automatic identification circuit of PCIe passageway split, through the mode of addding the mainboard, realizes the automatic identification to PCIe port split state, reaches the effect that promotes configuration efficiency, reduces the human cost.
The PCIe lane splitting automatic identification circuit provided in the present application is described in the following as an example:
As an alternative implementation manner, referring to fig. 5, the PCIe channel splitting automatic identification circuit includes a motherboard 110, a CPU120, and a PCIe device 130, where the motherboard 110 includes a first connector and a second connector, the PCIe device 130 includes an x4 channel splitting device and/or an x8 channel splitting device, and the x4 channel splitting device includes an inverter, the x8 channel splitting device includes a frequency divider, the motherboard 110 is communicatively connected to the CPU120, and the motherboard 110 is also communicatively connected to the PCIe device 130 through the first connector and the second connector; the motherboard 110 is configured to generate a first PWM test signal and a second PWM test signal, and send the first PWM test signal and the second PWM test signal to the PCIe device 130 through the first connector and the second connector; the motherboard 110 is further configured to receive a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal, and determine a PCIe port split state according to duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal, and the second feedback signal; the CPU120 is configured to configure the PCIe port according to the PCIe port split state.
In one implementation, referring to fig. 6, the motherboard 110 is communicatively connected to the CPU120 through an I2C or SPI bus, and the motherboard 110 further includes a logic unit, where the logic unit includes a CPLD, an FPGA, or an MCU, and the logic unit motherboard 110 is communicatively connected to the PCIe device 130 through a first connector and a second connector; the logic unit is configured to generate a first PWM test signal and a second PWM test signal, and receive a first feedback signal and a second feedback signal, so as to determine a PCIe port split state according to duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal, and the second feedback signal.
Through the implementation mode, the split condition of each PCIe port of the CPU can be detected and collected through the CPLD or the FPGA or the MCU, and the split condition is reported to the CPU through the I2C or the SPI bus.
In addition, referring to fig. 7, the motherboard further includes a first output circuit, a first feedback circuit, a second output circuit, a second feedback circuit, and a power module, where the first output circuit and the first feedback circuit are electrically connected to the first connector, the second output circuit and the second feedback circuit are electrically connected to the second connector, and the first feedback circuit and the second feedback circuit are electrically connected to the power module. Meanwhile, the first output circuit, the first feedback circuit, the second output circuit and the second feedback circuit of the logic unit are all electrically connected, and the test signal is sent and the feedback signal is received through the four circuits.
The power module comprises a resistor and a power supply, one end of the resistor is connected with the power supply, and the other end of the resistor is respectively and electrically connected with the first feedback circuit and the second feedback circuit.
The PCIe device also comprises a first connector and a second connector, and the second connector of the main board is in communication connection with the second connector of the PCIe device through a second cable.
The following detailed analysis of different resolution cases:
In a first scenario, referring to fig. 7, in a PCIe device including an x8 channel splitting device, the x8 channel splitting device indicates a device capable of splitting a PCIe port into an x8 PCIe link width, for example, a PCIe standard card or the like, where the PCIe standard card supports two PCIe link width splitting application modes of x8 and x 16. In this configuration mode, the motherboard and PCIe card backplane each employ 2 MCIO connectors (i.e., a first connector and a second connector), each MCIO connector having a PCIe signal of x8, the 2 MCIO connectors being capable of passing PCIe signals of x 16. The main board and the PCIe standard card backboard adopt MCIO cables (namely, a first cable and a second cable) to realize PCIe signal connection, a first connector of the main board is connected with a first connector on the PCIe standard card backboard through the first cable, and a second connector of the main board is connected with a second connector on the PCIe standard card backboard through the second cable. There is no CPLD on the PCIe card backplane. The main board CPLD/FPGA/MCU generates 2 first PWM test signals and 2 PWM test signals, namely PWM1 and PWM2, wherein the PWM1 returns to the main board CPLD/FPGA/MCU in a primary way through a first cable, and returns to the main board CPLD/FPGA/MCU through a second cable after being reversed on a PCIe label card backboard through an inverter. The first feedback signal and the second feedback signal are LOOPBACK_PWM1 and LOOPBACK_PWM2, respectively. The CPLD/FPGA/MCU of the main board judges the split condition of the PCIe port of the CPU by judging the duty ratio of the returned PWM signal.
Specifically, when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an undeployed state;
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x8 split state;
and when the duty ratio of the first feedback signal and the second feedback signal is 100%, determining that the PCIe port is in an unused state.
For example, when PWM1 outputs a PWM signal with 11% duty cycle, PWM2 outputs a PWM signal with 17% duty cycle, lopback_pwm1 returns an 11% duty cycle PWM signal, and lopback_pwm2 returns an 89% duty cycle PWM signal, indicating that in this case both cable 1 and cable 2 are in place, the PCIe device on the PCIe card backplane is a PCIe x16 device, the PCIe port is in an undeployed state, and the system needs to configure PCIe to x16.
Referring to fig. 8, when PWM1 outputs a PWM signal with 11% duty cycle, PWM2 outputs a PWM signal with 17% duty cycle, and lopback_pwm 1 returns an PWM signal with 11% duty cycle, and lopback_pwm 2 returns an PWM signal with 17% duty cycle, it is stated that in this case, cable 1 and cable 2 form two separate loops and are all in place, PCIe devices on the PCIe card back board are PCIe x8 devices, PCIe ports are in an x8+x8 split state, and the system needs to configure PCIe in an x8+x8 mode.
When PWM1 outputs a PWM signal with 11% duty cycle, PWM2 outputs a PWM signal with 17% duty cycle, and lock_pwm 1 returns a PWM signal with 100% duty cycle, and lock_pwm 2 returns a PWM signal with 100% duty cycle, which indicates that neither cable 1 nor cable 2 is in place in this situation, and the PCIe port is in an unused state, and the system needs to configure PCIe in disable mode.
Of course, the above duty cycle is only an example, and in practical application, other duty cycles, such as 20% or 40% duty cycle, etc. may be used.
In a second scenario, referring to FIG. 9, the PCIe device includes a x4 lane splitting device. The x4 channel splitting device represents a device capable of splitting a PCIe port into a PCIe link width of x4, for example, the device can be an NVMe hard disk backboard and other devices, a CPLD (integrated circuit) is arranged on the NVMe hard disk backboard, PWM signals sent by a main board CPLD/FPGA/MCU are sent to the CPLD of the backboard through a cable, and after receiving the PWM signals sent by the main board, the backboard CPLD returns to the main board CPLD/FPGA/MCU after dividing the frequency by 2. If the CPLD/FPGA/MCU detects that the duty ratio of the first feedback signal LOOP_PWM1 and the second feedback signal LOOP_PWM2 returned by the NVMe hard disk backboard is half of the duty ratio of the first PWM test signal and the second PWM test signal sent by the CPLD/FPGA/MCU, the PCIe port is considered to be connected with NVMe equipment, and the PCIe port needs to be split into 4 x4 for use.
At this time, when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal, and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining a PCIe port as x4+x4+x4+x4 split state;
when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to the duty cycle of the second PWM test signal, or when the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal, determining that the PCIe port is in a x4+x8 or x8+x4+x4 split state.
For example, the duty cycles of the first PWM test signal and the second PWM test signal are 22% and 34%, respectively, when the duty cycles of the first feedback signal and the second feedback signal are 11% and 17% respectively, then the PCIe port is determined to be x4 +. X4+x4+x4 split state.
And the CPLD/FPGA/MCU of the main board records the split state of the PCIe port into a register thereof, and the system BIOS reads the split requirement of the PCIe port through the I2C or SPI bus, thereby finishing PCIe initialization and realizing automatic configuration of the PCIe port.
In a third scenario, referring to fig. 10, a pcie device includes an x4 lane splittable device and an x8 lane splittable device, based on which,
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half of the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x4+x4 split state;
and when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal and the duty ratio of the second feedback signal is equal to the duty ratio of the second PWM test signal, determining that the PCIe port is in the x4+x4+x8 split state.
For example, the duty cycle of the first PWM test signal and the second PWM test signal are 22% and 34%, respectively, and when the duty cycle of the first feedback signal is 22% and the duty cycle of the second feedback signal is 17%, the PCIe port is determined to be in the x8+x4+x4 split state.
And when the duty cycle of the first feedback signal is 11% and the duty cycle of the second feedback signal is 34%, determining that the PCIe port is in the x4+x4+x8 split state.
Similarly, after determining the port splitting state, the motherboard CPLD/FPGA/MCU records the splitting state of the PCIe port into a register thereof, and the system BIOS reads the splitting requirement of the PCIe port and accordingly completes PCIe initialization to realize automatic configuration of the PCIe port.
It should be noted that, in the above example, the duty ratios of the first PWM test signal and the second PWM test signal are different, and the motherboard is configured to send the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector simultaneously or sequentially.
In another implementation, the duty cycle of the first PWM test signal and the second PWM test signal is the same, for example, the first PWM test signal and the second PWM test signal are both 20% or both 40%, and the motherboard is configured to send the first PWM test signal and the second PWM test signal to the PCIe device sequentially through the first connector and the second connector.
Based on the implementation manner, the embodiment of the application further provides a PCIe channel splitting automatic identification method, which is applied to the above-mentioned motherboard, wherein the PCIe channel splitting automatic identification circuit comprises a motherboard, a CPU and a PCIe device, the motherboard comprises a first connector and a second connector, the PCIe device comprises an x4 channel splitting device and/or an x8 channel splitting device, the x4 channel splitting device comprises a reverser, the x8 channel splitting device comprises a frequency divider, the motherboard is in communication connection with the CPU, and the motherboard is also in communication connection with the PCIe device through the first connector and the second connector; referring to fig. 11, the method includes:
S102, generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to PCIe equipment through a first connector and a second connector;
s104, receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal;
s106, determining a split state of the PCIe port according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal, so that the CPU configures the PCIe port according to the split state of the PCIe port.
The main board further comprises a first output circuit, a first feedback circuit, a second output circuit, a second feedback circuit and a power module, wherein the first output circuit and the first feedback circuit are electrically connected with the first connector, the second output circuit and the second feedback circuit are electrically connected with the second connector, and the first feedback circuit and the second feedback circuit are electrically connected with the power module;
where the PCIe device comprises a x8 lane splitting device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an undetached state;
When the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal, and the duty cycle of the second feedback signal is equal to 100%; or when the duty ratio of the first feedback signal is equal to 100%, and the duty ratio of the second feedback signal is equal to 100% -the duty ratio of the first PWM test signal, determining that the PCIe port is in an x8+x8 split state;
and when the duty ratio of the first feedback signal and the second feedback signal is 100%, determining that the PCIe port is in an unused state.
Where the PCIe device comprises an x4 lane splittable device:
when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal, and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining a PCIe port as x4+x4+x4+x4 split state;
determining that the PCIe port is in a x4+x8 or x8+x4+x4 split state when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal or when the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal.
In the case where the PCIe device includes an x4 lane splittable device and an x8 lane splittable device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half of the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x4+x4 split state;
and when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal and the duty ratio of the second feedback signal is equal to the duty ratio of the second PWM test signal, determining that the PCIe port is in the x4+x4+x8 split state.
Specifically, the step of S102 includes:
generating a first PWM test signal and a second PWM test signal with different duty ratios, and sending the first PWM test signal and the second PWM test signal to PCIe equipment through a first connector and a second connector simultaneously or successively.
Alternatively, the step of S102 includes:
and generating a first PWM test signal and a second PWM test signal with the same duty ratio, and sequentially sending the first PWM test signal and the second PWM test signal to PCIe equipment through a first connector and a second connector.
In summary, the embodiment of the application provides a PCIe lane splitting automatic identification circuit and method, where the PCIe lane splitting automatic identification circuit includes a motherboard, a CPU, and a PCIe device, the motherboard includes a first connector and a second connector, the PCIe device includes an x4 lane splitting device and/or an x8 lane splitting device, the x4 lane splitting device includes a reverser, the x8 lane splitting device includes a frequency divider, the motherboard is in communication connection with the CPU, and the motherboard is also in communication connection with the PCIe device through the first connector and the second connector; the main board is used for generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to PCIe equipment through a first connector and a second connector; the main board is further used for receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal, and determining a split state of the PCIe port according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal; the CPU is used for configuring the PCIe port according to the split state of the PCIe port. Because the mainboard is additionally arranged, the split state of the PCIe port is determined by utilizing the duty ratio of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal, the automatic identification of the split of the PCIe channel is realized, the automatic configuration of the PCIe port for the CPU is realized, and the effects of high configuration efficiency and low labor cost are achieved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (15)

1. The PCIe channel splitting automatic identification circuit is characterized by comprising a main board, a CPU and PCIe equipment, wherein the main board comprises a first connector and a second connector, the PCIe equipment comprises x4 channel splitting equipment and/or x8 channel splitting equipment, the x4 channel splitting equipment comprises a reverser, the x8 channel splitting equipment comprises a frequency divider, the main board is in communication connection with the CPU, and the main board is also in communication connection with the PCIe equipment through the first connector and the second connector; wherein,
The main board is used for generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector;
the main board is further used for receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal, and determining a split state of the PCIe port according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal;
the CPU is used for configuring the PCIe port according to the split state of the PCIe port.
2. The PCIe lane splitting automatic identification circuit of claim 1 wherein the motherboard further comprises a first output line, a first feedback line, a second output line, a second feedback line, and a power module, the first output line and the first feedback line each electrically connected to the first connector, the second output line and the second feedback line each electrically connected to the second connector, and the first feedback line and the second feedback line each electrically connected to the power module.
3. The PCIe lane splitting auto-id circuit of claim 2, wherein in the case where the PCIe device comprises a x8 lane splitting capable device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an undetached state;
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x8 split state;
and when the duty ratio of the first feedback signal and the second feedback signal is 100%, determining that the PCIe port is in an unused state.
4. The PCIe lane splitting auto-id circuit of claim 2, wherein in the case where the PCIe device comprises a x4 lane splitting capable device:
when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal, and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining the PCIe port as x4+x4+x4+x4 split state;
Determining that the PCIe port is in a x4+x4+x8 or x8+x4+x4 split state when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal or when the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal.
5. The PCIe lane splitting auto-id circuit of claim 2, wherein in the case where the PCIe device comprises an x4 lane splitting device and an x8 lane splitting device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x4+x4 split state;
and when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal and the duty ratio of the second feedback signal is equal to the duty ratio of the second PWM test signal, determining that the PCIe port is in a x4+x4+x8 split state.
6. The PCIe lane splitting automatic identification circuit of any one of claims 3-5 wherein the first PWM test signal and the second PWM test signal have different duty cycles and the motherboard is configured to send the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector simultaneously or sequentially.
7. The PCIe lane splitting automatic identification circuit of claim 4 or 5, wherein the first PWM test signal and the second PWM test signal have the same duty cycle, and the motherboard is configured to send the first PWM test signal and the second PWM test signal to the PCIe device sequentially through the first connector and the second connector.
8. The PCIe lane splitting automatic identification circuit of claim 2 wherein the power module comprises a resistor and a power source, one end of the resistor is connected to the power source, and the other end of the resistor is electrically connected to the first feedback line and the second feedback line, respectively.
9. The PCIe lane splitting automatic identification circuit of claim 1 wherein the motherboard further comprises a logic unit comprising a CPLD, FPGA or MCU, the logic unit motherboard communicatively connected to the PCIe device through the first connector, the second connector; wherein,
The logic unit is configured to generate a first PWM test signal and a second PWM test signal, and receive the first feedback signal and the second feedback signal, so as to determine a PCIe port split state according to duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal, and the second feedback signal.
10. The PCIe lane splitting automatic identification method is applied to a main board in a PCIe lane splitting automatic identification circuit according to any one of claims 1 to 9, wherein the PCIe lane splitting automatic identification circuit comprises a main board, a CPU and a PCIe device, the main board comprises a first connector and a second connector, the PCIe device comprises an x4 lane splitting device and/or an x8 lane splitting device, the x4 lane splitting device comprises an inverter, the x8 lane splitting device comprises a frequency divider, the main board is in communication connection with the CPU, and the main board is also in communication connection with the PCIe device through the first connector and the second connector; the method comprises the following steps:
generating a first PWM test signal and a second PWM test signal, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector;
Receiving a first feedback signal and a second feedback signal generated based on the first PWM test signal and the second PWM test signal;
determining a PCIe port split state according to the duty ratios of the first PWM test signal, the second PWM test signal, the first feedback signal and the second feedback signal, so that the CPU configures the PCIe port according to the PCIe port split state.
11. The PCIe lane splitting automatic identification method of claim 10 wherein said motherboard further comprises a first output line, a first feedback line, a second output line, a second feedback line, and a power module, said first output line and said first feedback line each electrically connected to said first connector, said second output line and said second feedback line each electrically connected to said second connector, said first feedback line and said second feedback line each electrically connected to said power module;
where the PCIe device comprises a x8 lane splitting device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an undetached state;
When the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to 100%; or when the duty cycle of the first feedback signal is equal to 100%, and the duty cycle of the second feedback signal is equal to 100% -the duty cycle of the first PWM test signal, determining that the PCIe port is in an x8+x8 split state;
and when the duty ratio of the first feedback signal and the second feedback signal is 100%, determining that the PCIe port is in an unused state.
12. The PCIe lane splitting auto-identification method of claim 11, wherein in the case where the PCIe device comprises a x4 lane splitting capable device:
when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal, and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining the PCIe port as x4+x4+x4+x4 split state;
determining that the PCIe port is in a x4+x4+x8 or x8+x4+x4 split state when the duty cycle of the first feedback signal is equal to half the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal or when the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal.
13. The PCIe lane splitting auto-identification method of claim 11, wherein in the case where the PCIe device comprises a x4 lane splitting device and a x8 lane splitting device:
when the duty cycle of the first feedback signal is equal to the duty cycle of the first PWM test signal and the duty cycle of the second feedback signal is equal to half the duty cycle of the second PWM test signal, determining that the PCIe port is in an x8+x4+x4 split state;
and when the duty ratio of the first feedback signal is equal to half of the duty ratio of the first PWM test signal and the duty ratio of the second feedback signal is equal to the duty ratio of the second PWM test signal, determining that the PCIe port is in a x4+x4+x8 split state.
14. The PCIe lane splitting automatic identification method of claim 10 wherein the steps of generating a first PWM test signal and a second PWM test signal and transmitting the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector comprise:
generating a first PWM test signal and a second PWM test signal with different duty ratios, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector simultaneously or sequentially.
15. The PCIe lane splitting automatic identification method of claim 10 wherein the steps of generating a first PWM test signal and a second PWM test signal and transmitting the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector comprise:
generating a first PWM test signal and a second PWM test signal with the same duty ratio, and sending the first PWM test signal and the second PWM test signal to the PCIe device through the first connector and the second connector successively.
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