CN116148741A - Self-checking system for semiconductor testing machine - Google Patents
Self-checking system for semiconductor testing machine Download PDFInfo
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- CN116148741A CN116148741A CN202310066100.3A CN202310066100A CN116148741A CN 116148741 A CN116148741 A CN 116148741A CN 202310066100 A CN202310066100 A CN 202310066100A CN 116148741 A CN116148741 A CN 116148741A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention provides a self-checking system for a semiconductor testing machine, which can diagnose the reliability of the testing machine and ensure the reliability of the testing result of a semiconductor product; the resource board of the semiconductor tester to be tested is connected with the diagnosis board through the PC control end, and the PC control end calls the resource data in the resource board and inputs the resource data into the diagnosis board; the resource board controls the diagnosis board to diagnose; the diagnosis board is provided with a voltage current source module circuit for realizing detection of a VI source of the resource board; the DIO module circuit is used for realizing DIO resource detection of the resource board; the QTMU module circuit is used for realizing QTMU resource detection of the resource board; the ACSM module circuit is used for detecting ACM and ACS resources of the resource board; the POWER module circuit is used for providing detection POWER supply; the CBIT module circuit is used for realizing voltage detection of CBIT resources of the resource board; and the input/output detection module circuit is used for receiving the voltage current source detection data of the voltage current source module circuit, comparing the voltage current source detection data with a set reference value and outputting a comparison result.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a self-checking system for a semiconductor testing machine.
Background
In the process of manufacturing semiconductor products, to ensure the quality of the manufactured products, semiconductor test machines are often used to test the electrical properties of the semiconductor products to ensure that the circuit structure of the semiconductor products is free from open circuits, short circuits or other damage. However, due to the problems of testing equipment, various devices, cable aging and the like, the cable in the testing machine is damaged, the relay is adhered to cause the testing machine to fail, and further misjudgment of the detection result is caused, so that huge cost loss is caused, and in order to ensure the reliability of the testing result of the semiconductor product, the self-inspection of each part of the testing machine is required.
Disclosure of Invention
In view of the above problems, the present invention provides a self-inspection system for a semiconductor tester, which can perform reliability diagnosis on the tester, thereby ensuring the reliability of the test results of semiconductor products.
The technical scheme is as follows: the self-checking system for the semiconductor testing machine is characterized by comprising a diagnosis board, wherein a resource board of the semiconductor testing machine to be tested is connected with the diagnosis board through a PC control end, and the PC control end calls resource data in the resource board and inputs the resource data into the diagnosis board; the resource board is connected with the diagnosis board to control the diagnosis board to perform diagnosis;
the diagnosis board is provided with a voltage current source module circuit, a DIO module circuit, a QTMU module circuit, an ACSM module circuit, a POWER module circuit, a CBIT module circuit and an input/output detection module circuit;
the voltage current source module circuit is used for detecting a VI source of the resource board;
the DIO module circuit is used for realizing DIO resource detection of the resource board;
the QTMU module circuit is used for realizing QTMU resource detection of the resource board;
the ACSM module circuit is used for detecting ACM and ACS resources of the resource board;
the POWER module circuit is used for providing detection POWER supply;
the CBIT module circuit is used for realizing voltage detection of CBIT resources of the resource board;
and the input/output detection module circuit is connected with the voltage current source module circuit and is used for receiving the voltage current source detection data of the voltage current source module circuit, comparing the voltage current source detection data with a set reference value and outputting a comparison result.
It is further characterized by:
the input/output detection module circuit comprises relays F1-F7, light emitting diodes V1-V7, resistors RD 1-RD 7, resistors R1-R13 and an interface X1, wherein the interface X1 is a CBIT control bit European interface; the relay F3, the resistors R5, R4 and RD3 and the light emitting diode V3 are connected to form a forceH detection circuit; the sensor H detection circuit is formed by connecting the relay F2, the resistors R2, R3 and RD2 and the light emitting diode V2; the relay F6, the resistors R10, R11, RD5 and the light emitting diode V6 are connected to form a forceL detection circuit; the sensor L detection circuit is formed by connecting the relay F5, the resistors R8, R9 and RD6 and the light-emitting diode V5; the forceH detection circuit is used for detecting forceH loops in the voltage current source module circuit; the sensor H detection circuit is used for detecting a sensor H loop in the voltage current source module circuit; the forceL detection circuit is used for detecting forceL loops in the voltage-current source module circuit; the sensor L detection circuit is used for detecting a sensor L loop in the voltage current source module circuit;
the voltage current source module circuit comprises relays F8-F11, resistors R14-R17 and interfaces X2-X4; the VI source comprises FOVI and FPVI resources, the interface X2 is a CBIT control bit European interface, the interface X3 is a FOVI 0-3 resource European interface, and the interface X4 is a FPVI 0-3 resource European interface; the contact ends of the relays F8-F11 are respectively and correspondingly connected to the contact ends of the relay F1; the relays F8, F9 and the resistors R14 and R15 are connected to realize FOVI resource detection; the relays F10, F11 and the resistors R16 and R17 are connected to realize FPVI resource detection;
the QTMU module circuit comprises interfaces X5 and X6 which are connected with each other, wherein the interface X5 is a QTMU resource European interface and is used for providing QTMU 0A-3B resources; the interface X6 is a CBIT control bit European interface and is used for providing diagnostic voltage for QTMU0A, QTMU 0B, QTMU 1A, QTMU 1B, QTMU 2A, QTMU 2B, QTMU 3A, QTMU3B resources respectively to realize QTMU resource detection;
the ACSM module circuit comprises resistors R18-R25 and interfaces X7 and X8, wherein the interface X7 is an European interface of ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, ACM 3-resource; the interface X8 is a CBIT control bit European interface and is used for providing corresponding control bits to realize ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, ACM 3-resource detection;
the POWER module circuit comprises relays F13-F16, resistors R26-R33 and an interface X9, wherein one end contacts of the relays F13-F16 are connected and then connected to a FHc contact end of the relay F1, and the interface X9 is a CBIT control bit European interface and is used for providing corresponding control bits so that the POWER module circuit is connected to the forceH detection circuit, thereby realizing the provision of detection voltage;
the CBIT module circuit comprises a relay F17, resistors R34 and R35, a resistor-discharging PRC, a triode Q1 and an interface X10, wherein the resistor-discharging PRC is connected between the relay F17 and a CBIT board card on the resource board, and the interface X10 is a CBIT control bit European interface and is used for providing corresponding control bits to realize voltage detection of CBIT resources on the CBIT board card;
the DIO module circuit comprises an interface X11, input/output ports DIO 0-DIO 15 are correspondingly connected to the interface X11, and the interface X11 is a CBIT control bit European interface and is used for providing corresponding control bits to realize voltage detection of the input/output ports DIO 0-DIO 15.
The invention has the beneficial effects that the resource data in the resource board of the semiconductor testing machine to be tested can be called by the PC control end to be input into the diagnosis board, and when diagnosis is needed, the control of each functional module in the diagnosis board is correspondingly detected by the resource board, so that the reliability detection of the semiconductor testing machine can be realized, the reliability of the testing result of the semiconductor product is further ensured, and the invention has better economic use value.
Drawings
FIG. 1 is a block diagram of the structure of the present invention;
FIG. 2 is a schematic circuit diagram of an input/output detection module according to the present invention;
FIG. 3 is a schematic diagram of a voltage current source module circuit of the present invention;
FIG. 4 is a schematic circuit diagram of the QTMU module of the present invention;
FIG. 5 is a schematic circuit diagram of an ACSM module of the present invention;
FIG. 6 is a schematic circuit diagram of the POWER module of the present invention;
FIG. 7 is a schematic diagram of a CBIT module circuit of the present invention;
fig. 8 is a schematic diagram of DIO module circuitry of the present invention.
Detailed Description
The present application is described and illustrated below with reference to the accompanying drawings and examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific examples described herein are for purposes of illustration only and are not intended to limit the present application. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
As shown in fig. 1 to 8, the self-checking system for a semiconductor tester of the present invention includes a diagnosis board, a resource board of the semiconductor tester to be tested is connected with the diagnosis board through a PC control terminal, and the PC control terminal invokes resource data in the resource board to be input into the diagnosis board; the resource board is connected with the diagnosis board to control the diagnosis board to perform diagnosis;
the diagnosis board is provided with a voltage current source module circuit, a DIO module circuit, a QTMU module circuit, an ACSM module circuit, a POWER module circuit, a CBIT module circuit and an input/output detection module circuit;
the voltage current source module circuit is used for detecting a VI source of the resource board;
the DIO module circuit is used for realizing DIO resource detection of the resource board;
the QTMU module circuit is used for realizing QTMU resource detection of the resource board;
the ACSM module circuit is used for detecting ACM and ACS resources of the resource board;
the POWER module circuit is used for providing detection POWER supply;
the CBIT module circuit is used for realizing voltage detection of CBIT resources of the resource board;
the input/output detection module circuit is connected with the voltage current source module circuit and is used for receiving the voltage current source detection data of the voltage current source module circuit, comparing the voltage current source detection data with a set reference value and outputting a comparison result.
The input/output detection module circuit comprises relays F1-F7, light emitting diodes V1-V7, resistors RD 1-RD 7, resistors R1-R13 and an interface X1, wherein the interface X1 is a CBIT control bit European interface; the ForceH detection circuit is formed by connecting a relay F3, resistors R5, R4, RD3 and a light emitting diode V3; the sensor H detection circuit is formed by connecting a relay F2, resistors R2, R3, RD2 and a light emitting diode V2; the ForceL detection circuit is formed by connecting a relay F6, resistors R10, R11, RD5 and a light emitting diode V6; the sensor L detection circuit is formed by connecting a relay F5, resistors R8, R9 and RD6 and a light emitting diode V5; the forceH detection circuit is used for detecting forceH loops in the voltage current source module circuit; the sensor H detection circuit is used for detecting a sensor H loop in the voltage current source module circuit; the forceL detection circuit is used for detecting forceL loops in the voltage current source module circuit; the sensor L detection circuit is used for detecting a sensor L loop in the voltage current source module circuit.
The voltage current source module circuit comprises relays F8-F11, resistors R14-R17 and interfaces X2-X4; the VI source comprises FOVI and FPVI resources, the interface X2 is a CBIT control bit European interface, the interface X3 is a FOVI 0-3 resource European interface, and the interface X4 is a FPVI 0-3 resource European interface; the contact ends of the relays F8-F11 are correspondingly connected to the contact ends of the relay F1; the FOVI resource detection is realized through connection of relays F8, F9 and resistors R14 and R15; the FPVI resource detection is realized by connecting relays F10, F11 and resistors R16 and R17;
the detection principle of the voltage current source module circuit is that detection voltage and current are provided by adjacent FOVI and pass through the input/output detection module circuit, and then the FOVI detects loop voltage and current, namely, if the control bits CBIT56 and CBIT58 control the relays F8 and F9 to be connected to the SHc and FHc ends (namely, to be connected to the input/output detection module); the FOVI SH0 and the FOVI FH0 measure voltage and current values, and the measured values are compared with set reference values after the measurement, so that diagnosis of the loop cable and the FOVI resource is realized; control bits CBIT25 and CBIT26 control relays F10 and F11 to be connected to SHc and FHc ends (i.e. to be connected to the input/output detection module); the FPVI SH0 and the FPVI FH0 measure the loop voltage and current values, and the measured values are compared with the set reference values after the measurement, so that the diagnosis of loop cables and FPVI resources is realized.
The QTMU module circuit comprises interfaces X5 and X6 which are connected with each other, wherein the interface X5 is a QTMU resource European interface and is used for providing QTMU 0A-3B resources; the interface X6 is a CBIT control bit European interface and is used for providing diagnostic voltage for QTMU0A, QTMU 0B, QTMU 1A, QTMU 1B, QTMU 2A, QTMU 2B, QTMU 3A, QTMU3B resources respectively to realize QTMU resource detection; the detection principle is that control bits CBIT65, CBIT67, CBIT69, CBIT71, CBIT73, CBIT75, CBIT77 and CBIT79 respectively provide diagnostic voltages for QTMU0A, QTMU 0B, QTMU 1A, QTMU 1B, QTMU 2A, QTMU 2B, QTMU 3A, QTMU B resources to realize QTMU resource diagnosis. For example, the control bit CBIT65 provides a detection voltage, the detection voltage is connected to QTMU0A by CBIT, and then the QTMU0A of the interface X5 performs waveform period and output detection.
The ACSM module circuit comprises resistors R18-R25, interfaces X7 and X8, wherein the interface X7 is an ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, ACM 3-resource European interface; the interface X8 is a CBIT control bit European interface and is used for providing corresponding control bits to realize ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, ACM 3-resource detection; the detection principle is that +5V provides voltage, ACS0, ACS1, ACS2 and ACS3 provide periodic alternating current waveform output, and control bits CBIT37, CBIT 39, CBIT 41 and CBIT 43 control to realize diagnosis of ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, ACM 3-resources and circuits. For example, ACSM0 is detected, ACS0 provides periodic alternating current waveform, and ACM0+ and ACM 0-measured time domain data are controlled by control bits in different states.
The POWER module circuit comprises relays F13-F16, resistors R26-R33 and an interface X9, wherein one end contacts of the relays F13-F16 are connected and then connected to a FHc contact end of the relay F1, and the interface X9 is a CBIT control bit European interface and is used for providing corresponding control bits so that the POWER module circuit is connected to a forceH detection circuit, thereby realizing the provision of detection voltage; the POWER module circuit can also detect +5V, +15V, -15V and +12V POWER voltages, for example, the detection principle of +5V voltages is that the control bit CBIT97 controls the relay F13 to be closed so as to switch on +5V POWER supply to the forceH detection circuit, and then the control bit CBIT58 closes FOVI resources to detect the forceH detection circuit.
The CBIT module circuit comprises a relay F17, resistors R34 and R35, a resistor PRC, a triode Q1 and an interface X10, wherein the resistor PRC is connected between the relay F17 and the CBIT board, and the interface X10 is a European plug interface of a CBIT control bit and is used for providing corresponding control bits to realize voltage detection of CBIT resources on the CBIT board. The CBIT board is arranged on the resource board and is used for providing 128-bit CBIT control bits.
The DIO module circuit comprises an interface X11, input and output ports DIO 0-DIO 15 on the resource board are correspondingly connected with the interface X11, the interface X11 is a CBIT control bit European interface and is used for providing corresponding control bits to realize voltage detection of the input and output ports DIO 0-DIO 15; the diagnosis principle is that 8-bit CBIT control bits of CBIT96, CBIT98, CBIT100, CBIT102, CBIT104, CBIT106, CBIT108 and CBIT110 provide detection sources to realize the diagnosis of DIO 0; detection of DIO1 is achieved by a detection source provided by the 8-bit CBIT control bits of CBIT112, CBIT114, CBIT116, CBIT118, CBIT120, CBIT122, CBIT124, CBIT 126.
When the resource diagnosis is carried out on the semiconductor testing machine to be tested, the corresponding resource data is called by the PC control end and is input into the diagnosis board, and the corresponding CBIT control bit is provided by the CBIT board card on the resource board to control the corresponding functional module to realize the diagnosis detection, so that the reliability detection of the semiconductor testing machine can be realized; the DIO module circuit and the QTMU module circuit on the diagnosis board are detected by using CBIT driving only directly; the control bit on the European interface of the control bit of the diagnosis board is correspondingly connected to the CBIT board card; the European interfaces of the resources on the diagnosis board are correspondingly connected to the resource board.
Wherein, FOVI represents a floating eight-channel voltage/current source;
FPVI represents a floating dual channel power voltage/current source;
DIO means digital channel module;
QTMU represents a four-way time measurement unit;
ACSM represents a precision ac source table;
the CBIT board card on the resource board is equivalent to a user board control module for providing CBIT control bits to realize corresponding control diagnosis.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (8)
1. The self-checking system for the semiconductor testing machine is characterized by comprising a diagnosis board, wherein a resource board of the semiconductor testing machine to be tested is connected with the diagnosis board through a PC control end, and the PC control end calls resource data in the resource board and inputs the resource data into the diagnosis board; the resource board is connected with the diagnosis board to control the diagnosis board to perform diagnosis;
the diagnosis board is provided with a voltage current source module circuit, a DIO module circuit, a QTMU module circuit, an ACSM module circuit, a POWER module circuit, a CBIT module circuit and an input/output detection module circuit;
the voltage current source module circuit is used for detecting a VI source of the resource board;
the DIO module circuit is used for realizing DIO resource detection of the resource board;
the QTMU module circuit is used for realizing QTMU resource detection of the resource board;
the ACSM module circuit is used for detecting ACM and ACS resources of the resource board;
the POWER module circuit is used for providing detection POWER supply;
the CBIT module circuit is used for realizing voltage detection of CBIT resources of the resource board;
and the input/output detection module circuit is connected with the voltage current source module circuit and is used for receiving the voltage current source detection data of the voltage current source module circuit, comparing the voltage current source detection data with a set reference value and outputting a comparison result.
2. A self-test system for a semiconductor tester as recited in claim 1, wherein: the input/output detection module circuit comprises relays F1-F7, light emitting diodes V1-V7, resistors RD 1-RD 7, resistors R1-R13 and an interface X1, wherein the interface X1 is a CBIT control bit European interface; the relay F3, the resistors R5, R4 and RD3 and the light emitting diode V3 are connected to form a forceH detection circuit; the sensor H detection circuit is formed by connecting the relay F2, the resistors R2, R3 and RD2 and the light emitting diode V2; the relay F6, the resistors R10, R11, RD5 and the light emitting diode V6 are connected to form a forceL detection circuit; the sensor L detection circuit is formed by connecting the relay F5, the resistors R8, R9 and RD6 and the light-emitting diode V5; the forceH detection circuit is used for detecting forceH loops in the voltage current source module circuit; the sensor H detection circuit is used for detecting a sensor H loop in the voltage current source module circuit; the forceL detection circuit is used for detecting forceL loops in the voltage-current source module circuit; the sensor L detection circuit is used for detecting a sensor L loop in the voltage current source module circuit.
3. A self-test system for a semiconductor tester as recited in claim 2, wherein: the voltage current source module circuit comprises relays F8-F11, resistors R14-R17 and interfaces X2-X4; the VI source comprises FOVI and FPVI resources, the interface X2 is a CBIT control bit European interface, the interface X3 is a FOVI 0-3 resource European interface, and the interface X4 is a FPVI 0-3 resource European interface; the contact ends of the relays F8-F11 are respectively and correspondingly connected to the contact ends of the relay F1; the relays F8, F9 and the resistors R14 and R15 are connected to realize FOVI resource detection; and the relays F10, F11 and the resistors R16 and R17 are connected to realize FPVI resource detection.
4. A self-test system for a semiconductor tester as recited in claim 1, wherein: the QTMU module circuit comprises interfaces X5 and X6 which are connected with each other, wherein the interface X5 is a QTMU resource European interface and is used for providing QTMU 0A-3B resources; the interface X6 is a CBIT control bit European interface and is used for providing diagnostic voltage for QTMU0A, QTMU 0B, QTMU 1A, QTMU 1B, QTMU 2A, QTMU 2B, QTMU 3A, QTMU3B resources respectively to realize QTMU resource detection.
5. A self-test system for a semiconductor tester as recited in claim 1, wherein: the ACSM module circuit comprises resistors R18-R25 and interfaces X7 and X8, wherein the interface X7 is an European interface of ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, ACM 3-resource; the interface X8 is a CBIT control bit European interface and is used for providing corresponding control bits to realize ACM0+, ACM1+, ACM2+, ACM3+, ACM0-, ACM1-, ACM2-, and ACM 3-resource detection.
6. A self-test system for a semiconductor tester as recited in claim 2, wherein: the POWER module circuit comprises relays F13-F16, resistors R26-R33 and an interface X9, wherein one end contacts of the relays F13-F16 are connected and then connected to a FHc contact end of the relay F1, and the interface X9 is a CBIT control bit European interface and is used for providing corresponding control bits so that the POWER module circuit is connected to the forceH detection circuit, thereby realizing the provision of detection voltage.
7. A self-test system for a semiconductor tester as recited in claim 1, wherein: the CBIT module circuit comprises a relay F17, resistors R34 and R35, a resistor-removing PRC, a triode Q1 and an interface X10, wherein the resistor-removing PRC is connected between the relay F17 and a CBIT board card on a resource board, and the interface X10 is a CBIT control bit European interface and is used for providing corresponding control bits to realize voltage detection of CBIT resources on the CBIT board card.
8. A self-test system for a semiconductor tester as recited in claim 1, wherein: the DIO module circuit comprises an interface X11, input/output ports DIO 0-DIO 15 are correspondingly connected to the interface X11, and the interface X11 is a CBIT control bit European interface and is used for providing corresponding control bits to realize voltage detection of the input/output ports DIO 0-DIO 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310066100.3A CN116148741A (en) | 2023-02-06 | 2023-02-06 | Self-checking system for semiconductor testing machine |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310066100.3A CN116148741A (en) | 2023-02-06 | 2023-02-06 | Self-checking system for semiconductor testing machine |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116859223A (en) * | 2023-09-05 | 2023-10-10 | 西安赛英特科技有限公司 | On-line self-checking method and circuit for VI source and VI source |
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2023
- 2023-02-06 CN CN202310066100.3A patent/CN116148741A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116859223A (en) * | 2023-09-05 | 2023-10-10 | 西安赛英特科技有限公司 | On-line self-checking method and circuit for VI source and VI source |
| CN116859223B (en) * | 2023-09-05 | 2023-12-08 | 西安赛英特科技有限公司 | On-line self-checking method and circuit for VI source and VI source |
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