CN116148625B - Method for testing semiconductor product - Google Patents
Method for testing semiconductor product Download PDFInfo
- Publication number
- CN116148625B CN116148625B CN202310427255.5A CN202310427255A CN116148625B CN 116148625 B CN116148625 B CN 116148625B CN 202310427255 A CN202310427255 A CN 202310427255A CN 116148625 B CN116148625 B CN 116148625B
- Authority
- CN
- China
- Prior art keywords
- signal
- test
- semiconductor product
- eye
- core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
- G01R31/2603—Apparatus or methods therefor for curve tracing of semiconductor characteristics, e.g. on oscilloscope
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The present disclosure provides a testing method of a semiconductor product for testing a core package structure of the semiconductor product, the testing method of the semiconductor product comprising: transmitting a test signal to at least one signal path in the semiconductor product, each signal path connecting a plurality of die; receiving a test result fed back by the semiconductor product based on the test signal; and determining the core packaging structure of the semiconductor product according to a test result, wherein the test signal is a data pattern containing inter-code crosstalk, and the test result comprises the eye height and the eye width of a test eye pattern. In the method, the test signal containing inter-code crosstalk is sent to the signal channel of the semiconductor product, the test result of the semiconductor product based on the feedback of the test signal is received, the core particle packaging structure of the semiconductor product can be obtained through analyzing the eye height and the eye width of the test result, the semiconductor product is not required to be disassembled, the cost is saved, and the test method is simple and rapid and speeds up the research and development progress.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for testing a semiconductor product.
Background
In the field of semiconductor technology, the interior of a semiconductor product is typically formed by stacking a plurality of Die/dice (Die), and the Die package structure of different semiconductor products may be different, such as different stacking modes of Die in the semiconductor product. The method has the advantages that the packaging structure of a packaged semiconductor product is obtained, a certain reference value is realized for the packaging design of the semiconductor product, and development progress is facilitated.
Disclosure of Invention
The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.
According to an embodiment of the present disclosure, there is provided a testing method of a semiconductor product for testing a core package structure of the semiconductor product, the testing method of the semiconductor product including:
transmitting a test signal to at least one signal path in the semiconductor product, each signal path connecting a plurality of die;
receiving a test result fed back by the semiconductor product based on the test signal;
determining a core packaging structure of the semiconductor product according to the test result;
the test signal is a data pattern containing inter-code crosstalk, and the test result comprises the eye height and the eye width of a test eye pattern.
In some embodiments, a plurality of said core particles connected to the same said signal channel form a core particle set;
determining the core particle packaging structure of the semiconductor product according to the test result, wherein the method comprises the following steps:
and determining the stacking mode of the plurality of core particle groups according to the advantages and disadvantages of the test results of the plurality of signal channels.
In some embodiments, determining a stacking manner of the plurality of core particle groups according to the merits of the test results of the plurality of signal channels includes:
if the difference value of the test results of any two signal channels in the plurality of signal channels is in a first preset range, a plurality of core particle groups are determined to be distributed along the horizontal direction, and a plurality of core particles in each core particle group are stacked.
If the difference value of the test results of any two signal channels in the plurality of signal channels is not in the first preset range, a plurality of core particles in the plurality of core particle groups are determined to be stacked together, and the plurality of core particles in different core particle groups are alternately arranged along the stacking direction.
In some embodiments, determining a die package structure of the semiconductor product based on the test results comprises:
and determining the packaging structures of a plurality of core particles connected with the same signal channel according to the test results of signals with different bytes in the same signal channel.
In some embodiments, determining the package structure of the plurality of the core grains according to the test results of the signals of different bytes in the same signal channel includes:
and the core grain corresponding to the byte signal with strong signal strength of the test result is positioned below the core grain corresponding to the byte signal with weak signal strength of the test result.
In some embodiments, determining a die package structure of the semiconductor product based on the test results comprises:
and determining the topology type of the signal line of the semiconductor product according to the test results of different channel areas in the same signal channel.
In some embodiments, determining the topology type of the signal line of the semiconductor product according to the test results of different channel regions in the same signal channel includes:
if the difference value of the test results of any two channel areas in the plurality of channel areas is not in a second preset range, determining that the signal line is in a tree topology;
and if the difference value of the test results of any two channel areas in the plurality of channel areas is within the second preset range, determining that the signal line is in a serial topology.
In some embodiments, the test results are presented by an eye-folding function of an oscilloscope.
In some embodiments, the test results include an average of eye widths and an average of eye heights of test eye patterns of the plurality of test signals.
In some embodiments, determining a die package structure of the semiconductor product based on the test results comprises:
determining the advantages and disadvantages of a plurality of test results according to the difference value of the eye widths and the difference value of the eye heights of any two test eye patterns in the plurality of test eye patterns;
and determining a core particle packaging structure of the semiconductor product according to the advantages and disadvantages of the plurality of test results, wherein the core particle packaging structure and the advantages and disadvantages of the test results have a corresponding relationship.
In the testing method of the semiconductor product, the testing signal containing inter-code crosstalk is sent to the signal channel of the semiconductor product, the testing result of the semiconductor product based on the feedback of the testing signal is received, the core particle packaging structure of the semiconductor product can be obtained through analyzing the eye height and the eye width of the testing result, the semiconductor product is not required to be disassembled, the cost is saved, and the testing method is simple and rapid and speeds up the research and development progress.
Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart illustrating a method of testing a semiconductor product according to an exemplary embodiment.
Fig. 2 is a schematic diagram illustrating a test apparatus for semiconductor products according to an exemplary embodiment.
Fig. 3 is a flow chart illustrating a method of testing a semiconductor product according to an exemplary embodiment.
Fig. 4 is a schematic diagram of a semiconductor product obtained according to the test method shown in fig. 3.
Fig. 5 is a schematic diagram of a semiconductor product obtained according to the test method shown in fig. 3.
Fig. 6 is a schematic diagram of a semiconductor product obtained according to the test method shown in fig. 3.
Fig. 7 is a flowchart illustrating a method of testing a semiconductor product according to an exemplary embodiment.
Fig. 8 is a schematic diagram of a semiconductor product obtained according to the test method shown in fig. 7.
Fig. 9 is a schematic diagram of a semiconductor product obtained according to the test method shown in fig. 7.
Fig. 10 illustrates a flowchart of a method of testing a semiconductor product, according to an exemplary embodiment.
Fig. 11 is a schematic view of a semiconductor product obtained according to the test method shown in fig. 10.
Fig. 12 is a schematic view of a semiconductor product obtained according to the test method shown in fig. 10.
Fig. 13 is a schematic view of a semiconductor product obtained according to the test method shown in fig. 10.
Fig. 14 is a pin schematic diagram of a signal path shown according to an example embodiment.
Fig. 15 is a block diagram illustrating a test apparatus for semiconductor products according to an exemplary embodiment.
Fig. 16 is a block diagram illustrating a test apparatus for semiconductor products according to an exemplary embodiment.
Reference numerals:
100. a semiconductor product;
10. a substrate; 11. a signal path; 11a, a first signal path; 11b, a second signal path;
20. a core particle group; 20a, a first set of core particles; 20b, a second set of core particles;
211. core particles; 211a, first core particles; 211b, second core particles;
30. a signal line; 30a, a first data line; 30b, a second data line;
31. a first signal line; 32. a second signal line; 33. a third signal line; 34. a fourth signal line;
40. a channel region; 41. a first channel region; 41', a first channel region; 42. a second channel region; 42', a second channel region;
151. a transmitting module; 152. a receiving module; 153. a determining module;
160. a testing device; 161. a processor; 162. a memory.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.
In the field of semiconductor technology, the interior of a semiconductor product is typically formed by stacking a plurality of Die/dice (Die), and the Die package structure of different semiconductor products may be different, such as different stacking modes of Die in the semiconductor product. The package structure of a plurality of core grains in a semiconductor product is known, and the package structure has a certain reference value for the package design of the semiconductor product, and is beneficial to promoting the development progress.
However, after the semiconductor product is packaged, the stacking manner of the internal core particles is not directly known.
In the related art, it is desired to know the internal package structure of the packaged semiconductor product, and only the semiconductor product can be cut and disassembled, and the 3D X-ray test is used for observation, so that manpower and material resources are consumed, and the semiconductor product cannot be used after being cut, thereby increasing the research and development cost. Also, the stacking order of the core particles could not be observed by means of cutting and 3D X-ray testing.
In order to solve the above-mentioned problems, the present disclosure provides a method for testing a semiconductor product, the method for testing a core package structure of the semiconductor product, the method for testing the semiconductor product comprising: transmitting a test signal to at least one signal path in the semiconductor product, each signal path connecting a plurality of die; receiving a test result fed back by the semiconductor product based on the test signal; and determining the core packaging structure of the semiconductor product according to a test result, wherein the test signal is a data pattern containing inter-code crosstalk, and the test result comprises the eye height and the eye width of a test eye pattern. In the method, the test signal containing inter-code crosstalk is sent to the signal channel of the semiconductor product, the test result of the semiconductor product based on the feedback of the test signal is received, the core particle packaging structure of the semiconductor product can be obtained through analyzing the eye height and the eye width of the test result, the semiconductor product is not required to be disassembled, the cost is saved, and the test method is simple and rapid and speeds up the research and development progress.
In an exemplary embodiment of the present disclosure, as shown in fig. 1, the embodiment of the present disclosure provides a method for testing a semiconductor product, which may be used to test the semiconductor product to obtain a core package structure inside the semiconductor product. In the present disclosure, a semiconductor product is taken as an example of a low power memory (Low Power Double Data Rate SDRAM, abbreviated as LPDDR), specifically, for example, a fourth generation low power dual rate memory (LPDDR 4/4X).
Referring to fig. 1, a method of testing a semiconductor product includes the steps of:
step S101, transmitting a test signal to at least one signal channel of the semiconductor product, wherein each signal channel is connected to a plurality of core particles.
Referring to fig. 4 and 8, the semiconductor product 100 includes a Substrate 10 (Substrate) and a plurality of core particles 211 (Die) disposed on the Substrate 10, and an adhesive layer (not shown in the drawings) is disposed between two adjacent core particles 211 stacked and between the Substrate 10 and the core particles 211 located on the Substrate 10. The substrate 10 serves as a package carrier for the semiconductor product 100, and the substrate 10 provides electrical connection, protection, support, heat dissipation, etc. for the core 211, and the semiconductor product has different signal channels 11 (e.g., a first signal channel 11a and a second signal channel 11 b).
For example, referring to fig. 2 and 4, a memory controller may be connected to at least one signal path 11 in the semiconductor product 100, and the memory controller may transmit a test signal to the semiconductor product 100 through a data bus, and the test signal may be transmitted to the core particle 211 inside the semiconductor product 100 through the signal path 11. Each signal path 11 connects two core particles 211, for example, a first signal path 11a connects two stacked core particles 211 located on the left side in fig. 4, and a second signal path 11b connects two stacked core particles 211 located on the right side in fig. 4.
Step S102, receiving a test result fed back by the semiconductor product based on the test signal.
In this step, referring to fig. 2 and 4, after the core particle 211 receives the test signal, it can generate a feedback signal based on the test signal, so as to generate a test result by receiving the feedback signal using a specific instrument (such as an oscilloscope) in response to a read/write command of the memory controller. With continued reference to fig. 2, an oscilloscope may be connected to the semiconductor product 100, and the oscilloscope may accumulate and superimpose the results of displaying the bits of the collected feedback signal in an afterglow manner, and generate a test eye pattern after superposition.
The test result may include an Eye Width (Eye Width) and an Eye Height (Eye Height) of the test Eye, and by testing the Eye Height and the Eye Width of the test Eye, the variation of inter-code crosstalk and noise in the feedback signal may be known, for example, the larger the Eye Height of the test Eye, the smaller the inter-code crosstalk. In some optional embodiments, the test result may further include any one or more of a cross-over ratio and a quality factor of the test eye pattern, which is not repeated in the present disclosure.
In the test process, a write-in instruction containing inter-code crosstalk can be selected as a test signal for testing, and compared with the test using a simple code pattern, the test eye pattern can reflect the authenticity of a feedback signal more, so that the accuracy and the reliability of the test are improved. In one example, for example, '00101011' including inter-symbol interference and having a complex pattern may be selected as the test signal, '00101011', that is, 0x2B.
Step S103, determining the core particle packaging structure of the semiconductor product according to the test result.
It should be noted that, referring to fig. 4, if the package structure of the core of the semiconductor product 100 is different, inter-code crosstalk and noise existing between the cores 211 on different signal channels are also different, and the package mode of the semiconductor product 100 has a corresponding relationship with the generated inter-code crosstalk and noise. Therefore, the test result is analyzed to obtain the conditions of inter-code crosstalk and noise, and the core package structure can be obtained by back-pushing, so that the core package structure of the semiconductor product 100 can be obtained without disassembling the semiconductor product 100.
In an alternative embodiment, the correspondence of the die package structure to the test results may be obtained in the following manner. Referring to fig. 2, a semiconductor product 100 of a known package structure may be tested, a test result of the semiconductor product 100 based on feedback of a test signal may be received using an oscilloscope, and a table of correspondence between the test result and the die package structure may be recorded. After the corresponding relation between various test results and the core particle packaging structure is determined, in the process of testing the semiconductor product with unknown packaging structure to determine the packaging structure of the semiconductor product, the core particle packaging structure of the semiconductor product can be obtained only by finding the core particle packaging structure corresponding to the test results in the corresponding relation table.
In the embodiment of the disclosure, the test signal containing inter-code crosstalk is sent to the signal channel of the semiconductor product, the test result of the semiconductor product based on the feedback of the test signal is received, the core particle packaging structure in the semiconductor product can be obtained without disassembling the semiconductor product by analyzing the eye height and the eye width of the test result, the cost is saved, and the test method is simple and quick, and the research and development progress is accelerated.
In one exemplary embodiment, as shown in fig. 3, an embodiment of the present disclosure provides a method for testing a semiconductor product to determine a die package structure of the semiconductor product from test results of a plurality of signal channels. The method for testing a semiconductor product may include the steps of:
step S201, sending a test signal to a plurality of signal channels in the semiconductor product, wherein each signal channel is connected to a plurality of core particles.
The implementation principle of this step is the same as that of step S101 in the foregoing embodiment, and will not be described here again.
Step S202, receiving a test result fed back by the semiconductor product based on the test signal.
The implementation principle of this step is the same as that of step S102 in the foregoing embodiment, and will not be described here again.
Step S203, determining a stacking mode of the plurality of core particle groups according to the advantages and disadvantages of the test results of the plurality of signal channels.
In this step, referring to fig. 3 to 5, and taking the semiconductor product 100 as LPDDR4 as an example, in conjunction with fig. 14, there are two signal channels 11 in LPDDR4, where the two signal channels 11 are a first signal Channel 11a (Channel a, abbreviated as CHA) and a second signal Channel 11B (Channel B, abbreviated as CHB), and each signal Channel 11 has an independent Data signal (Data-Quality, abbreviated as DQ), a Chip Select signal (CS), a Clock Enable signal (Clock Enable, abbreviated as CKE), and the like, that is, the different signal channels 11 are independent of each other. Each signal path 11 is connected to a plurality of core particles 211 at the same time, and a plurality of core particles 211 connected to the same signal path 11 can form one core particle group 20.
Wherein, referring to fig. 14, each signal path 11 (referring to fig. 4) of the lpddr4 includes 16 data signal pins of DQ0, DQ1, DQ2 … DQ13, DQ14, DQ15, wherein the first signal path 11a includes 16 data signal pins of dq0_ A, DQ1_a … dq15_a, and the second signal path 11B includes 16 data signal pins of dq0_ B, DQ1_b … dq15_b. In the test process, an oscilloscope may be used to test 16 data signals in total of dq0_a-dq15_a in the first signal channel 11a to obtain 16 test eye patterns, average the eye heights of the 16 test eye patterns, and average the eye widths, where the calculated average eye height and average eye width are used as the test result of the first signal channel 11a (the average eye height is used as the eye height of the test eye pattern, and the average eye width is used as the eye width of the test eye pattern). Similarly, the test result of the second signal channel 11b may be obtained in the foregoing manner, which is not described herein.
After the test results (the average value of the eye widths and the average value of the eye heights of the test eye patterns) of the two signal channels are obtained, the eye heights and the eye widths of the two test eye patterns can be compared, and the advantages and disadvantages of the test results of the two signal channels are determined through the difference value of the average value of the eye widths and the difference value of the average value of the eye heights of the two test eye patterns, so that the stacking mode of the two core particle groups is determined according to the advantages and disadvantages of the test results.
After step S203, the semiconductor product testing method includes the following steps:
step S204, if the difference value of the test results of any two signal channels in the plurality of signal channels is within a first preset range, it is determined that the plurality of core particle groups are arranged along the horizontal direction, and the plurality of core particles in each core particle group are stacked.
Referring to fig. 4, there is shown a stacking manner of two core particle groups 20, a first core particle group 20a is connected to a first signal path 11a, a second core particle group 20b is connected to a second signal path 11b, the first core particle group 20a and the second core particle group 20b are arranged in a horizontal direction (x direction shown in fig. 4), and a plurality of core particles 211 within each core particle group 20 are stacked.
It will be appreciated that in the stacked manner shown in fig. 4, the length of the signal line 30 connecting the first signal channels 11a of the first core particle group 20a is the same as the length of the signal line connecting the second signal channels 11b of the second core particle group 20b, so that the signal quality of the first signal channels 11a and the second signal channels 11b is the same, i.e., the eye widths and the eye heights of the test eye patterns of the two signal channels 11 are the same.
Accordingly, when the difference in eye height of the test eye pattern of the two core particle groups 20 and the difference in eye width of the test eye pattern of the two core particle groups 20 are within the first preset range, it can be determined that the two core particle groups 20 are stacked on the substrate 10 in the manner shown in fig. 4. The first preset range may be known by those skilled in the art through experiments, for example, the eye height difference between the two test eyes is 400mv, and the eye width difference is 230ps. And moreover, the first preset range can be adaptively adjusted according to the test precision requirement, and the smaller the first preset range is, the higher the test precision is.
Step S205, if the difference value of the test results of any two signal channels in the plurality of signal channels is not within the first preset range, determining that the plurality of core particles in the plurality of core particle groups are stacked together, and alternately arranging the plurality of core particles in different core particle groups along the stacking direction.
Referring to FIG. 5, another manner of stacking two sets of core particles 20 is shown. The two core particle groups 20 include a first core particle group 20a and a second core particle group 20b, all core particles 211 in the two core particle groups 20 are stacked together, that is, all core particles 211 are stacked in order, and the plurality of core particles 211 in the same core particle group 20 are not disposed adjacently, that is, the plurality of core particles 211 of the two core particle groups 20 are alternately arranged in the stacking direction (z direction shown in fig. 5) of the core particle groups 20.
It will be understood that in the stacking manner shown in fig. 5, the lengths of the signal lines 30 connecting the two signal channels 11 of the two core particle groups 20 are different, so that the signal quality of the two signal channels 11 is different, resulting in a large difference between the eye widths and the eye heights of the test eye patterns of the two signal channels 11 measured by the oscilloscope, that is, the difference between the eye widths and the eye heights of the test eye patterns of the two signal channels 11 is not within the first preset range.
This step is illustrated by way of example in the stacked configuration shown in fig. 5, which is not intended to limit the aspects of the present disclosure. The plurality of core particle groups may also be stacked as shown in fig. 6, as described in more detail below.
After step S205, that is, after determining that the two core particle groups are stacked in the manner shown in fig. 5 or 6, the method for testing a semiconductor product may further include the steps of:
step S206, determining the stacking sequence of the plurality of core particles in the plurality of core particle groups according to the advantages and disadvantages of the test results of the plurality of signal channels.
Referring to fig. 5 and 6, it can be determined that when all the core particles 211 in the first core particle group 20a and the second core particle group 20b are stacked together, the routing distance between the signal channels 11 connecting the two core particle groups 20 is different, so that there is a difference in signal quality of the two core particle groups 20. Wherein, the shorter the routing distance is, the better the signal quality is.
In one example, referring to fig. 5, the core connected to the first signal path 11a is located below the core connected to the second signal path 11b as a whole, so that the length of the signal line 30 of the first signal path 11a connecting the two cores 211 of the first core group 20a is shorter, so that the signal quality of the first core group 20a is better.
In another example, referring to fig. 6, the core connected to the second signal path 11b is below the core connected to the first signal path 11a as a whole, so that the length of the signal line 30 of the second signal path 11b connecting the two cores 211 of the second core group 20b is shorter, so that the signal quality of the second core group 20b is better.
In one exemplary embodiment, as shown in fig. 7, the disclosed embodiments provide a method for testing a semiconductor product to determine a die package structure from test results of different byte signals in the same signal path. The method for testing a semiconductor product may include the steps of:
step S301, a test signal is sent to a signal channel of the semiconductor product, where the signal channel is connected to a plurality of core particles.
This step is the same as the implementation of step S101 in the foregoing embodiment, and will not be described here again.
Step S302, receiving a test result fed back by the semiconductor product based on the test signal.
The implementation manner of this step is the same as that of step S102 in the foregoing embodiment, and will not be repeated here.
Step S303, determining the package structure of a plurality of core particles according to the test results of different byte signals in the same signal channel.
In this step, referring to fig. 8, 9 and 14, the semiconductor product 100 is exemplified as LPDDR4, and the first signal path 11a (CHA) of LPDDR4 is selected to have 16 bits of data, so that the first signal path 11a includes 16 data signal pins in total of dq0_ A, DQ1 _1_ A, DQ2_a … dq13_ A, DQ14_a and dq15_a.
Referring to fig. 8, 9 and 14, the dq0_a-dq7_a in the first signal path 11a forms a set of byte signals, also referred to as byte0, for transmitting the low-order signal "0" to the first core particle 211 a. The dq8_a-dq15_a in the first signal path 11a forms another set of byte signals, also referred to as byte1, for transmitting the high signal "1" to the second core 211 b. The test result of the byte0 byte signal can be obtained by averaging the eye heights of the test eye diagrams of the dq0_a-dq7_a total 8 data signals and averaging the eye widths, and the test result of the byte1 byte signal can be obtained by averaging the eye heights of the test eye diagrams of the dq8_a-dq15_a total 8 data signals and averaging the eye widths.
Referring to fig. 8 and 9, the first and second core grains 211a and 211b are connected to the first signal path 11a, the first signal path 11a connected to the first core grain 211a has the first data line 30a, and the first signal path 11a connected to the second core grain 211b has the second data line 30b. The different stacking arrangement order of the first core particle 211a and the second core particle 211b affects the length of the signal line 30 of the first signal path 11a, resulting in a difference in signal quality of the two core particles 211. Wherein the shorter the length of the signal line 30, the better the signal quality. Therefore, which core particle is located above and which core particle is located below can be determined according to the quality of the signal line 30 in the test result.
In one embodiment, referring to fig. 8, the first core particle 211a is directly connected to the substrate 10, and the first data line 30a connected to the first core particle 211a is shorter than the second data line 30b connected to the second core particle 211 b. Since the shorter the signal line is, the better the signal quality is, when the signal quality of the first data line 30a is detected to be better than that of the second data line 30b, it is determined that the first core particle 211a is stacked under the second core particle 211 b.
In another embodiment, referring to fig. 9, the second core particle 211b is directly connected to the substrate 10, so that the second data line 30b connected to the second core particle 211b is shorter than the first data line 30a connected to the first core particle 211 a. Therefore, when it is detected that the signal quality of the second data line 30b is better than that of the first data line 30a, it is determined that the second core particle 211b is stacked under the first core particle 211 a.
The above-described method may be used to determine the stacking order of the core particles 211 connected to the second signal path 11b, which will not be described in detail herein.
In one exemplary embodiment, as shown in fig. 10, the disclosed embodiments provide a method for testing a semiconductor product to determine a die package structure from test results of different channel regions in the same signal channel. The method for testing a semiconductor product may include the steps of:
step S401, a test signal is sent to a signal channel of the semiconductor product, where the signal channel is connected to a plurality of core particles.
This step is the same as the implementation of step S101 in the foregoing embodiment, and will not be described here again.
Step S402, receiving a test result fed back by the semiconductor product based on the test signal.
The implementation manner of this step is the same as that of step S102 in the foregoing embodiment, and will not be repeated here.
Step S403, determining the topology type of the signal line of the semiconductor product according to the test results of different channel regions (rank) in the same signal channel (channel).
Referring to fig. 11 to 13, and in combination with fig. 2, a plurality of core particles connected to the same signal channel 11 form a plurality of channel regions 40 (rank), each channel region 40 being provided with a data signal line (DQ) and a Chip Select signal line (CS) for short. The chip select signal line is one of address buses (refer to fig. 2), and the plurality of chip select signal lines are connected with the plurality of channel areas 40 in a one-to-one correspondence manner, the memory controller can select the channel area 40 corresponding to the chip select signal line through the chip select signal line, and independently transmit data, address or command to the selected channel area 40, so that the selected channel area 40 can generate a feedback signal, and then an oscilloscope can be used to measure a test eye diagram of the selected channel area 40.
Referring to fig. 11 and 12 as an example, and referring to fig. 14, the first signal channel 11a includes two channel regions 40, the two channel regions 40 are a first channel region 41 (rank 0) and a second channel region 42 (rank 1), respectively, the signal line 30 includes a first signal line 31 and a second signal line 32, the first signal line 31 is correspondingly connected to the first channel region 41, the first signal line 31 includes dq0_a-dq15_a for 16 data signal lines and one chip selection signal line cs0_a, the second signal line 32 is correspondingly connected to the second channel region 42, and the second signal line 32 includes dq0_a-dq15_a for 16 data signal lines and one chip selection signal line cs1_a. Referring to fig. 11, taking the first signal channel 11a as an example, it may be determined that the memory controller may select the first channel region 41 of the first signal channel 11a through the chip select signal line cs0_a, and when the oscilloscope measures all the data signal pins (DQ [15:0] _a) in the first signal channel 11a, the test result is a test eye diagram of the core feedback signal in the first channel region 41. The memory controller can select the second channel region 42 of the first signal channel 11a through the chip selection signal line CS1_A, and when measuring all the data signal pins (DQ [15:0] _A) by using the oscilloscope, the test results are all test eye diagrams of the core particle feedback signals in the second channel region 42. Similarly, the memory controller may select different channel regions (first channel region 41 'and second channel region 42') of the second signal channel 11B through chip select signal lines cs0_b and cs1_b, and test the data signal pins DQ [15:0] _b, which are not repeated herein.
It should be noted that, referring to fig. 11 to 13, the eye heights of the test eye patterns of DQ0 through DQ15 in total 16 data signal lines in each channel region 40 may be averaged and the eye widths may be averaged to serve as the test results (the eye heights and the eye widths of the test eye patterns) of the channel regions 40, and by comparing the eye height average values of the test eye patterns of the first channel region 41 and the second channel region 42 and comparing the eye width average values, the signal quality of the two channel regions 40 may be determined, and thus the topology type of the signal lines between the two channel regions 40 and the signal channel 11 may be determined.
In one embodiment, referring to fig. 11 and 12, taking the first signal channel 11a as an example, the first signal line 31 is connected to the first channel region 41, the second signal line 32 is connected to the second channel region 42, and the first signal line 31 is arranged in parallel with the second signal line 32, and the topology type of the signal lines is tree topology. With continued reference to fig. 11 and 12, the second signal line 32 is a signal branch (stub) for the first signal line 31, so that the second signal line 32 will reflect on the first signal line 31, resulting in a reduced signal quality of the first signal line 31. Moreover, the signal reflection has a large influence on the signal quality of the first signal line 31, so that the difference between the eye widths and the eye heights of the test eye patterns of the first signal line 31 and the second signal line 32 exceed the second preset range. It should be noted that the value of the second preset range may vary according to the specifications of the semiconductor product, and when the semiconductor product is LPDDR4, the difference between the second preset range and the eye width is 6ps, and the difference between the eye heights is 3mv.
From the above, it can be determined that the first signal line 31 and the second signal line 32 are tree-shaped topology when the difference of the test results of the first channel region 41 and the second channel region 42 exceeds the second preset range.
In another embodiment, referring to fig. 11 and 13, taking the second signal channel 11b as an example, wherein the third signal line 33 is connected to the first channel region 41', the fourth signal line 34 is connected to the second channel region 42', the third signal line 33 is arranged in series with the fourth signal line 34, and the topology type of the signal lines is a series topology. With continued reference to fig. 11 and 13, the third signal line 33 is connected in series with the fourth signal line 34, and the fourth signal line 34 does not reflect on the third signal line 33, so that the difference in eye width and the difference in eye height of the test eye pattern of the first and second channel regions 41 and 42 fall within the second preset range.
From the above, it can be determined that the signal line is in a serial topology when the difference of the test results of the first channel region 41 'and the second channel region 42' is within the second preset range.
The embodiments of the present disclosure describe in detail how to test LPDDR4/4X to obtain a core package structure of LPDDR4/4X, which is not limited to the technical solution of the present disclosure, and it is understood that, for a core package structure of other semiconductor products (such as LPDDR 5), the method provided by the above embodiments may also be used for testing.
Exemplary embodiments of the present disclosure provide a test apparatus for a semiconductor product. Fig. 15 is a block diagram of a test apparatus for semiconductor products, the test apparatus comprising:
a transmitting module 151 configured to transmit a test signal to at least one signal channel in the semiconductor product, each signal channel being connected to a plurality of core particles;
a receiving module 152 configured to receive a test result of the semiconductor product based on the test signal feedback;
the determining module 153 is configured to determine the package structure of the core particle of the semiconductor product according to the test result.
The specific manner in which the various modules perform the operations of the test apparatus of this embodiment has been described in detail in connection with the embodiments of the method and will not be described in detail herein.
Fig. 16 is a block diagram of a semiconductor product testing apparatus, i.e., a computer device 160, according to an exemplary embodiment. The test device may be a test device of a semiconductor product in the above-described exemplary embodiments of the present disclosure, and for example, the computer device 160 may be provided as a terminal device. Referring to fig. 16, the computer device 160 includes a processor 161, and the number of processors may be set to one or more as needed. Computer device 160 also includes a memory 162 for storing instructions, such as application programs, executable by processor 161. The number of the memories can be set to one or more according to the requirement. Which may store one or more applications. The processor 801 is configured to execute instructions to perform the above-described methods.
It will be apparent to those skilled in the art that embodiments of the present disclosure may be provided as a method, apparatus (device), or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including, but not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
In one exemplary embodiment of the present disclosure, a non-transitory computer-readable storage medium is also provided, such as memory 162, including instructions executable by processor 161 of computer device 160 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
In exemplary embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided to enable a test apparatus of a semiconductor product to perform the test method of the semiconductor product provided by the exemplary embodiments of the present disclosure.
In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.
It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.
In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.
Claims (6)
1. A method of testing a semiconductor product, the method of testing a die package structure of a semiconductor product comprising:
transmitting a test signal to at least one signal path in the semiconductor product, each signal path connecting a plurality of die;
receiving a test result fed back by the semiconductor product based on the test signal;
determining a core packaging structure of the semiconductor product according to the test result;
the test signal is a data pattern containing inter-code crosstalk, and the test result comprises the eye height and the eye width of a test eye pattern; a plurality of said core particles connected to the same said signal path forming a core particle group;
determining the core particle packaging structure of the semiconductor product according to the test result, wherein the method comprises the following steps:
determining a stacking mode of a plurality of core particle groups according to the advantages and disadvantages of the test results of the signal channels;
if the difference value of the test results of any two signal channels in the plurality of signal channels is in a first preset range, determining that the plurality of core particle groups are arranged along the horizontal direction, and stacking the plurality of core particles in each core particle group;
if the difference value of the test results of any two signal channels in the plurality of signal channels is not in the first preset range, determining that a plurality of core particles in the plurality of core particle groups are stacked together, and alternately arranging the plurality of core particles in different core particle groups along the stacking direction.
2. The method of testing a semiconductor product according to claim 1, wherein determining a die package structure of the semiconductor product based on the test result comprises:
determining the packaging structures of a plurality of core particles connected with the same signal channel according to the test results of different byte signals in the same signal channel;
and the core grain corresponding to the byte signal with strong signal strength of the test result is positioned below the core grain corresponding to the byte signal with weak signal strength of the test result.
3. The method of testing a semiconductor product according to claim 1, wherein determining a die package structure of the semiconductor product based on the test result comprises:
determining the topology type of the signal line of the semiconductor product according to the test results of different channel areas in the same signal channel;
if the difference value of the test results of any two channel areas in the plurality of channel areas is not in a second preset range, determining that the signal line is in a tree topology;
and if the difference value of the test results of any two channel areas in the plurality of channel areas is within the second preset range, determining that the signal line is in a serial topology.
4. A method of testing a semiconductor product according to any one of claims 1-3, wherein the test results are presented by an eye-stack function of an oscilloscope.
5. A method of testing a semiconductor product according to any one of claims 1-3, wherein the test result comprises an average of eye widths and an average of eye heights of test eye patterns of the plurality of test signals.
6. The method of testing a semiconductor product according to claim 5, wherein determining a die package structure of the semiconductor product based on the test result comprises:
determining the advantages and disadvantages of a plurality of test results according to the difference value of the eye widths and the difference value of the eye heights of any two test eye patterns in the plurality of test eye patterns;
and determining a core particle packaging structure of the semiconductor product according to the advantages and disadvantages of the plurality of test results, wherein the core particle packaging structure and the advantages and disadvantages of the test results have a corresponding relationship.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310427255.5A CN116148625B (en) | 2023-04-20 | 2023-04-20 | Method for testing semiconductor product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310427255.5A CN116148625B (en) | 2023-04-20 | 2023-04-20 | Method for testing semiconductor product |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116148625A CN116148625A (en) | 2023-05-23 |
| CN116148625B true CN116148625B (en) | 2023-09-19 |
Family
ID=86362218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310427255.5A Active CN116148625B (en) | 2023-04-20 | 2023-04-20 | Method for testing semiconductor product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116148625B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100816758B1 (en) * | 2006-11-07 | 2008-03-25 | 삼성전자주식회사 | Test apparatus testing multi-chip package improved signal integrity as restraining reflecting wave |
| CN102083277A (en) * | 2009-12-01 | 2011-06-01 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board and wiring method thereof |
| JP2014011470A (en) * | 2012-06-27 | 2014-01-20 | Jvc Kenwood Corp | Depth information generating device, depth information generating method, depth information generating program, and pseudo three-dimensional image generating device |
| WO2017111834A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices |
| CN107493131A (en) * | 2017-07-17 | 2017-12-19 | 武汉电信器件有限公司 | The chip-scale eye diagram testing method and test device of a kind of semiconductor laser chip |
| CN108535631A (en) * | 2018-04-02 | 2018-09-14 | 郑州云海信息技术有限公司 | A kind of test method and system of test chip internal signal eye pattern |
| CN108701684A (en) * | 2015-12-26 | 2018-10-23 | 英特尔公司 | The ground plane for being guided through the horizontal data signal transmission line of packaging is isolated vertically, ground path is coaxially isolated and impedance-tumed |
| CN109765254A (en) * | 2017-11-10 | 2019-05-17 | 株式会社日立高新技术 | Pattern measurement device and measurement method |
| CN109766232A (en) * | 2019-01-15 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of PCIe pressure eye figure detection calibration method |
| CN217605914U (en) * | 2022-04-11 | 2022-10-18 | 成都英思嘉半导体技术有限公司 | Circuit and test assembly for chip impedance, S parameter and eye pattern test |
| CN115562916A (en) * | 2022-09-29 | 2023-01-03 | 浪潮(山东)计算机科技有限公司 | Method, device and medium for evaluating signal quality |
| CN115987862A (en) * | 2022-12-30 | 2023-04-18 | 浪潮(山东)计算机科技有限公司 | SATA signal quality testing method and device and storage medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7075175B2 (en) * | 2004-04-22 | 2006-07-11 | Qualcomm Incorporated | Systems and methods for testing packaged dies |
| DE102004036520B4 (en) * | 2004-07-28 | 2007-12-13 | Infineon Technologies Ag | Component arrangement with an evaluation circuit for detecting wear of connection connections and method for detecting wear of connection connections |
| US7957462B2 (en) * | 2007-12-21 | 2011-06-07 | Anritsu Company | Integrated compact eye pattern analyzer for next generation networks |
| US11456283B2 (en) * | 2019-12-23 | 2022-09-27 | SK Hynix Inc. | Stacked semiconductor device and test method thereof |
| KR20210107411A (en) * | 2020-02-24 | 2021-09-01 | 삼성전자주식회사 | Semiconductor package test method, semiconductor package test device and semiconductor package |
-
2023
- 2023-04-20 CN CN202310427255.5A patent/CN116148625B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100816758B1 (en) * | 2006-11-07 | 2008-03-25 | 삼성전자주식회사 | Test apparatus testing multi-chip package improved signal integrity as restraining reflecting wave |
| CN102083277A (en) * | 2009-12-01 | 2011-06-01 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board and wiring method thereof |
| JP2014011470A (en) * | 2012-06-27 | 2014-01-20 | Jvc Kenwood Corp | Depth information generating device, depth information generating method, depth information generating program, and pseudo three-dimensional image generating device |
| WO2017111834A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices |
| CN108701684A (en) * | 2015-12-26 | 2018-10-23 | 英特尔公司 | The ground plane for being guided through the horizontal data signal transmission line of packaging is isolated vertically, ground path is coaxially isolated and impedance-tumed |
| CN107493131A (en) * | 2017-07-17 | 2017-12-19 | 武汉电信器件有限公司 | The chip-scale eye diagram testing method and test device of a kind of semiconductor laser chip |
| CN109765254A (en) * | 2017-11-10 | 2019-05-17 | 株式会社日立高新技术 | Pattern measurement device and measurement method |
| CN108535631A (en) * | 2018-04-02 | 2018-09-14 | 郑州云海信息技术有限公司 | A kind of test method and system of test chip internal signal eye pattern |
| CN109766232A (en) * | 2019-01-15 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of PCIe pressure eye figure detection calibration method |
| CN217605914U (en) * | 2022-04-11 | 2022-10-18 | 成都英思嘉半导体技术有限公司 | Circuit and test assembly for chip impedance, S parameter and eye pattern test |
| CN115562916A (en) * | 2022-09-29 | 2023-01-03 | 浪潮(山东)计算机科技有限公司 | Method, device and medium for evaluating signal quality |
| CN115987862A (en) * | 2022-12-30 | 2023-04-18 | 浪潮(山东)计算机科技有限公司 | SATA signal quality testing method and device and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| High-Frequency Electrical Characterization of a New Coaxial Silicone Rubber Socket for High-Bandwidth and High-Density Package Test;Junyong Park等;《IEEE Transactions on Components, Packaging and Manufacturing Technology》;第8卷(第12期);全文 * |
| 基于CT成像和数字体图像相关法的岩石内部变形场量测方法的研究进展;毛灵涛等;《科学通报》;第68卷(第4期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116148625A (en) | 2023-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108511008B (en) | Stacked semiconductor device | |
| US20120138927A1 (en) | Semiconductor device having stacked structure including through-silicon-vias and method of testing the same | |
| KR102092745B1 (en) | Semiconductor appratus and testing method thereof | |
| US9030245B2 (en) | Semiconductor device that can adjust propagation time of internal clock signal | |
| KR20110075347A (en) | Semiconductor memory apparatus including data compression test circuit | |
| US20120182042A1 (en) | Semiconductor apparatus, method for assigning chip ids therein, and method for setting chip ids thereof | |
| CN116148625B (en) | Method for testing semiconductor product | |
| JP6127184B1 (en) | High frequency memory test apparatus and test method | |
| CN103066066A (en) | Semiconductor apparatus | |
| KR101094945B1 (en) | Semiconductor memory apparatus and probr test method thereof | |
| CN103377961A (en) | Testing and manufacturing methods of three-dimensional stacking type random access memory and testing method of wafer | |
| US11929132B2 (en) | Testing method, testing system, and testing apparatus for semiconductor chip | |
| US9396765B2 (en) | Stacked semiconductor package | |
| US20210279129A1 (en) | Memory device and test operation thereof | |
| KR101088588B1 (en) | Test apparatus for multi chip package and test method thereof | |
| WO2024077825A1 (en) | Data storage method and apparatus based on ethash algorithm, device, and storage medium | |
| EP4084052A1 (en) | Wafer to wafer structure and test method therefor, and high bandwidth memory and manufacturing method therefor | |
| KR100630701B1 (en) | Test board of semiconductor tester having modified I/O printed circuit pattern and method for testing thereof | |
| CN103116123A (en) | Integrated circuit and test method thereof | |
| JP4939428B2 (en) | Test equipment | |
| KR101885465B1 (en) | SSD BIST apparatus | |
| US20080208537A1 (en) | Circuit measuring operating speed and related semiconductor memory device | |
| EP3923285B1 (en) | Integrated circuit structure and memory | |
| CN108447524A (en) | A method of for detecting external memory interface failure | |
| JP2012002509A (en) | Test board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |