CN103116123A - Integrated circuit and test method thereof - Google Patents

Integrated circuit and test method thereof Download PDF

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Publication number
CN103116123A
CN103116123A CN2011103658033A CN201110365803A CN103116123A CN 103116123 A CN103116123 A CN 103116123A CN 2011103658033 A CN2011103658033 A CN 2011103658033A CN 201110365803 A CN201110365803 A CN 201110365803A CN 103116123 A CN103116123 A CN 103116123A
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path
switch unit
integrated circuit
information
testing cushion
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CN103116123B (en
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林树森
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Winbond Electronics Corp
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Winbond Electronics Corp
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Abstract

The invention discloses an integrated circuit which comprises a test pad unit, a storage unit array, a first switch unit, a boundary scanning unit and a second switch unit. The test pad unit transmits first test information, second test information or a test result under a test module. The storage unit array stores the first test information. Under the test module, the first switch unit transmits the first test information to the storage unit array according to a first enabled signal, or transmits data stored in the storage unit array to the test pad unit according to a read signal, wherein the data stored in the storage unit array serves as the test result. The boundary scanning unit converts the second test information into scanning information. Under the test module, the second switch unit transmits the scanning information to the test pad unit according to a second enabled signal.

Description

Integrated circuit and method of testing thereof
Technical field
The present invention relates to a kind of integrated circuit (Integrated Circuit), particularly relevant for a kind of integrated circuit that has memory function and test function can be provided.
Background technology
Along with the progress of semiconductor fabrication process, by packing (package) technology, just a storage chip and a control chip can be packaged together.Have many pins around the packaging body, use so that the storage chip of package interior and control chip can be linked up with an external device (ED).
For the storage chip of test package body inside whether normal, existing test mode is the pin by the packaging body outside, one test data is write to storage chip in the packaging body, and then read stored data of storage chip in the packaging body, and according to reading result, but judge storage chip regular event whether in the packaging body.Yet, pass through reading result, the wire that only can judge between the pin of storage chip in the packaging body and packaging body outside can normally transmit data, whether can normally transmit data as for the storage chip in the packaging body and the wire between control chip, but can't learn.
Summary of the invention
The invention provides a kind of integrated circuit, comprise a testing cushion unit, a memory cell array, one first switch unit, a border scanning element and one second switch unit.Under a test pattern, the testing cushion unit transmits one first detecting information, the second detecting information or a test result.Under a normal mode, the testing cushion unit transmits an access information.Memory cell array is in order to store first, second detecting information or access information.Under test pattern, the first switch unit memory cell array is given in the transmission of the first detecting information, or according to a read signal, the data that memory cell array is stored is sent to the testing cushion unit as test result according to one first enable signal.Boundary scan cell converts the second detecting information to one scan information.The second switch unit couples the first switch unit, and under test pattern, according to one second enable signal, transmits scanning information to the testing cushion unit.
The present invention provides a kind of method of testing in addition, by a testing cushion unit, tests an integrated circuit.Integrated circuit has a memory cell array and a border scanning element.Have many first paths and many read paths between testing cushion unit and memory cell array.Have many second paths between testing cushion unit and boundary scan cell.Method of testing of the present invention comprises: under a test pattern: conducting the first path, in order to write one first detecting information to memory cell array; The conducting read path is in order to the stored data of reading cells array; Write one second detecting information to boundary scan cell; Make boundary scan cell convert the second detecting information to one scan information; And conducting the second path, in order to scanning information is sent to the testing cushion unit.
For the features and advantages of the present invention can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, does not consist of limitation of the invention.In the accompanying drawings:
Fig. 1 is a possible embodiment of integrated circuit of the present invention;
Fig. 2 is another possibility embodiment of integrated circuit of the present invention;
Fig. 3 is that one of method of testing of the present invention may embodiment.
Drawing reference numeral:
100,200: integrated circuit; 110,210: the testing cushion unit;
120,220: memory cell array;
130,140,230,240,260: switch unit;
150,250: boundary scan cell; 270: processing unit;
S310～S360: step;
SDI, SDO, CA 0～CA n, DQ 0～DQ m: testing cushion;
S ENA, S ENB, S ENC: enable signal;
S ENR: read signal;
PA 1～PA n, PB 1～PB m, PC 1～PC m, PD 1～PD n, PE 1～PE m, PF 1～PF m: the path;
MA 1～MA n, MB 1～MB m, MC 1～MC m, MD 1～MD n, ME 1～ME m, MF 1～MF m, MG, MH: multiplexer;
SA 1～SA n, SB 1～SB m: scanning information;
BA 1～BA n, BB 1～BB m, BC 1～BC m, BD 1～BD n, BE 1～BE m, BF 1～BF m, BH; Impact damper.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing the embodiment of the invention is described in further details.At this, illustrative examples of the present invention and explanation thereof are used for explanation the present invention, but not as a limitation of the invention.
Fig. 1 is that one of integrated circuit of the present invention may embodiment.In the present embodiment, integrated circuit 100 has memory function, and test function can be provided, but makes an external testing board be judged whether regular event of integrated circuit 100.As shown in the figure, integrated circuit 100 comprises, a testing cushion unit 110, a memory cell array 120, switch unit 130,140 and one border scanning element (boundary scan cell) 150.
Testing cushion unit 110 comprises testing cushion SDI, CA 0～CA n, DQ 0～DQ m, as the communication bridge of integrated circuit 100 and an external device (ED) (such as a tester table).In a possibility embodiment, testing cushion SDI is in order to transmit serial data, testing cushion CA 0～CA nIn order to the transfer control signal, and testing cushion DQ 0～DQ mIn order to data signal.
Under a test pattern, integrated circuit 100 can pass through testing cushion unit 110, receives one first detecting information or one second detecting information that an external device (ED) provides, or by testing cushion unit 110, provides a test result to an external device (ED).In addition, under a normal mode, testing cushion unit 110 can transmit an access information, in order to access memory cell array 120, but is not to limit the present invention.In other embodiments, integrated circuit 100 is not by testing cushion unit 110, receives an access data.
The present invention does not limit the kind of first and second detecting information.For example, the first detecting information can be same or different from the second detecting information.In the present embodiment, the first detecting information is in order to carry out one first test action.By the first test action, but in order to judging the wire normal transmission whether between testing cushion unit 110 and the memory cell array 120, but but also test storage cell array 120 regular event whether.The second detecting information is in order to carry out one second test action.By the second test action, but in order to judge the wire normal transmission whether between testing cushion unit 110 and the boundary scan cell 150.
Because the wire between sectionalization test memory cell array 120 of the present invention and the boundary scan cell 150, so after above-mentioned two test actions are finished, but not only guarantee memory cell array 120 regular events, also can guarantee that the transmission action between memory cell array 120 and the boundary scan cell 150 is normal.
Therefore, when another integrated circuit (not shown) couples boundary scan cell 150, if this another integrated circuit is normally during access memory cell array 120, then problem of representation is to be another integrated circuit, rather than memory cell array 120 thereby, can significantly reduce debug (debug) time.
Memory cell array 120 is in order to storage data.The present invention does not limit the kind of memory cell array 120.In a possibility embodiment, memory cell array 120 is the DRAM memory cell array.In addition, the present invention does not limit the source of the stored data of memory cell array 120.In a possibility embodiment, memory cell array 120 can store from the data of testing cushion unit 110 (such as detecting information or access information).In other embodiments, when boundary scan cell 150 coupled another integrated circuit (such as a storage unit controller), then memory cell array 120 can store the data that another integrated circuit provides.
Under a test pattern, switch unit 130 is according to an enable signal S ENA, one first detecting information of in the future self-test single pad unit 110 sends memory cell array 120 to, or according to a read signal S ENR, as a test result, and be sent to testing cushion unit 110 in order to the data that memory cell array 120 is stored.
In the present embodiment, switch unit 130 is according to enable signal S ENA, the first path PA is provided 1～PA n, PB 1～PB m, in order to transmitting the first detecting information to memory cell array 120, or according to read signal S ENR, read path PC is provided 1～PC m, in order to transmit a test result to testing cushion unit 110.
The present invention does not limit the first path PA 1～PA n, PB 1～PB mWith read path PC 1～PC mStructure.In the present embodiment, switch unit 130 has multiplexer MA 1～MA nAnd MB 1～MB mMultiplexer MA 1～MA nAnd MB 1～MB mBy enable signal S ENAControl, in order to the first path PA to be provided 1～PA n, PB 1～PB mFor example, as enable signal S ENAConducting multiplexer MA 1～MA nAnd MB 1～MB mThe time, multiplexer MA 1～MA nAnd MB 1～MB mOne corresponding path just can be provided, and one first detecting information of in the future self-test single pad unit 110 sends memory cell array 120 to.
In addition, switch unit 130 has more multiplexer MC 1～MC mMultiplexer MC 1～MC mBy read signal S ENRControl, in order to read path PC to be provided 1～PC mAs read signal S ENRConducting multiplexer MC 1～MC mThe time, multiplexer MC 1～MC mOne corresponding path just can be provided,, and test result be sent at least one testing cushion of testing cushion unit 110 as a test result in order to the data that memory cell array 120 is stored.Therefore, a tester table just can be according to the accurate state in position on the testing cushion of testing cushion unit 110, but learns whether regular event of memory cell array 120.
One second detecting information of boundary scan cell 150 in the future self-test pad SDI converts one scan information SA to 1～SA n, SB 1～SB mAs shown in the figure, switch unit 140 has multiplexer MG.As enable signal S ENBDuring conducting multiplexer MG, boundary scan cell 150 just converts the second detecting information to scanning information SA 1～SA n, SB 1～SB mIn the present embodiment, the second detecting information is a serial data, and scanning information SA 1～SA n, SB 1～SB mIt is a parallel data.
Under test pattern, switch unit 140 is according to enable signal S ENB, transmit scanning information SA 1～SA n, SB 1～SB mGive testing cushion CA 0～CA n, DQ 0～DQ mThe present invention does not limit switch unit 140 and how to transmit scanning information to testing cushion.In the present embodiment, switch unit 140 is according to enable signal S ENB, the second path P D is provided 1～PD n, PE 1～PE m, PF 1～PF m, in order to transmit scanning information SA 1～SA n, SB 1～SB m
As shown in the figure, switch unit 140 has multiplexer MD 1～MD n, ME 1～ME m, MF 1～MF mAs enable signal S ENBConducting multiplexer MD 1～MD n, ME 1～ME m, MF 1～MF mThe time, multiplexer MD 1～MD n, ME 1～ME m, MF 1～MF mProvide separately a path, in order to received scanning information SA 1～SA n, SB 1～SB mBe sent to the testing cushion CA of testing cushion unit 110 0～CA n, DQ 0～DQ mTherefore, a tester table just can according to the accurate state in position on the testing cushion of testing cushion unit 110, learn whether the wire of 150 of testing cushion unit 110 and boundary scan cells can normally transmit data.
In the present embodiment, switch unit 130 and 140 is series between memory cell array 120 and the boundary scan cell 150, in order to the wire between sectionalization test memory cell array 120 and the boundary scan cell 150.In a possibility embodiment, when switch unit 130 provides the first path PA 1～PA n, PB 1～PB mOr provide read path PC 1～PC mThe time, switch unit 140 does not provide the second path P D 1～PD n, PE 1～PE m, PF 1～PF mSimilarly, provide the second path P D when switch unit 140 1～PD n, PE 1～PE m, PF 1～PF mThe time, switch unit 130 does not provide the first path PA 1～PA n, PB 1～PB mOr read path PC 1～PC m
Because switch unit 130 and 140 is not that corresponding path is provided simultaneously, therefore, one external testing board just can be tested respectively the path of 120 of testing cushion unit 110 and memory cell arrays, and the path of 150 of testing cushion unit 110 and boundary scan cells, in order to guarantee 150 of memory cell array 120 and boundary scan cells, can normally transmit data.
Under a normal mode, switch unit 130 provides corresponding path simultaneously with 140, and therefore, memory cell array 120 just can be carried out data transmission with another integrated circuit (may couple boundary scan cell 150).Because after leaving test pattern, can normally transmit to guarantee memory cell array 120 and boundary scan cell 150, thus when another integrated circuit can't access memory cell array 120, be expressed as another integrated circuit abnormal, thereby the reduction debug time.
In a possibility embodiment, switch unit 130 provides the first path PA simultaneously 1～PA n, PB 1～PB mAnd read path PC 1～PC mIn other words, multiplexer MA 1～MA n, MB 1～MB m, MC 1～MC mBe switched on simultaneously, in order to the first path PA to be provided 1～PA n, PB 1～PB mAnd read path PC 1～PC mIn another possibility embodiment, when switch unit 130 provides the first path PA 1～PA n, PB 1～PB mThe time, read path PC is not provided 1～PC mOn the contrary, do not provide the first path PA when switch unit 130 1～PA n, PB 1～PB mThe time, read path PC is provided 1～PC m
Fig. 2 is another possibility embodiment of integrated circuit of the present invention.Fig. 2 similar diagram 1, difference be, Fig. 2 is many impact damper BA 1～BA n, BB 1～BB m, BC 1～BC m, BD 1～BD n, BE 1～BE m, BF 1～BF m, BG, switches unit 260, a processing unit 270 and a testing cushion SDO, but is not to limit the present invention.In other embodiments, impact damper BA 1～BA n, BB 1～BB m, BC 1～BC m, BD 1～BD n, BE 1～BE m, BF 1～BF m, BG, switch unit 260 and processing unit 270 at least one be integrated among the integrated circuit 100.
As shown in Figure 2, the output terminal of each multiplexer couples an impact damper, in order to increasing the fan-out capability of multiplexer, but and inessential.In other embodiments, only there is the multiplexer of part need couple impact damper.
Processing unit 270 is with testing cushion DQ 0～DQ 15The first received detecting information is suitably distributed to the first path PB 1～PB m, or with read path PC 1～PC mOn data, suitably distribute to testing cushion DQ 0～DQ 15, thereby the quantity of reduction testing cushion.
The present invention does not limit processing unit 270 and how to carry out assign action.To distribute the first detecting information as example, in a possibility embodiment, processing unit 270 can be with testing cushion DQ 0～DQ 15Received detecting information is distributed to first the first path PB 1～PB 16, and then with testing cushion DQ 0～DQ 15Received detecting information is distributed to the first path PB 17～PB 32, then again with testing cushion DQ 0～DQ 15Received detecting information is distributed to the first path PB 33～PB 48, until all first paths all receive detecting information.In other embodiments, processing unit 270 can utilize other allocation scheme, with testing cushion DQ 0～DQ 15Received detecting information is distributed to the first path PB 1～PB m
Boundary scan cell 250 produces a string column information Sser according to one second detecting information on the testing cushion SDI.In the present embodiment, tandem information Sser is serial data with the second detecting information that reaches on the testing cushion SDI, and scanning information SA 1～SA n, SB 1～SB mIt is a parallel data.
Switch unit 260 is according to an enable signal S ENC, provide Third Road footpath PH, in order to tandem information Sser is sent to the testing cushion SDO of testing cushion unit 210.Therefore, an external device (ED) can according to the signal on the testing cushion SDO, learn whether boundary scan cell 250 is normal.
Because outside test machine can be passed through the testing cushion unit, each path and element in the sectionalization test integrated circuit 100,200, so when abnormal, can differentiate rapidly unusual place, and the test signal of the boundary scan cell in the integrated circuit 100,200 is not from memory cell array, so can reduce the complexity of test, and can contract and know the test duration, because not needing the access memory cell array.
Moreover, when integrated circuit 100,200 passes through test, if integrated circuit 100 or 200 is coupled another integrated circuit (such as the storage unit control circuit), then can be when access exception occurs, learn immediately it is another integrated circuit abnormal, thereby significantly reduce the debug time.
Fig. 3 is that one of method of testing of the present invention may embodiment.Method of testing of the present invention is tested an integrated circuit by a testing cushion unit.In the present embodiment, integrated circuit has a memory cell array and a border scanning element.Have many first paths and many read paths between testing cushion unit and memory cell array.Have many second paths between testing cushion unit and boundary scan cell.
At first, under a test pattern, the first path between continuity test single pad unit and memory cell array is in order to write one first detecting information to memory cell array (step S310).The present invention does not limit the conduction mode in the first path.In a possibility embodiment, the first path is provided by one first switch unit.The first switch unit provides the first path according to one first enable signal.
Under test pattern, the conducting read path is in order to the stored data (step S320) of reading cells array.By judging the result read, but just can learn whether regular event of memory cell array, and can learn whether the wire between testing cushion and the memory cell array can normally transmit data.The present invention does not limit the conduction mode of read path.In a possibility embodiment, read path is provided by this first switch unit.The first switch unit provides read path according to a read signal.
Under test pattern, write one second detecting information to boundary scan cell (step S330).The present invention does not limit the form of the second detecting information.In a possibility embodiment, the second detecting information is serial data.Then, make boundary scan cell convert the second detecting information to one scan information (step S340).The present invention does not limit the form of scanning information.In a possibility embodiment, scanning information is parallel data.
Under test pattern, conducting the second path is in order to be sent to scanning information testing cushion unit (step S350).By reading scan-data, but just can learn whether regular event of boundary scan cell, and can learn whether the wire between testing cushion and boundary scan cell can normally transmit data.
The present invention does not limit the conduction mode in the second path.In a possibility embodiment, the second path is provided by one second switch unit.The second switch unit provides the second path according to one second enable signal.In the present embodiment, when the first path was switched on, the second path was not switched on.On the contrary, when the second path was switched on, the first path was not switched on.
After through step S310～S350, can learn just whether integrated circuit is normal.If integrated circuit is normal, and be coupled in a time-out with another integrated circuit (such as the storage unit control circuit), under normal mode, first, second path of conducting and read path (step S360) are so that two integrated circuit can transmit data mutually.Unless define in addition, all belong to (comprising technology and science vocabulary) persond having ordinary knowledge in the technical field of the present invention's general understanding at these all vocabulary.In addition, unless clear expression, it is consistent that the definition of vocabulary in general dictionary should be interpreted as in the article with its correlative technology field meaning, and should not be construed as perfect condition or too formal voice.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.

Claims (15)

1. an integrated circuit is characterized in that, comprising:
One testing cushion unit under a test pattern, transmits one first detecting information, the second detecting information or a test result, under a normal mode, transmits an access information;
One memory cell array is in order to store described the first detecting information or described access information;
One first switch unit, under described test pattern, according to one first enable signal, send described the first detecting information to described memory cell array, or according to a read signal, the data that described memory cell array is stored are sent to described testing cushion unit as described test result;
One border scanning element converts described the second detecting information to one scan information; And
One second switch unit couples described the first switch unit, under described test pattern, according to one second enable signal, transmits described scanning information to described testing cushion unit.
2. integrated circuit as claimed in claim 1 is characterized in that, described first and second switch unit is series between described boundary scan cell and the described memory cell array.
3. integrated circuit as claimed in claim 1, it is characterized in that, described the first switch unit is according to described the first enable signal, many the first paths are provided, in order to send described the first detecting information to described memory cell array, and according to described read signal, many read paths are provided, in order to described test result, be sent to described testing cushion unit, described the second switch unit provides many second paths according to described the second enable signal, in order to transmit described scanning information to described testing cushion unit.
4. integrated circuit as claimed in claim 3, it is characterized in that, when described the first switch unit provides described the first path or described read path, described the second switch unit does not provide described the second path, when described the second switch unit provided described the second path, described the first switch unit did not provide described the first path or described read path.
5. integrated circuit as claimed in claim 3 is characterized in that, described the first switch unit provides described the first path and described read path simultaneously.
6. integrated circuit as claimed in claim 3 is characterized in that, when described the first switch unit provides described the first path, does not provide described read path, when described the first switch unit provides described read path, does not provide described the first path.
7. integrated circuit as claimed in claim 3 is characterized in that, described the first switch unit comprises:
Many the first multiplexers according to described the first enable signal, provide described the first path; And
Many the second multiplexers according to described read signal, provide described read path.
8. integrated circuit as claimed in claim 7 is characterized in that, described the first switch unit more comprises at least one impact damper, couples one in described the first multiplexer or the one in described the second multiplexer.
9. integrated circuit as claimed in claim 7 is characterized in that, more comprises: a processing unit, and in order to described the first detecting information is suitably distributed to described the first path or described data is suitably distributed to described testing cushion unit.
10. integrated circuit as claimed in claim 3 is characterized in that, under described normal mode, described the first switch unit provides described first and read path, and described the second switch unit provides described the second path.
11. integrated circuit as claimed in claim 1, it is characterized in that described boundary scan cell produces a string column information according to described the second detecting information, described tandem information and described the second detecting information are serial data, and described scanning information is a parallel data.
12. integrated circuit as claimed in claim 11 is characterized in that, more comprises:
One the 3rd switch unit according to one the 3rd enable signal, provides Third Road footpath, in order to described tandem information is sent to described testing cushion unit.
13. method of testing, it is characterized in that, by a testing cushion unit, test an integrated circuit, described integrated circuit has a memory cell array and a border scanning element, have many first paths and many read paths between described testing cushion unit and described memory cell array, have many second paths between described testing cushion unit and described boundary scan cell, described method of testing comprises:
Under a test pattern:
Described the first path of conducting is in order to write one first detecting information to described memory cell array;
The described read path of conducting is in order to read the stored data of described memory cell array;
Write one second detecting information to described boundary scan cell;
Make described boundary scan cell convert described the second detecting information to one scan information; And
Described the second path of conducting is in order to be sent to described scanning information described testing cushion unit.
14. method of testing as claimed in claim 13 is characterized in that, when described the first path was switched on, described the second path was not switched on, and when described the second path was switched on, described the first path was not switched on.
15. method of testing as claimed in claim 13 is characterized in that, more comprises:
Under a normal mode:
Described first, second path of conducting and described read path.
CN201110365803.3A 2011-11-17 2011-11-17 Integrated circuit Active CN103116123B (en)

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CN109154633A (en) * 2016-04-29 2019-01-04 德州仪器公司 Full pad covering boundary scan
TWI680454B (en) * 2018-04-17 2019-12-21 南亞科技股份有限公司 Dram and method of designing the same
CN113933683A (en) * 2021-09-23 2022-01-14 洛晶半导体(上海)有限公司 Chip testing system and method

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CN101551438A (en) * 2009-04-28 2009-10-07 钰创科技股份有限公司 Chip data compressing and testing multiplex circuit and chip test circuit
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CN101553879A (en) * 2006-12-15 2009-10-07 高通股份有限公司 Method and device for testing memory
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109154633A (en) * 2016-04-29 2019-01-04 德州仪器公司 Full pad covering boundary scan
TWI680454B (en) * 2018-04-17 2019-12-21 南亞科技股份有限公司 Dram and method of designing the same
CN113933683A (en) * 2021-09-23 2022-01-14 洛晶半导体(上海)有限公司 Chip testing system and method
CN113933683B (en) * 2021-09-23 2024-04-23 洛晶半导体(上海)有限公司 Chip testing system and method

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