CN116148272A - Chip failure analysis method - Google Patents

Abstract

The embodiment of the application relates to a chip failure analysis method, which comprises the following steps: unsealing the back surface of the chip; performing failure positioning on the back of the chip and forming a back mark at the positioned failure position; unsealing the front surface of the chip; the back mark is displayed on the front surface of the chip by utilizing the chip after the light is transmitted through the unsealed chip, and a front mark overlapped with the back mark is formed on the front surface of the chip; and performing physical failure analysis on the front surface of the chip by using the front surface mark. The chip failure analysis method provided by the embodiment of the application has the advantages that the failure positioning result is accurate, and high-precision analysis can be realized.

Description

Chip failure analysis method

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for analyzing chip failure.

Background

When the chip failure analysis is performed, the failure position needs to be positioned first, and then specific defect analysis is performed. The purpose of failure location is to find the physical location of the defect within the chip, which is a critical step in the whole analysis process, and if the failure location is inaccurate, the subsequent analysis results will deviate greatly.

The chip is usually fixed in the plastic package body, and the plastic package body can play roles of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance. When the chip failure analysis is performed, the chip needs to be unsealed, namely, the plastic package body covered on the surface is removed, and the functional structure layer of the device in the chip is exposed. The unsealing generally adopts methods such as laser and chemical acid dropping corrosion, specifically, for example, a laser unsealing machine is adopted to pre-unseal the chip plastic package body, and then acid liquor is slowly dropped on the surface of the chip so that the rest plastic package body is corroded by the acid liquor to be removed. The process is slow, the flow time is long, and if the functional structure layer in the chip is damaged in the unsealing process, the accuracy of failure positioning can be affected.

The prior art can generally select to perform failure analysis on the front side of the chip or failure analysis on the back side of the chip, and the two modes have advantages and disadvantages. The process of failure analysis on the front side of the chip is as follows: unsealing the front surface of the chip, removing the passivation layer and the metal layer on the front surface of the chip, performing failure positioning on the front surface, and performing specific failure analysis on the front surface. The failure analysis process on the back of the chip is as follows: unsealing the back of the chip, removing the layer on the back of the chip, removing the metal layer on the back of the chip, performing failure positioning on the back, and performing specific failure analysis on the back. The damage to the functional structure layer in the chip is caused in the unsealing process, the damage is mainly easy to occur in the front failure analysis, the material property of the passivation layer positioned on the front of the chip is close to that of the plastic package body, the passivation layer is easy to be damaged when the plastic package body is removed, and the failure mode is changed. In addition, the front failure analysis needs to remove the plastic package, the passivation layer and the metal layer on the front surface of the chip, and the damage to the chip structure to be tested can introduce interference factors, which can also cause the change of the fault mode. Eventually leading to inaccurate positioning of the failure. If backside failure analysis is selected, the accuracy is far lower than that of the front side analysis when specific failure analysis is performed on the backside since the mark of the failure position is formed on the backside of the chip. It will be appreciated that, for example, in the case of a discrete device chip composed of repeated cells, the positioning is aimed at identifying the failed individual cells, which is easy to achieve on the front side of the chip, but on the back side of the chip, since there is no pattern corresponding to each cell, the failed cells are often only roughly determined according to the marks, and it is difficult to achieve high-precision analysis.

Disclosure of Invention

In view of this, the embodiments of the present application provide a chip failure analysis method for solving at least one of the problems existing in the background art.

Specifically, the method comprises the following steps:

unsealing the back surface of the chip;

performing failure positioning on the back of the chip and forming a back mark at the positioned failure position;

unsealing the front surface of the chip;

the back mark is displayed on the front surface of the chip by utilizing the chip after the light is transmitted through the unsealing, and a front mark overlapped with the back mark is formed on the front surface of the chip;

and performing physical failure analysis on the front side of the chip by using the front side mark.

In an alternative embodiment, the making the backside mark appear on the front side of the chip includes:

observing the chip by using an optical microscope positioned on one side of the front surface of the chip, adjusting the focal length of the optical microscope to enable the optical microscope to be focused on the back surface of the chip, moving an observation area of the optical microscope, and searching for the back surface mark;

the focal length of the optical microscope is adjusted so that the optical microscope is focused on the front side of the chip at a position where the back side mark can be observed.

In an alternative embodiment, the forming the front mark on the front surface of the chip, where the front mark coincides with the back mark, includes:

the front side mark is formed by laser irradiation.

In an alternative embodiment, after the unsealing the back surface of the chip and before the unsealing the chip by light transmission, the method further includes:

and removing the back metal layer of the chip.

In an alternative embodiment, after said unsealing the front surface of the chip and before said unsealing the chip by light transmission, the method further comprises:

and removing the front metal layer of the chip.

In an alternative embodiment, the unsealing the front surface of the chip includes:

and immersing the chip into corrosive liquid required for unsealing.

In an alternative embodiment, the chip after unsealing by light transmission includes:

the substrate material corresponding to the chip is silicon carbide, and the chip is unsealed by irradiation of visible light.

In an alternative embodiment, the chip after unsealing by light transmission includes:

the substrate material corresponding to the chip is silicon, and the chip after unsealing is irradiated by infrared light.

In an alternative embodiment, after forming the front side mark, the method further comprises: and performing physical failure analysis on the chip.

The chip failure analysis method provided by the embodiment of the application comprises the following steps: unsealing the back surface of the chip; performing failure positioning on the back of the chip and forming a back mark at the positioned failure position; unsealing the front surface of the chip; the back mark is displayed on the front surface of the chip by utilizing the chip after the light is transmitted through the unsealed chip, and a front mark overlapped with the back mark is formed on the front surface of the chip; and performing physical failure analysis on the front surface of the chip by using the front surface mark. Because the failure positioning is completed on the back of the chip, before the failure positioning, the plastic package body and the internal functional structure layer on the front of the chip are completely reserved, so that the failure mode of the chip is not changed, and the failure positioning result is accurate; the chip after the unsealing is penetrated by light, and the position where the back mark can be observed is searched on the front surface, so that the front mark is formed, and high-precision analysis can be realized.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

fig. 1 is a schematic flow chart of a chip failure analysis method provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a chip structure after backside marking is formed in an embodiment of the present application;

FIG. 3 is an electron microscope image of a backside mark on the backside of a chip using an optical microscope;

FIG. 4 is a schematic view of a scene of searching for a back mark position on the front surface of a chip by using an optical microscope in the embodiment of the present application;

FIG. 5 is an electron microscope image corresponding to FIG. 4 with the optical microscope used to view the backside marking on the front side of the chip and the optical microscope focused on the backside;

FIG. 6 is a schematic view of a scenario in which the focal length of an optical microscope is adjusted to focus the optical microscope on the front surface in an embodiment of the present application;

FIG. 7 is an electron microscope image corresponding to FIG. 6 with the optical microscope used to view the backside marking on the front side of the chip and the optical microscope focused on the front side;

FIG. 8 is a schematic view of a scene of forming a front mark at a found position in an embodiment of the present application;

FIG. 9 is an electron microscope image corresponding to FIG. 8 for observing the front side mark on the front side of the chip using an optical microscope;

FIG. 10 is a plot of drain-source saturation current versus reverse breakdown voltage for the comparative example;

FIG. 11 is a plot of drain-source saturation current versus reverse breakdown voltage in an embodiment.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

The embodiment of the application provides a chip failure analysis method, please refer to fig. 1, which includes:

s01, unsealing the back surface of the chip;

step S02, failure positioning is carried out on the back surface of the chip, and a back surface mark is formed at the positioned failure position;

s03, unsealing the front surface of the chip;

step S04, utilizing the light to penetrate through the unsealed chip, enabling the back mark to be displayed on the front surface of the chip, and forming a front mark overlapped with the back mark on the front surface of the chip;

and S05, performing physical failure analysis on the front side of the chip by using the front side mark.

It will be appreciated that this embodiment differs from the prior art process of performing failure analysis on the front side of the chip, and from the prior art process of performing failure analysis on the back side of the chip. In this embodiment, the failure positioning is performed on the back side of the chip, and then the specific failure analysis can be performed on the front side of the chip, where the key is that in step S04, accurate copy transfer of the back side mark to the front side of the chip is achieved, so that the problems that the failure positioning of the front side failure analysis is inaccurate and the failure analysis of the back side is difficult to achieve high accuracy are avoided. Because the failure positioning is completed on the back of the chip in the embodiment, before the failure positioning, the plastic package body and the internal functional structure layer on the front of the chip are completely reserved, so that the failure mode of the chip is not changed, and the failure positioning result is accurate; the chip after the unsealing is penetrated by light, and the position where the back mark can be observed is searched on the front surface, so that the front mark is formed, and high-precision analysis can be realized. In this embodiment, the back surface and the front surface of the chip are both required to be unsealed, but since the failure position is determined when the front surface of the chip is unsealed, the problems of passivation layer damage, interference factor introduction and the like caused by the front surface unsealing process are not required to be considered, and thus the unsealing process can be performed quickly.

Next, please refer to fig. 2. Fig. 2 shows a chip 100. The chip 100 may be a power device, a memory, an optoelectronic device, etc. In a specific example, chip 100 is a silicon carbide field effect transistor (SiC MOSFET) device.

Although not specifically shown in the drawings, it is understood that the chip 100 includes a substrate and a functional structural layer formed on the substrate; and before unsealing, the substrate and the functional structure layer are sealed by the plastic package body. The substrate is, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or the like. For different substrate materials, light sources with different wave bands can be used for irradiation in the subsequent steps. The material of the plastic package body may be a plastic package material commonly used in the art, such as modified epoxy resin, and the like.

As shown in fig. 2, the chip 100 includes a back side 101 and a front side 102 opposite to each other.

In step S01, the back surface 101 of the chip 100 may be unsealed by a back surface unsealing process commonly used in the art, which is not particularly limited in this application.

After unsealing the back side 101 of the chip 100, the method may further comprise: the back metal layer of the chip 100 is removed. It will be appreciated that this step is relevant to the particular device type of chip 100, not all chips have a backside metal layer, e.g., devices with lateral structures typically have no backside metal layer, and electrodes are disposed on the front side of the chip; while part of the electrodes in the vertical structure are arranged on the back side of the chip. In a vertical MOS device, a drain is provided on the back surface of the chip, and thus, after the back surface 101 of the chip 100 is unsealed, the back metal layer serving as the drain is exposed. For chips with a backside metal layer in the structure, removing the backside metal layer can avoid the backside metal layer from blocking light and making it impossible to observe backside marks in the later steps when the chip 100 is unsealed by light transmission.

After unsealing the back surface 101 of the chip 100 and removing the back metal layer of the chip 100, before failure positioning, the plastic package and the internal functional structure layer on the front surface of the chip 100 are reserved.

Next, step S02 is performed to perform failure positioning on the back surface 101 of the chip 100 and form a back surface mark 110 (refer to fig. 2) at the positioned failure position.

Specifically, a laser method may be used to etch back mark 110 at the located failure location. Similarly, in a subsequent step, the front side mark may also be formed by laser methods. Of course, in this embodiment, the front mark and the back mark may be formed by different methods.

The back surface mark is observed from the back surface of the chip by using an optical microscope, so that the pattern of the back surface mark can be clearly observed, and the obtained electron microscope image can be referred to as fig. 3. As shown in the figure, since there is no pattern corresponding to each cell on the back side of the chip, it is impossible to determine which cell the back side mark is specifically directed to in the electron microscope image.

Next, step S03 is performed to unseal the front surface 102 of the chip 100.

Optionally, unsealing the front side 102 of the chip 100 includes: the chip 100 is immersed in an etching solution required for unsealing. Because the failure position is determined at this time, the problems of passivation layer damage, interference factor introduction and the like caused by the front opening process do not need to be considered, and therefore, the step S03 is rapidly performed by adopting a soaking mode. Compared with the process of failure analysis on the front surface of the chip in the prior art, the time required for the step of unsealing the front surface of the chip is greatly shortened. In practical operation, each chip in the prior art needs about 5 hours to finish the front opening, and the front opening step in this embodiment only needs about 1 hour.

Since the back surface 101 of the chip 100 is already unsealed, the die can be taken out after unsealing the front surface 102 of the chip 100 at the time of actual execution.

And then, removing the passivation layer to expose the front metal layer. In a specific example, the passivation layer is, for example, a polyimide film (Pi).

After unsealing the front side 102 of the chip 100 and before the unsealed chip 100 is transmitted by light, the method may further include: the front side metal layer of the chip 100 is removed. Since the metal material used for preparing the chip electrode generally blocks the light, removing the front metal layer of the chip 100 can avoid that the light cannot penetrate the front metal layer and the backside mark 110 cannot be observed when the chip 100 is unsealed by light irradiation in the subsequent steps.

It will be appreciated that after unsealing the front side 102 of the chip 100 and removing the front side metal layer of the chip 100, no front side failure location is required.

Next, step S04 is performed to make the back surface mark 110 appear on the front surface 102 of the chip 100 by the light transmitted through the unsealed chip 100, and to form the front surface mark 120 overlapping with the back surface mark 110 in position on the front surface 102 of the chip 100.

It is understood that the positional registration here refers to the projection registration of the front surface mark 120 and the rear surface mark 110 in the thickness direction of the substrate 100; in other words, the positions of the front surface mark 120 and the back surface mark 110 in the thickness direction of the chip are different, but the positions in the planar direction of the chip are the same.

Wherein the light may be a light source that is self-contained with the optical microscope 200.

Please refer to fig. 4. The visualization of the backside indicia 110 on the front side 102 of the chip 100 may specifically include: the chip 100 is observed with the optical microscope 200 located on the front side 102 of the chip 100, the focal length of the optical microscope 200 is adjusted so that the optical microscope is focused on the back side 101 of the chip 100, and the observation area of the optical microscope 200 is moved to find the back side mark 110.

Thus, the back surface mark can be observed on the front surface of the chip by using the focusing function of the optical microscope (Optical Microscope, OM) by utilizing the light transmission characteristic of the remaining functional structure layer of the chip. The electron microscope image may refer to fig. 5.

Optionally, the substrate material corresponding to chip 100 is silicon carbide, and the unsealed chip is irradiated with visible light. The substrate material corresponding to the chip 100 is silicon, and the unsealed chip is irradiated with infrared light. Thus, failure analysis of various chips with different substrates can be realized by using different light sources of the optical microscope.

It can be understood that the chip failure analysis method provided by the application is also applicable to other transparent materials or devices, and in practical application, only a corresponding light source is needed. In addition, in the embodiments of the present application, the light source of the optical microscope is not limited to visible light and infrared light, and other light sources capable of penetrating the chip material may be applied thereto, such as laser, etc.

Next, please refer to fig. 6. The focal length of the optical microscope 200 is adjusted to focus the optical microscope on the front side 102 of the chip 100 at a location where the back side mark 110 can be observed. It should be noted that during this process, the position of the optical microscope focus is changed only in the thickness direction of the chip, i.e. transferred from the back side to the front side of the chip; the focus position is unchanged in the planar direction of the chip, and thus, the failure position corresponding to the back surface is determined on the front surface of the chip.

The image observed by the optical microscope at this time can be referred to fig. 7. The back mark 110 is not already visible in the field of view, but the front cell structure of the chip is clearly visible, due to the adjustment of the focal length of the optical microscope.

Next, please refer to fig. 8. A front surface marker 120 is formed on the front surface 102 of the chip 100 to be positioned in registration with the back surface marker 110.

Specifically, the position of the back surface mark 110 may be found by laser irradiation to form the front surface mark 120 at the position. In this way, an accurate copy transfer of the backside marking 110 to the front side of the chip is achieved.

After the front mark 120 is formed, an image observed by an optical microscope can be referred to fig. 9. As shown, the positive indicia may indicate a particular cell location.

Next, step S05 is performed to perform physical failure analysis (Physical Failure Analysis, PFA) on the front side 102 of the chip 100 using the front side flag 120. Because the failure positioning is accurate, high-precision physical failure analysis can be performed on the front surface of the chip, and a relatively accurate analysis result is obtained.

Before failure positioning, the embodiment completely reserves the packaging structure and the chip structure on the front surface of the device, keeps the fault mode of the sample, and improves the analysis efficiency by more than 70%.

Fig. 10 shows a drain-source saturation current (IDSS) versus reverse breakdown Voltage (VDS) in the comparative example, and fig. 11 shows a drain-source saturation current versus reverse breakdown voltage in the example. The comparative example adopts a method for failure analysis on the front surface of the chip in the prior art.

As is apparent from fig. 10, the reverse breakdown voltage VDS has been changed in the curve (b) measured after the front metal layer is removed, compared to the curve (a) measured before the front metal layer is removed. Whereas in the curves of the embodiment shown in fig. 11, the curves measured before and after the front metal layer is removed substantially coincide, i.e., fig. a and b substantially coincide. It follows that embodiments do not result in a change in failure mode.

It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the various features of the above embodiments may be combined arbitrarily to form further embodiments of the application that may not be explicitly described. Thus, the above examples merely represent several embodiments of the present application and do not limit the scope of protection of the patent of the present application.

Claims (8)

1. A method for chip failure analysis, the method comprising:

unsealing the back surface of the chip;

performing failure positioning on the back of the chip and forming a back mark at the positioned failure position;

unsealing the front surface of the chip;

the back mark is displayed on the front surface of the chip by utilizing the chip after the light is transmitted through the unsealing, and a front mark overlapped with the back mark is formed on the front surface of the chip;

and performing physical failure analysis on the front side of the chip by using the front side mark.

2. The method of claim 1, wherein the visualizing the backside marking on the front side of the chip comprises:

observing the chip by using an optical microscope positioned on one side of the front surface of the chip, adjusting the focal length of the optical microscope to enable the optical microscope to be focused on the back surface of the chip, moving an observation area of the optical microscope, and searching for the back surface mark;

the focal length of the optical microscope is adjusted so that the optical microscope is focused on the front side of the chip at a position where the back side mark can be observed.

3. The method for analyzing chip failure according to claim 1 or 2, wherein forming a front surface mark overlapping with a back surface mark position on a front surface of the chip comprises:

the front side mark is formed by laser irradiation.

4. The method of claim 1, wherein after unsealing the back surface of the chip and before the unsealed chip is penetrated by the light, the method further comprises:

and removing the back metal layer of the chip.

5. The method of claim 1, wherein after unsealing the front surface of the chip and before the unsealed chip is penetrated by the light, the method further comprises:

and removing the front metal layer of the chip.

6. The method of claim 1, wherein unsealing the front side of the chip comprises:

and immersing the chip into corrosive liquid required for unsealing.

7. The method of claim 1, wherein the unsealed chip by light transmission comprises:

the substrate material corresponding to the chip is silicon carbide, and the chip is unsealed by irradiation of visible light.

8. The method of claim 1, wherein the unsealed chip by light transmission comprises:

the substrate material corresponding to the chip is silicon, and the chip after unsealing is irradiated by infrared light.

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