CN116136031A - Reactive ion etching method and preparation method of vertical cavity surface emitting laser - Google Patents

Reactive ion etching method and preparation method of vertical cavity surface emitting laser Download PDF

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CN116136031A
CN116136031A CN202310409703.9A CN202310409703A CN116136031A CN 116136031 A CN116136031 A CN 116136031A CN 202310409703 A CN202310409703 A CN 202310409703A CN 116136031 A CN116136031 A CN 116136031A
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etching
epitaxial wafer
layer
emitting laser
vertical cavity
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CN116136031B (en
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白龙刚
顾本祥
张松涛
余里程
惠利省
杨国文
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Dugen Core Optoelectronics Technology Suzhou Co ltd
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/08—Etching
    • C30B33/12—Etching in gas atmosphere or plasma
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B7/00—Cleaning by methods not provided for in a single other subclass or a single group in this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The application relates to a reactive ion etching method and a preparation method of a vertical cavity surface emitting laser, which are used for removing side wall products of an etching groove of the vertical cavity surface emitting laser. The sidewall product is a polymer comprising C and In, and the polymer comprises: o, P, ga, as and F. The etching process parameters comprise: the etching power is 100W-120W, the cavity pressure is 120mTorr-180mTorr, the etching environment temperature is 150-200 ℃, the etching gas is hydrogen and argon, the flow of the hydrogen gas is 70sccm-90sccm, and the flow of the argon gas is 70sccm-90sccm. The process of etching the sidewall product is a micro-processing process. In the process: the cavity is controlled in a proper pressure environment, the anisotropism is enhanced, and the etching rate and the ion damage are reduced; physically binding polymers by Ar ionsStripping the side wall of the etching groove; by H 2 As a reaction gas, the material is effectively decomposed; and the C-based product is easily volatilized and taken away by adding a proper etching temperature.

Description

Reactive ion etching method and preparation method of vertical cavity surface emitting laser
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a reactive ion etching method and a preparation method of a vertical cavity surface emitting laser.
Background
In the process of forming a deep groove of a Vertical Cavity Surface Emitting Laser (VCSEL) by adopting a plasma etching technology, etching products are easy to adhere to the side wall of the deep groove, and are not easy to remove cleanly, particularly red light products (the lasing wavelength is 650nm, 670nm or 680 nm) of the VCSEL. The side wall of the deep groove is not etched cleanly, so that uneven wet oxidation is finally caused, and the stability of electrical aging is affected.
After deep groove etching, the prior technical scheme adopts a rapid flushing and solution etching method to remove the side wall products of the deep groove, so that the effect is unstable, the side wall products cannot be thoroughly removed, uneven wet oxidation is caused, and the electrical property and aging stability are affected.
In the prior art, a certain functional layer (such as an InP cladding layer) is directly etched vertically downwards by adopting a reactive ion etching method, and the thickness of the functional layer is thicker and is generally 1-2 microns; the width is also relatively wide, typically 5 microns to 20 microns. The main purpose in the existing vertical downward etching technical scheme is to etch the base material to form a specific shape. CH is generally used 4 And H 2 On the one hand, the functional layer has proper selectivity to reactive ion etching, and can ensure that the materials of other film layers are not etched, so that proper etching rate can be used, excessive etching can be performed, and the etching depth and bottom morphology are not affected. While in other arrangements N is added 2 The method is to form a passivation protection layer on the side wall of the etched groove to obtain a specific shape. There is currently no suitable counterThe technological method of ion etching is used for removing side wall products.
Disclosure of Invention
The purpose of the application is to overcome the defect that the side wall products of the deep groove cannot be thoroughly removed and the wet oxidation is uneven in the prior art, and provide a reactive ion etching method and a preparation method of a vertical cavity surface emitting laser.
In order to achieve the above object, the present application provides a reactive ion etching method for removing a sidewall product of an etching groove of a vertical cavity surface emitting laser, wherein the sidewall product of the etching groove is a polymer including C and In, and the polymer contains: o, P, ga, as and F;
the reactive ion etching method adopts reactive ion etching equipment, and the etching process parameters comprise: the etching power is 100W-120W, the cavity pressure is 120mTorr-180mTorr, the etching environment temperature is 150-200 ℃, the etching gas is hydrogen and argon, the gas flow of the hydrogen is 70sccm-90sccm, and the gas flow of the argon is 70sccm-90sccm.
In one embodiment, the etching groove side surface comprises: the side of the P-DBR layer, the side of the first semiconductor layer, the side of the active layer, the side of the second semiconductor layer and the side of the N-DBR layer, the depth of the etching groove is 4 micrometers-5 micrometers, and the time of reactive ion etching is 2 minutes-5 minutes.
In one embodiment, the etching power is 110W, the chamber pressure is 150mTorr, the etching ambient temperature is 180deg.C, the gas flow rate of hydrogen is 80sccm, the gas flow rate of argon is 80sccm, and the time for reactive ion etching is 4 minutes.
The application also provides a preparation method of the vertical cavity surface emitting laser, which comprises the following steps:
s10, growing an epitaxial wafer on a substrate, wherein the epitaxial wafer comprises: the buffer layer, the N-DBR layer, the first semiconductor layer, the active layer, the second semiconductor layer, the P-DBR layer and the cap layer are sequentially arranged from bottom to top;
s20, performing first etching on the epitaxial wafer to form an etching groove and a boss structure;
s30, performing in-situ second etching to remove side wall products of the etching groove, wherein the second etching adopts the reactive ion etching method in any embodiment;
s40, soaking and cleaning the epitaxial wafer to obtain the boss structure with the clean surface;
s50, oxidizing the boss structure with the clean surface by adopting a wet oxidation process to obtain the boss structure with oxidation holes;
s60, evaporating a water-oxygen barrier film on the surface of the epitaxial wafer;
and S70, forming an N-type electrode on the surface of the substrate far away from the buffer layer, and forming a P-type electrode on the surface of the cap layer far away from the P-DBR.
In one embodiment, S20 includes:
s21, presetting a boss position on the epitaxial wafer, and coating photoresist on the boss position;
s22, exposing and developing the photoresist to obtain a mask pattern;
s23, performing the first etching on the epitaxial wafer with the mask pattern by adopting an inductive coupling plasma etching process to form the etching groove and the boss structure.
In one embodiment, S20 includes:
and S25, forming a passivation layer on the epitaxial wafer, and performing the first etching on the epitaxial wafer with the passivation layer so as to form the etching groove and the boss structure.
In one embodiment, S30 further comprises, after:
and S31, carrying out in-situ third etching on the epitaxial wafer after the side wall products are removed, so as to remove the residual passivation layer.
In one embodiment, the etching gas for the first etching is boron trichloride, chlorine and argon, the gas flow rate of boron trichloride is 30 sccm-50 sccm, the gas flow rate of chlorine is 8 sccm-15 sccm, the gas flow rate of argon is 30 sccm-40 sccm, and the pressure of the etching chamber is 15mTorr.
In one embodiment, the specific parameters of the wet oxidation process include: the furnace temperature of the oxidation furnace ranges from 360 ℃ to 420 ℃, the auxiliary gas is nitrogen, the flow rate of the nitrogen ranges from 1.5 liters per minute to 2 liters per minute, and the wet oxidation time ranges from 110 minutes to 120 minutes.
In one embodiment, the specific step of performing soaking cleaning on the epitaxial wafer includes: and soaking and cleaning the epitaxial wafer by sequentially adopting a methyl pyrrolidone solution, an acetone solution and an isopropanol solution to remove impurities, so as to obtain the epitaxial wafer with the boss structure and a clean surface.
The application provides a reactive ion etching method and a preparation method of a vertical cavity surface emitting laser, which are used for removing side wall products of an etching groove of the vertical cavity surface emitting laser. The sidewall product is a polymer including C and In, and the polymer contains: o, P, ga, as and F. The etching process parameters in the reactive ion etching method comprise: the etching power is 100W-120W, the cavity pressure is 120mTorr-180mTorr, the etching environment temperature is 150-200 ℃, the etching gas is hydrogen and argon, the flow of the hydrogen gas is 70sccm-90sccm, and the flow of the argon gas is 70sccm-90sccm. The process of etching the sidewall product using the reactive ion etching method of the present application is a micro-process. During reactive ion etching: the cavity is controlled in a proper pressure environment, the anisotropism is enhanced, and the etching rate and the ion damage are reduced; physically stripping the polymer from the side wall of the etching groove by means of Ar ions; by H 2 As a reaction gas, the material is effectively decomposed; and the C-based product is easily volatilized and taken away by adding a proper etching temperature.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a portion of a vertical cavity surface emitting laser including a sidewall formation according to one embodiment of the present application;
FIG. 2 is a schematic diagram of a VCSEL according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of a method for fabricating a VCSEL according to an embodiment of the present application;
FIG. 4 is a schematic view of the aperture of the VCSEL provided in example 1 of the present application;
FIG. 5 is a schematic view of the aperture of the VCSEL provided in example 2 of the present application;
fig. 6 is a schematic view of an oxidation limiting aperture of a vcsels according to embodiment 3 of the present application.
Description of the reference numerals
Vertical cavity surface emitting laser 100: a substrate 10, a buffer layer 11, an N-DBR layer 12, a first semiconductor layer 13, an active layer 14, a second semiconductor layer 15, a P-DBR layer 16, a cap layer 17, an etched trench 18, a sidewall product 19, a mesa structure 20, an oxidation limiting layer 21, an oxidation hole 22, a water-oxygen barrier film 23, a Via metal layer 24, a P-type electrode 25, and an N-type electrode 26.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
The present application provides a reactive ion etching method for removing sidewall products 19 of an etched trench 18 of a vertical cavity surface emitting laser 100. Referring to fig. 1 and 2, fig. 1 is a schematic diagram of an etched trench 18 and a sidewall product 19 of an unshaped vcsels 100, fig. 2 is a complete structure diagram of the vcsels 100, and fig. 2 also illustrates an oxide hole 22 and an exit hole (typically, the diameter of the oxide hole 22 is slightly larger than the diameter of the exit hole). The vertical cavity surface emitting laser 100 includes: a substrate 10, a buffer layer 11, an N-DBR layer 12, a first semiconductor layer 13, an active layer 14, a second semiconductor layer 15, a P-DBR layer 16, a cap layer 17, an etched trench 18, a sidewall product 19, a mesa structure 20, an oxidation limiting layer 21, an oxidation hole 22, a water-oxygen barrier film 23, a Via metal layer 24, a P-type electrode 25, and an N-type electrode 26. Wherein the substrate 10 may be GaAs; the active layer 14 may be GaAs, alGaAs, inP; the active layer 14 may be InGaAs; the N-DBR layer and the P-DBR layer 16 may be GaAs, alGaAs, inP. The sidewall product 1919 is a product formed by polymerizing the materials of the respective material layers of the vertical cavity surface emitting laser 100 at a high temperature. The sidewall formation 19 is a polymer including C and In. The polymer may also include one or more of O, P, ga, as, F. In some embodiments, sidewall formation 19 may also include other elements in addition to the polymers described above.
The reactive ion etching method adopts reactive ion etching equipment, and the etching process parameters comprise: the etching power is 100W-120W, the cavity pressure is 120mTorr-180mTorr, the etching environment temperature is 150-200 ℃, the etching gas is hydrogen and argon, the gas flow of the hydrogen is 70sccm-90sccm, and the gas flow of the argon is 70sccm-90sccm.
In this embodiment, the sidewall product 19 of the etched trench 18 of the VCSEL 100 is removed by reactive ion etching. The sidewall formation 19 is thin and non-uniform, typically on the order of nanometers. In one embodiment, sidewall formation 19 is a polymer that includes C, O, in, P, ga, as, F. In one embodiment, sidewall formation 19 is a polymer that includes C, in, P, ga, as, F. In one embodiment, sidewall formation 19 is a polymer that includes C, O, in, ga, as, F. In one embodiment, sidewall formation 19 is a polymer that includes C, O, in, P, as, F. In one embodiment, sidewall formation 19 is a polymer that includes C, O, in, P, ga, as. In one embodiment, sidewall formation 19 is a polymer that includes C, O, in, P, ga, F. In one embodiment, sidewall formation 19 is a polymer that includes C, in, ga, as, F. In other embodiments the sidewall formation 19 may be other. Damage to other film materials is not desirable during removal of the sidewall formation 19, so the reactive ion etching process cannot be too fast, and the nanoscale polymers of the sidewalls are mainly removed. The inventors found through a great deal of experimental study: in the reactive ion etching method, CH cannot be increased 4 As an etching gas. Once CH is increased 4 A C-H compound is produced and the sidewalls of etched trench 18 are repassivated.
In the present embodiment, the process of etching the sidewall product 19 by the reactive ion etching method is a process of micro-treating the sidewall product 19. The process comprises the following steps: firstly, the cavity is controlled in a proper pressure environment (120 mTorr-180 mTorr), so that the anisotropism can be enhanced, the etching rate and the ion damage can be reduced (the etching rate in the traditional scheme is generally 200-500 nm/min, and the etching rate achieved by adopting the technical scheme provided by the embodiment is generally less than 50nm/min, so that the etching rate is obviously reduced, and the etching rate is reduced by 75% -90%); second, the polymer is physically stripped from the sidewalls of etch bath 18 by means of Ar ions; third, by H 2 The substance containing P is decomposed to produce PH as a reaction gas 3 Pumping out the gas; fourth, the proper temperature is added in the whole etching processThe temperature is 150-200 ℃, and other C-based products are volatilized and taken away. The reactive ion etching method provided in this embodiment can effectively remove the sidewall product 19 of the etching groove 18 of the vertical cavity surface emitting laser 100.
In one embodiment, the reactive ion etching method etches the sides of the trench 18 including: the side of the P-DBR layer 16, the side of the first semiconductor layer 13, the side of the active layer 14, the side of the second semiconductor layer 15, and the side of the N-DBR layer, the depth of the etched trench 18 is 4 micrometers to 5 micrometers, and the time of reactive ion etching is 2 minutes to 5 minutes.
In this embodiment, the etched trench 18 has a large depth. The sidewall product 19 formed in the etching groove 18 may be a sidewall product 19 which covers the entire depth, may be a sidewall product 19 which covers a partial depth range, or may be a sidewall product 19 which covers different depths and thicknesses. The time of the reactive ion etching in the embodiment is 2-5 minutes, the etching speed is low, the etching time is long, and the nanoscale polymer on the side wall can be removed completely on the premise of not damaging other film materials.
In one embodiment, the reactive ion etching method has an etching power of 110W, a chamber pressure of 150mTorr, an etching ambient temperature of 180deg.C, a gas flow rate of 80sccm for hydrogen, a gas flow rate of 80sccm for argon, and a reactive ion etching time of 4 minutes.
In this embodiment, specific process parameters of the reactive ion etching method are given, and the specific process parameters are as follows: first, ar and H 2 Bombarding and reacting the sidewall products 19 in a physical and chemical manner, respectively, so that gaseous byproducts can be directly discharged from the chamber; second, the greater airflow increases the rate and efficiency of byproduct removal within the chamber; third, the larger air pressure can minimize damage to the side of the P-DBR layer 16, the side of the first semiconductor layer 13, the side of the active layer 14, the side of the second semiconductor layer 15, and the N-DBR layer; fourth, lower etching power (110W) and longer response time (4 minutes) also avoid over etching, reducing damage to the N-DBR layer; fifth, a third step of, in the case of a vehicle,the proper ambient temperature (180 ℃) in the etching process can also ensure the evaporation, gasification and discharge of the residual.
Referring to fig. 3, the present application further provides a method for preparing the vertical cavity surface emitting laser 100, which includes:
s10, growing an epitaxial wafer on the substrate 10, the epitaxial wafer including: the N-DBR layer, the first semiconductor layer 13, the active layer 14, the second semiconductor layer 15, the P-DBR layer 16, and the cap layer 17 are sequentially disposed from bottom to top. In this step, a growth method such as molecular beam epitaxy may be employed.
S20, performing first etching on the epitaxial wafer to form an etching groove 18 and a boss structure 20. The first etching may expose a portion of the P-DBR layer 16 to be oxidized, where the P-DBR layer 16 is a high aluminum layer and the Al content is 98%. Such as: the first etching may employ an inductively coupled plasma etching (ICP etching) process.
S30, performing in-situ second etching to remove the side wall products 19 of the etching groove 18, wherein the second etching adopts the reactive ion etching (reaction ionetching; RIE) method in any embodiment. Through the reasonable arrangement of the second etching in the step, the side wall product 19 can be completely removed, so that water vapor is prevented from transversely drilling into an epitaxial wafer (particularly the P-DBR layer 16 with high Al component) to react with AlGaAs, and further a uniform oxidation limiting layer 21 cannot be formed in the wet oxidation process, and light beams cannot be concentrated to influence the electrical performance and the aging performance of the vertical cavity surface laser.
And S40, soaking and cleaning the epitaxial wafer to obtain the boss structure 20 with the clean surface. In this step, a special soaking solution (such as an organic solution) may be set to perform cleaning treatment (mainly remove substances such as surface photoresist) on the epitaxial wafer, so as to ensure that a clean surface is available during wet oxidation, and at the same time, ensure that no water vapor enters the epitaxial wafer.
And S50, oxidizing the boss structure 20 with the clean surface by adopting a wet oxidation process to obtain the boss structure 20 with the oxidation holes 22. In this step, the sidewall of the mesa structure 20 having a clean surface is oxidized by a wet oxidation process, al in the high aluminum layer (AlGaAs material in the P-DBR layer 16) to be oxidized therein is oxidized from the outside to the inside, thereby forming an oxidation restriction layer 21, and the intermediate unoxidized portion forms an oxidation hole 22 as an optical channel and an electrical channel, to finally obtain the mesa structure 20 having the oxidation hole 22.
S60, vapor plating a water-oxygen barrier film 23 on the surface of the epitaxial wafer. In this step, the water-oxygen barrier film 23 may be made of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, or the like. The coating process of the water-oxygen barrier film 23 may employ a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or an Atomic Layer Deposition (ALD) method.
S70, an N-type electrode 26 is formed on the surface of the substrate 10 away from the buffer layer 11, and a P-type electrode 25 is formed on the surface of the cap layer 17 away from the P-DBR. In this step, the N-type electrode 26 and the P-type electrode 25 may be gold, with a thickness of about 0.8 microns to about 5.5 microns.
In this embodiment, a method for manufacturing the vertical cavity surface emitting laser 100 is provided, which uses a reactive ion etching method to remove the sidewall product 19 of the deep trench. The sidewall formation 19 is completely removed and moisture is prevented from traversing into the epitaxial wafer (particularly the high Al composition P-DBR layer 16) and reacting with AlGaAs. After the side wall product 19 is removed completely, a more uniform oxidation limiting layer 21 can be formed in the wet oxidation process, the excited laser beams are more concentrated, and the electrical performance and the aging performance of the vertical cavity surface laser are improved.
In one embodiment, the first etching may be performed by inductively coupled plasma etching (Inductively coupled plasma etching, ICP etching), and the specific process parameters of the first etching may be set as follows: the etching gas is boron trichloride, chlorine and argon, the gas flow rate of boron trichloride is 30-50 sccm, the gas flow rate of chlorine is 8-15 sccm, the gas flow rate of argon is 30-40 sccm, the pressure of the etching chamber is 15mTorr, bias (bias of lower electrode) and RF 2 The power (radio frequency power of plasma) is 100-200W and 500-700W respectively.
In one embodiment, S20 includes:
s21, presetting a boss position on the epitaxial wafer, and coating photoresist on the boss position. The film thickness of the photoresist may be set to 5um to 15um. S22, exposing and developing the photoresist to obtain a mask pattern. S23, performing first etching on the epitaxial wafer with the mask pattern by using an inductively coupled plasma etching process (ICP etching) to form the etched grooves 18 and the mesa structures 20.
In this embodiment, a first specific method for forming the etched trench 18 is provided: a mask pattern is formed by a formation photolithography + development technique, and further a first etching is performed in accordance with the mask pattern to form etched trenches 18 and mesa structures 20.
In one embodiment, S20 includes:
s25, forming a passivation layer (SiO) 2 Or SiN), the epitaxial wafer formed with the passivation layer is subjected to a first etching to form the etched trenches 18 and the mesa structures 20.
In this embodiment, a second specific method for forming the etched trench 18 is provided: the epitaxial wafer with the passivation layer is etched for the first time by forming the passivation layer on the epitaxial wafer to form the etched trenches 18 and the mesa structures 20.
In one embodiment, S30 further comprises, after:
and S31, carrying out in-situ third etching on the epitaxial layer after the side wall product 19 is removed to remove the residual passivation layer silicon oxide/silicon nitride, wherein the third etching can adopt an inductively coupled plasma etching (ICP etching) process. The process parameters of the third etching can be set as follows: the etching power is 100W-120W, the cavity pressure is 10mTorr-15mTorr, the etching environment temperature is 25 ℃ -40 ℃ (room temperature), and the etching gas is O 2 And SF (sulfur hexafluoride) 6 ，O 2 Is 4sccm-8sccm, SF 6 The gas flow rate of (2) is 15sccm-30sccm. The third etching rate is 10-30 nm/min.
In this embodiment, when the second specific method for forming the etching groove 18 is adopted, the second etching is performed in situ at S30 to remove the sidewall product 19 of the etching groove 18, and then the method further includes: and S31, removing the passivation layer. The process steps/parameters of the third etch are different from those of the previous first etch due to the different materials and depths of the etches.
In one embodiment, specific parameters of the wet oxidation process include: the temperature range of the oxidation furnace is 360-420 ℃, the auxiliary gas is nitrogen, the flow rate range of the nitrogen is 1.5-2 liters per minute, and the wet oxidation time is 110-120 minutes. For example, in one specific embodiment, the temperature of the oxidation oven may be 380 ℃, the auxiliary gas is nitrogen, the flow rate of nitrogen is 1.9 liters per minute, and the time of wet oxidation is 120 minutes.
In this embodiment, a process parameter of wet oxidation is provided, under which the oxidation-limiting layer 21 of a better morphology can be prepared.
In one embodiment, the specific steps of soaking and cleaning the epitaxial wafer include: and soaking and cleaning the epitaxial wafer by sequentially adopting a methyl pyrrolidone solution (NMP), an acetone solution (ACE) and an isopropyl alcohol solution (IPA) to remove impurities mainly comprising C element, H element and O element, thereby obtaining the epitaxial wafer with the boss structure 20 with a clean surface.
In this embodiment, NMP solution with a temperature above 80 ℃ is adopted to soak and clean for more than 10min, ACE solution is adopted to soak and clean for more than 5min, and IPA solution is adopted to soak and clean for more than 5min, so that impurities on the surface of the epitaxial wafer can be sufficiently cleaned, and the epitaxial wafer with the boss structure 20 with the clean surface can be formed, so that the subsequent process flow is facilitated.
In a specific embodiment, a method for manufacturing a vertical cavity surface emitting laser 100 is provided, including the steps of:
step 1, growing an epitaxial wafer on a substrate 10GaAs, wherein the epitaxial wafer comprises: an N-DBR layer, a first semiconductor layer 13, an active layer 14, a second semiconductor layer 15, a P-DBR layer 16, and a cap layer 17, which are sequentially disposed from bottom to top;
step 2, presetting a boss position on the epitaxial wafer, and coating photoresist on the boss position, wherein the film thickness of the photoresist is 5-15 um; exposing and developing the photoresist to obtain a mask pattern;
and 3, performing first etching by adopting an inductive coupling plasma etching process (Inductively coupled plasma etching, ICP dry etching) to etch the epitaxial wafer with the mask pattern to form an etching groove 18 and a boss structure 20, and exposing the DBR high-aluminum layer of the limiting layer 21 to be oxidized, wherein the etching is usually performed until the lower layer of the quantum well layer is 1-10 pairs of N-DBRs. Typically the etched trenches are 4-5 microns. The gases for the first etching are boron trichloride, chlorine and argon, the flow rate of boron trichloride is 40sccm, the flow rate of chlorine is 10sccm, the flow rate of argon is 35sccm, the pressure of the etching chamber is 15mTorr, and the power of Bias power (Bias) and radio frequency power (RF 2) are 150W and 600W, respectively.
And 4, introducing hydrogen and argon into the chamber, and performing in-situ second etching by adopting reactive ion etching (Reactive ion etching, abbreviated as RIE), wherein specific process parameters of the second etching comprise: h 2 The gas flow 80sccm, ar gas flow 80sccm, process pressure 150mTorr, process power 110W, process time 3 minutes to remove the sidewall products 19 of the etch tank 18. The sidewall formation 19 of the etch tank 18 is a polymer including C, O, in, P, ga, as, F.
And 5, soaking the epitaxial wafer obtained in the step 4 by sequentially adopting a methyl pyrrolidone solution NMP, an acetone solution ACE and an isopropyl alcohol solution IPA, and cleaning photoresist mainly containing C element, H element and O element to obtain the epitaxial wafer with the boss structure 20 with the clean surface. In this step, after the second etching is completed and the sidewall product 19 is removed, an organic solution is used to remove the photoresist (the photoresist is a residue of components on the sidewall of the etching tank 18, for example, the photoresist volatilizes to the sidewall during plasma etching).
And 6, oxidizing Al in the high-aluminum layer of the boss structure 20 by adopting a wet oxidation process to obtain the boss structure 20 with the oxidation limiting structure. The temperature of the oxidation furnace was 400 ℃, the auxiliary gas included nitrogen, the flow rate of nitrogen was 1.6 liters per minute, and the time was 115 minutes.
Step 7, plating a water-oxygen barrier film 23 on the surface of the epitaxial wafer, wherein the plating process is PECVD or ALD, and the water-oxygen barrier film 23 can be SiN x 、SiO x 、SiON、AlO x 、TiO x Etc.;
step (a)8. An N-type electrode 26 is formed on the surface of the substrate 10 remote from the buffer layer 11, and a P-type electrode 25 is formed on the surface of the cap layer 17 remote from the P-DBR. Specifically, the method comprises the following steps: via hole 24 etching (exposing semiconductor material) is carried out on the epitaxial wafer, and the etching gas is CF 4 +Ar, obtaining an epitaxial wafer with Via holes 24; depositing metal to fill the Via holes 24, wherein the metal is Au, pt, ag, al and the like; depositing Pad metal, au, pt, ag, al and the like on the epitaxial wafer to finish the manufacture of the N-type electrode 26 and the P-type electrode 25; the epitaxial wafer is broken to obtain the vertical cavity surface emitting laser 100 of the present application.
Finally, a comparative experiment was performed on the technical effects of the reactive ion etching method and the method for manufacturing the vertical cavity surface emitting laser 100.
Example 1: after forming the etching groove 18 by ICP etching, directly performing wet oxidation to form an oxidation limiting structure, thereby further obtaining the vertical cavity surface emitting laser 100;
example 2: after forming the etching groove 18 by ICP etching, the sidewall residue is removed by an acidic or alkaline solution (dilute HCL, ammonia water, developer, etc.); wet oxidation is carried out to form an oxidation limiting structure, and the vertical cavity surface emitting laser 100 is further obtained;
example 3 (technical scheme of the present application): after forming the etching groove 18 by ICP etching, the sidewall product 19 is removed by reactive ion etching (RIE micro-processing) of the present application, and wet oxidation is performed to form an oxidation-limited structure, thereby further obtaining the vertical cavity surface emitting laser 100.
Fig. 4 is an effect diagram of embodiment 1, fig. 5 is an effect diagram of embodiment 2, and fig. 6 is an effect diagram of embodiment 3. The diameters of the light emitting holes of the vertical cavity surface emitting laser 100 obtained in the three embodiments are respectively marked in the three figures, and D1, D2 and D3 in the figures are the diameters of the light emitting holes schematically shown in the three embodiments. The diameter of the light outlet hole is generally about 10 microns, and the more uniform the diameter of the light outlet hole is, the better the light outlet effect is. As is apparent from comparing fig. 4 to fig. 6, the diameter D3 of the light exit hole in fig. 6 is most uniform, and the error value of the symmetry of the light exit hole is the smallest.
Therefore, the removal of the sidewall product 19 by the reactive ion etching method (RIE micro-processing) of the present application is optimal. After the sidewall product 19 is removed, a more uniform oxidation limiting layer 21 can be formed in the wet oxidation process of the device (especially the red VCSEL product), the excited laser beams are more concentrated, and the electrical performance and the aging performance of the vertical cavity surface laser are improved.
The application also relates to a vertical cavity surface emitting laser 100, and the vertical cavity surface emitting laser 100 is obtained by adopting the preparation method of any embodiment.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A reactive ion etching method, characterized In that the sidewall product of an etching groove of a vertical cavity surface emitting laser is removed, the sidewall product of the etching groove is a polymer comprising C and In, and the polymer comprises: o, P, ga, as and F;
the reactive ion etching method adopts reactive ion etching equipment, and the etching process parameters comprise: the etching power is 100W-120W, the cavity pressure is 120mTorr-180mTorr, the etching environment temperature is 150-200 ℃, the etching gas is hydrogen and argon, the gas flow of the hydrogen is 70sccm-90sccm, and the gas flow of the argon is 70sccm-90sccm.
2. The reactive ion etching method of claim 1, wherein the etching the sides of the trench comprises: the side of the P-DBR layer, the side of the first semiconductor layer, the side of the active layer, the side of the second semiconductor layer and the side of the N-DBR layer, the depth of the etching groove is 4 micrometers-5 micrometers, and the time of reactive ion etching is 2 minutes-5 minutes.
3. The method of claim 2, wherein the etching power is 110W, the chamber pressure is 150mTorr, the etching ambient temperature is 180 ℃, the gas flow rate of hydrogen is 80sccm, the gas flow rate of argon is 80sccm, and the time of reactive ion etching is 4 minutes.
4. A method of fabricating a vertical cavity surface emitting laser, comprising:
s10, growing an epitaxial wafer on a substrate, wherein the epitaxial wafer comprises: the buffer layer, the N-DBR layer, the first semiconductor layer, the active layer, the second semiconductor layer, the P-DBR layer and the cap layer are sequentially arranged from bottom to top;
s20, performing first etching on the epitaxial wafer to form an etching groove and a boss structure;
s30, performing in-situ second etching to remove side wall products of the etching groove, wherein the second etching adopts the reactive ion etching method as set forth in any one of the claims 1-3;
s40, soaking and cleaning the epitaxial wafer to obtain the boss structure with the clean surface;
s50, oxidizing the boss structure with the clean surface by adopting a wet oxidation process to obtain the boss structure with oxidation holes;
s60, evaporating a water-oxygen barrier film on the surface of the epitaxial wafer;
and S70, forming an N-type electrode on the surface of the substrate far away from the buffer layer, and forming a P-type electrode on the surface of the cap layer far away from the P-DBR.
5. The method of manufacturing a vertical cavity surface emitting laser according to claim 4, wherein S20 comprises:
s21, presetting a boss position on the epitaxial wafer, and coating photoresist on the boss position;
s22, exposing and developing the photoresist to obtain a mask pattern;
s23, performing the first etching on the epitaxial wafer with the mask pattern by adopting an inductive coupling plasma etching process to form the etching groove and the boss structure.
6. The method of manufacturing a vertical cavity surface emitting laser according to claim 4, wherein S20 comprises:
and S25, forming a passivation layer on the epitaxial wafer, and performing the first etching on the epitaxial wafer with the passivation layer so as to form the etching groove and the boss structure.
7. The method of manufacturing a vertical cavity surface emitting laser according to claim 6, further comprising, after S30:
and S31, carrying out in-situ third etching on the epitaxial wafer after the side wall products are removed, so as to remove the residual passivation layer.
8. The method of manufacturing a vertical cavity surface emitting laser according to claim 5 or 6, wherein the etching gas for the first etching is boron trichloride, chlorine and argon, the flow rate of the boron trichloride is 30sccm to 50sccm, the flow rate of the chlorine is 8sccm to 15sccm, the flow rate of the argon is 30sccm to 40sccm, and the pressure of the etching chamber is 15mTorr.
9. The method of manufacturing a vertical cavity surface emitting laser according to claim 4, wherein specific parameters of the wet oxidation process include: the furnace temperature of the oxidation furnace ranges from 360 ℃ to 420 ℃, the auxiliary gas is nitrogen, the flow rate of the nitrogen ranges from 1.5 liters per minute to 2 liters per minute, and the wet oxidation time ranges from 110 minutes to 120 minutes.
10. The method for preparing a vertical cavity surface emitting laser according to claim 4, wherein the specific step of performing immersion cleaning on the epitaxial wafer comprises: and soaking and cleaning the epitaxial wafer by sequentially adopting a methyl pyrrolidone solution, an acetone solution and an isopropanol solution to remove impurities, so as to obtain the epitaxial wafer with the boss structure and a clean surface.
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CN113659424A (en) * 2021-09-10 2021-11-16 深圳市中科光芯半导体科技有限公司 Top-emitting vertical-cavity surface-emitting laser with uniform light emission and preparation method thereof
CN114583550A (en) * 2022-03-02 2022-06-03 深圳博升光电科技有限公司 Vertical cavity surface emitting laser, electronic device having the same, and method of manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030224595A1 (en) * 2002-05-31 2003-12-04 Smith Patricia Beauregard Methods for polymer removal following etch-stop layer etch
CN1468977A (en) * 2002-07-19 2004-01-21 联华电子股份有限公司 Residual polymer eliminating method
CN106099637A (en) * 2016-07-13 2016-11-09 中国科学院半导体研究所 Two step dry etching methods based on nano impression grating and epitaxial wafer and laser instrument
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