CN116131848A - Open-loop fractional frequency divider supporting nonlinear correction, system on chip and electronic equipment - Google Patents

Open-loop fractional frequency divider supporting nonlinear correction, system on chip and electronic equipment Download PDF

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CN116131848A
CN116131848A CN202310147020.0A CN202310147020A CN116131848A CN 116131848 A CN116131848 A CN 116131848A CN 202310147020 A CN202310147020 A CN 202310147020A CN 116131848 A CN116131848 A CN 116131848A
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signal
digital
operation result
outputs
phase error
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邓伟
杨宇蒙
贾海昆
池保勇
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Tsinghua University
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Tsinghua University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention provides an open loop fractional frequency divider supporting nonlinear correction, a system on a chip and electronic equipment, which relate to the technical field of integrated circuits and comprise the following components: the multi-mode frequency divider is connected with the digital time converter; the digital time converter is respectively connected with the digital domain fitting module and the phase-locked loop module; the multi-mode frequency divider receives the reference clock signal and the frequency division control signal and outputs a frequency division signal to the digital time converter; the digital time converter receives the frequency division signal, performs nonlinear correction on the digital time converter by combining the piecewise nonlinear predistortion function to obtain an output signal and outputs the output signal; the phase-locked loop module acquires an output signal, extracts a phase error signal and outputs the phase error signal to the digital domain fitting module; and the digital domain fitting module carries out nonlinear fitting in the digital domain according to the phase error signal and the multi-bit signal to obtain a piecewise nonlinear predistortion function. The invention effectively reduces the complexity of nonlinear correction operation. A large performance boost is obtained at the cost of less power consumption and area.

Description

Open-loop fractional frequency divider supporting nonlinear correction, system on chip and electronic equipment
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an open-loop fractional frequency divider supporting nonlinear correction, a system on a chip and electronic equipment.
Background
With the continual search for portable electronic device performance, more and more circuit modules are integrated into a system on a chip (SoC), and providing high quality clock signals to the different modules is a key issue in the SoC.
In the SoC system at present, different circuit modules have different requirements on indexes such as frequency, jitter and the like of clock signals. In a conventional SoC, each clock signal is provided by a separate Phase Locked Loop (PLL) in order to meet the requirements of the respective module. However, the implementation of the PLL in the system on chip consumes a large amount of power consumption, occupies a large area, and has a very complex design process, so that the integration level of the SoC system is greatly limited.
Another idea of providing a clock signal is to divide a high quality clock with an open-loop fractional divider to obtain a set of clock signals of different frequencies. However, the existing open-loop fractional divider requires a complicated correction means due to the limitation of the system structure, and cannot stably work under various conditions, so that the nonlinearity of the circuit can cause serious interference to clock signals, and particularly cannot generate high-quality clock signals when the process, voltage and temperature (PVT) fluctuation is caused.
Therefore, how to reduce the complexity of the nonlinear correction operation while ensuring the generation of high-quality clock signals with smaller power consumption and area is a problem to be solved.
Disclosure of Invention
In view of the above, the present invention proposes an open loop fractional divider, a system on a chip and an electronic device supporting nonlinear correction.
The embodiment of the invention provides an open-loop fractional frequency divider supporting nonlinear correction, which comprises the following components: the device comprises a multi-modulus frequency divider, a digital time converter, a digital domain fitting module and a phase-locked loop module;
the multi-mode frequency divider is connected with the digital time converter;
the digital time converter is respectively connected with the digital domain fitting module and the phase-locked loop module;
the multi-mode frequency divider receives a reference clock signal and a frequency division control signal and outputs a frequency division signal to the digital time converter;
the digital time converter receives the frequency division signal, performs nonlinear correction on the digital time converter by combining a piecewise nonlinear predistortion function generated by the digital domain fitting module, and obtains an output signal and outputs the output signal;
the phase-locked loop module acquires the output signal, extracts a phase error signal in the output signal and outputs the phase error signal to the digital domain fitting module;
and the digital domain fitting module carries out nonlinear fitting in a digital domain according to the phase error signal and the multi-bit signal from the control unit to obtain the piecewise nonlinear predistortion function.
Optionally, the phase-locked loop module includes: a phase comparator, a digital filter, a digital controlled oscillator, and an integer divider;
the phase comparator is connected with the digital filter, the integer frequency divider and the digital domain fitting module;
the digital filter is connected with the numerical control oscillator;
the numerical control oscillator is connected with the integer frequency divider;
the phase comparator receives the output signal and the spurious-free clock signal, generates the phase error signal and outputs the phase error signal to the digital filter and the digital domain fitting module;
the digital filter filters the phase error signal and outputs the phase error signal to the numerical control oscillator;
the digital control oscillator receives the filtered phase error signal, and the generated digital control clock signal is output to the integer frequency divider;
and the integer frequency divider processes the numerical control clock signal to generate the spurious-free clock signal and outputs the spurious-free clock signal to the phase comparator.
Optionally, the digital domain fitting module performs segmentation processing on the phase error signal to obtain a multi-segment correction coefficient;
the digital domain fitting module determines a target segment correction coefficient when nonlinear fitting is performed in a digital domain according to the multi-bit signal, wherein the target segment correction coefficient is any segment correction coefficient in the multi-segment correction coefficients;
and the digital domain fitting module performs function operation according to the phase error signal, the multi-bit signal and the target segment correction coefficient to obtain the piecewise nonlinear predistortion function.
Optionally, the control unit generates a frequency control word, the frequency control word comprising: a frequency control word high bit signal and a frequency control word low bit signal;
the low-bit signal of the frequency control word is modulated by a DSM modulator to generate a single-bit signal and the multi-bit signal;
and adding the single-bit signal and the high-bit signal of the frequency control word to obtain the frequency signal.
Optionally, the digital domain fitting module includes: a 0-th factorial unit, a 1-th factorial unit, a 2-th factorial unit, a first adder and a second adder;
the operation result of the 1-order multiplication unit and the operation result of the 2-order multiplication unit are added through the second adder and output to the first adder;
and the first adder adds the output result of the second adder and the operation result of the 0-th order multiplication unit to obtain the piecewise nonlinear predistortion function.
Optionally, the 0 factorial unit includes: a first multiplier, a second multiplier and a first multiplexing unit;
the first multiplier multiplies the phase error signal and a first preset coefficient and outputs the operation result to the first multipath selection unit;
the first multi-path selection unit selects an operation result corresponding to the correction coefficient of the target segment according to the multi-bit signal and outputs the operation result to the second multiplier;
the second multiplier outputs an operation result corresponding to the target segment correction coefficient as an operation result of the 0-th order multiplication unit to the first adder.
Optionally, the 1 factorial unit includes: a third multiplier, a fourth multiplier, and a second multiplexing unit;
the third multiplier multiplies the phase error signal, the multi-bit signal and a second preset coefficient and outputs the operation result to the second multi-path selection unit;
the second multi-path selection unit selects an operation result corresponding to the correction coefficient of the target segment according to the multi-bit signal and outputs the operation result to the fourth multiplier;
the fourth multiplier multiplies the multi-bit signal by an operation result corresponding to the correction coefficient of the target segment, and outputs the operation result as an operation result of the 1-th order multiplication unit to the second adder.
Optionally, the 2 factorial unit includes: a fifth multiplier, a sixth multiplier, and a third multiplexing unit;
the fifth multiplier multiplies the phase error signal, the square signal of the multi-bit signal and a third preset coefficient, and outputs the operation result to the third multiplexing unit;
the third multi-path selection unit selects an operation result corresponding to the correction coefficient of the target segment according to the multi-bit signal and outputs the operation result to the sixth multiplier;
the sixth multiplier multiplies the operation result of the square signal of the multi-bit signal and the correction coefficient corresponding to the target segment, and outputs the operation result as the operation result of the 2-th order multiplication unit to the second adder.
The embodiment of the invention also provides a system on a chip, which comprises: an open loop fractional divider supporting nonlinear correction as claimed in any one of the preceding claims.
The embodiment of the invention also provides electronic equipment, which comprises: an open loop fractional divider supporting nonlinear correction as claimed in any one of the preceding claims.
The invention provides an open loop fractional frequency divider supporting nonlinear correction, comprising: a multi-modulus divider, a digital-to-time converter, a digital domain fitting module, and a phase-locked loop module. The multi-mode frequency divider is connected with the digital time converter; the digital time converter is respectively connected with the digital domain fitting module and the phase-locked loop module.
The multi-mode frequency divider receives a reference clock signal and a frequency division control signal and outputs a frequency division signal to the digital time converter; the digital time converter receives the frequency division signal, and combines the piecewise nonlinear predistortion function generated by the digital domain fitting module to carry out nonlinear correction on the digital domain fitting module to obtain an output signal and output the output signal. The phase-locked loop module acquires an output signal, extracts a phase error signal in the output signal and outputs the phase error signal to the digital domain fitting module; and the digital domain fitting module carries out nonlinear fitting in the digital domain according to the phase error signal and the multi-bit signal from the control unit to obtain a piecewise nonlinear predistortion function.
According to the invention, the phase error signal in the output signal of the digital time converter is extracted by using the phase-locked loop module, the digital time converter carries out nonlinear fitting in the digital domain by using the digital domain fitting module to obtain the piecewise nonlinear predistortion function, and the digital time converter carries out nonlinear correction on the digital time converter based on the piecewise nonlinear predistortion function, so that the problem that the open-loop fractional frequency divider cannot stably work under various environments and cannot generate high-quality clock signals is solved, and the quality of the output signal of the open-loop fractional frequency divider is greatly improved.
In addition, the open-loop fractional frequency divider provided by the invention does not need any prior information about circuit nonlinearity in the nonlinear correction process, and the complexity of nonlinear correction operation is effectively reduced. Meanwhile, because the nonlinear correction is performed by adopting a digital algorithm in a digital domain, a great deal of performance improvement can be obtained at the cost of smaller power consumption and area, and the method has higher practicability.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of an embodiment of a preferred open-loop fractional divider supporting nonlinear correction;
FIG. 2 is a schematic diagram of a preferred configuration of a PLL module according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a preferred structure of the digital domain fitting module INL Cali according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The open-loop fractional frequency divider supporting nonlinear correction provided by the invention has the advantages that the complexity of nonlinear correction operation is reduced while the generation of high-quality clock signals is ensured with smaller power consumption and area. The open-loop fractional divider supporting nonlinear correction includes: a multi-modulus divider, a digital-to-time converter, a digital domain fitting module, and a phase-locked loop module. The multi-mode frequency divider is connected with the digital time converter; the digital time converter is respectively connected with the digital domain fitting module and the phase-locked loop module.
The multi-mode frequency divider receives a reference clock signal and a frequency division control signal and outputs a frequency division signal to the digital time converter; the digital time converter receives the frequency division signal, and combines the piecewise nonlinear predistortion function generated by the digital domain fitting module to carry out nonlinear correction on the digital domain fitting module to obtain an output signal and output the output signal. And the digital domain fitting module carries out nonlinear fitting in the digital domain according to the phase error signal and the multi-bit signal from the control unit to obtain a piecewise nonlinear predistortion function. The phase error signal comes from the phase-locked loop module, and the phase-locked loop module acquires the output signal of the digital time converter, extracts the phase error signal in the output signal of the digital time converter and outputs the extracted phase error signal to the digital domain fitting module.
For a better explanation and description of the structure of the open-loop fractional divider supporting nonlinear correction according to the present invention, referring to fig. 1, a schematic diagram of a preferred open-loop fractional divider supporting nonlinear correction according to an embodiment of the present invention is shown. The multimode divider MMD receives the reference clock signal REF in And a frequency division control signal (adder output directly below MMD frame in FIG. 1) to digital time converter DTC M And outputting the frequency division signal.
Digital time converter DTC M Receiving the frequency division signal, and carrying out nonlinear correction on the frequency division signal by combining a piecewise nonlinear predistortion function generated by the digital domain fitting module INL Cali to obtain an output signal REF mod And outputs the output.
As can be seen from the structure of fig. 1: phase-locked loop module PLL obtaining digital time converter DTC M Is of the output signal REF of (2) mod And extract the output signal REF mod The phase error signal of (a) is output to a digital domain fitting module INL Cali. The digital domain fitting module INL Cali performs a nonlinear fit in the digital domain to obtain a piecewise nonlinear predistortion function based on the phase error signal and a multi-bit signal from the control unit (the output of the DSM modulator, the lower left hand side of INL Cali in fig. 1).
Typically, the control unit (not shown in fig. 1) generates a frequency control word FCW comprising: frequency control word high bit signal FCW int And frequency control word low bit signal FCW frac 。
Wherein, the frequency control word low bit signal FCW frac The single bit signal and the multi-bit signal are generated after the DSM modulation by the DSM modulator. Wherein the multi-bit signal is output to the digital domain fitting module INL Cali to participate in subsequent operation, and the single-bit signal and the frequency control word high-bit signal FCW int Performs an addition operation (positive by MMD in FIG. 1)The adder at the lower part performs addition operation) to obtain the frequency division control signal.
In one possible embodiment, the phase-locked loop module comprises: a phase comparator, a digital filter, a digital controlled oscillator, and an integer divider; the phase comparator is connected with the digital filter, the integer frequency divider and the digital domain fitting module; the digital filter is connected with the numerical control oscillator; the numerical control oscillator is connected with the integer frequency divider.
Referring to fig. 2, a preferred structure of a PLL module according to an embodiment of the invention is shown. As can be seen from fig. 2: the phase comparator PCM receives the output signal REF mod And a spurious-free clock signal CKVD, generating a phase error signal PHE and outputting to the digital filter DLF and the digital domain fitting module INL Cali. The digital filter DLF filters the phase error signal PHE and outputs it to the digitally controlled oscillator DCO.
The digitally controlled oscillator DCO receives the filtered phase error signal and outputs the generated digitally controlled clock signal CKV to an integer divider (denoted N in fig. 1); the integer divider processes the digital clock signal CKV to generate a spurious-free clock signal CKVD, and outputs the spurious-free clock signal CKVD to the phase comparator PCM.
Due to the output signal REF mod Contains spurious components, so that it can be used to determine the spurious clock signal CKD and the output signal REF by means of a phase comparator PCM mod In such a way that a phase error signal PHE is obtained, which is multiplexed, one is output to the digital filter DLF and the other is output to the digital domain fitting module INL Cali. The phase error signal PHE has a value of either 0 or 1, and can be used for the subsequent operation of the digital domain fitting module INL Cali, and thus the digital time converter DTC M Is of the output signal REF of (2) mod Nonlinear correction is realized.
In one possible embodiment, for the digital domain fitting module INL Cali, it performs a segmentation process on the phase error signal to obtain a multi-segment correction coefficient; the digital domain fitting module INL Cali determines a target segment correction coefficient when nonlinear fitting is performed in a digital domain according to the multi-bit signal, wherein the target segment correction coefficient is any segment correction coefficient in the multi-segment correction coefficients; and finally, performing function operation by the digital domain fitting module INL Cali according to the phase error signal, the multi-bit signal and the correction coefficient of the target segment to obtain a piecewise nonlinear predistortion function.
Referring to FIG. 3, a preferred structural schematic of the digital domain fitting module INL Cali in an embodiment of the present invention is shown. The exemplary digital domain fitting module INL Cali shown in fig. 3 includes: a 0-factorial unit 10, a 1-factorial unit 20, a 2-factorial unit 30, a first adder 40, and a second adder 50.
As can be seen from the structure shown in fig. 3: the operation result of the 1-step multiplying unit 20 and the operation result of the 2-step multiplying unit 30 are added by the second adder 50, and output to the first adder 40; the first adder 40 adds the output of the second adder 50 to the result of the operation of the 0-factorization unit 10 to obtain a piecewise nonlinear predistortion function, illustrated in fig. 3 as D dcw Representing a piecewise nonlinear predistortion function.
Specifically, the 0 factorial unit 10 includes: a first multiplier (left multiplier in dashed box 10 of fig. 3), a second multiplier (right multiplier in dashed box 10 of fig. 3), and a first multiplexing unit (portion within the solid line box in dashed box 10 of fig. 3).
For the 0 factorial unit 10 there are: the first multiplier is used for generating a phase error signal PHE and a first preset coefficient K C Performing multiplication operation and outputting an operation result to a first multi-path selection unit; the first multiplexing unit is used for selecting the multiple bit signal Q e Selecting an operation result of the correction coefficient of the corresponding target segment and outputting the operation result to a second multiplier; the second multiplier outputs the operation result of the correction coefficient of the corresponding target segment as the operation result of the 0 th order multiplication unit 10 to the first adder 40.
The 1-step unit 20 and the 2-step unit 30 have the same structure as the 0-step unit. The 1 factorial unit 20 includes: a third multiplier (left multiplier in dashed box 20 of fig. 3), a fourth multiplier (right multiplier in dashed box 20 of fig. 3), and a second multiplexing unit (portion within the solid line box in dashed box 20 of fig. 3).
For the 1 factorial unit 20 there are: the third multiplier multiplies the phase error signal PHE and the multi-bit signal Q e A second preset coefficient K B Performing multiplication operation and outputting an operation result to a second multipath selection unit; the second multiplexing unit is used for receiving the multi-bit signal Q e Selecting an operation result of the correction coefficient of the corresponding target segment and outputting the operation result to the fourth multiplier 50; fourth multiplier for multibit signal Q e And the operation result of the correction coefficient of the corresponding target segment are multiplied, and the multiplication result is output to the second adder 50 as the operation result of the 1-th order multiplication unit 20.
The 2 factorial unit 30 includes: a fifth multiplier (left multiplier in dashed box 30 of fig. 3), a sixth multiplier (right multiplier in dashed box 30 of fig. 3), and a third multiplexing unit (portion within the solid line box in dashed box 30 of fig. 3).
For the 2 factorial unit 30 there are: fifth multiplier multiplies the phase error signal PHE, the power signal Q of the multi-bit signal e 2 A third preset coefficient K A Performing multiplication operation and outputting an operation result to a third multi-path selection unit; the third multiplexing unit is based on the multi-bit signal Q e Selecting an operation result of the correction coefficient of the corresponding target segment and outputting the operation result to a sixth multiplier; the sixth multiplier multiplies the multiple bit signal by the Q e 2 And the operation result of the correction coefficient of the corresponding target segment are multiplied, and the multiplication result is output to the second adder 50 as the operation result of the 2-step multiplying unit 30.
By the method, the digital domain fitting module INL Cali realizes the function of the phase error signal PHE and the multi-bit signal Q e And the target segment correction coefficient is subjected to function operation to obtain the function of the piecewise nonlinear predistortion function.
Based on the above-mentioned open loop fractional frequency divider supporting nonlinear correction, the embodiment of the invention further provides a system on a chip, which includes: an open loop fractional divider supporting nonlinear correction as claimed in any one of the preceding claims.
Based on the above-mentioned open-loop fractional divider supporting nonlinear correction, the embodiment of the invention further provides an electronic device, which includes: an open loop fractional divider supporting nonlinear correction as claimed in any one of the preceding claims.
In summary, the open-loop fractional divider supporting nonlinear correction of the present invention includes: a multi-modulus divider, a digital-to-time converter, a digital domain fitting module, and a phase-locked loop module. The multi-mode frequency divider is connected with the digital time converter; the digital time converter is respectively connected with the digital domain fitting module and the phase-locked loop module.
The multi-mode frequency divider receives a reference clock signal and a frequency division control signal and outputs a frequency division signal to the digital time converter; the digital time converter receives the frequency division signal, and combines the piecewise nonlinear predistortion function generated by the digital domain fitting module to carry out nonlinear correction on the digital domain fitting module to obtain an output signal and output the output signal. The phase-locked loop module acquires an output signal, extracts a phase error signal in the output signal and outputs the phase error signal to the digital domain fitting module; and the digital domain fitting module carries out nonlinear fitting in the digital domain according to the phase error signal and the multi-bit signal from the control unit to obtain a piecewise nonlinear predistortion function.
According to the invention, the phase error signal in the output signal of the digital time converter is extracted by using the phase-locked loop module, the digital time converter carries out nonlinear fitting in the digital domain by using the digital domain fitting module to obtain the piecewise nonlinear predistortion function, and the digital time converter carries out nonlinear correction on the digital time converter based on the piecewise nonlinear predistortion function, so that the problem that the open-loop fractional frequency divider cannot stably work under various environments and cannot generate high-quality clock signals is solved, and the quality of the output signal of the open-loop fractional frequency divider is greatly improved.
In addition, the open-loop fractional frequency divider provided by the invention does not need any prior information about circuit nonlinearity in the nonlinear correction process, and the complexity of nonlinear correction operation is effectively reduced. Meanwhile, because the nonlinear correction is performed by adopting a digital algorithm in a digital domain, a great deal of performance improvement can be obtained at the cost of smaller power consumption and area, and the method has higher practicability.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. An open-loop fractional divider supporting nonlinear correction, the open-loop fractional divider comprising: the device comprises a multi-modulus frequency divider, a digital time converter, a digital domain fitting module and a phase-locked loop module;
the multi-mode frequency divider is connected with the digital time converter;
the digital time converter is respectively connected with the digital domain fitting module and the phase-locked loop module;
the multi-mode frequency divider receives a reference clock signal and a frequency division control signal and outputs a frequency division signal to the digital time converter;
the digital time converter receives the frequency division signal, performs nonlinear correction on the digital time converter by combining a piecewise nonlinear predistortion function generated by the digital domain fitting module, and obtains an output signal and outputs the output signal;
the phase-locked loop module acquires the output signal, extracts a phase error signal in the output signal and outputs the phase error signal to the digital domain fitting module;
and the digital domain fitting module carries out nonlinear fitting in a digital domain according to the phase error signal and the multi-bit signal from the control unit to obtain the piecewise nonlinear predistortion function.
2. The open-loop fractional divider of claim 1, wherein the phase-locked loop module comprises: a phase comparator, a digital filter, a digital controlled oscillator, and an integer divider;
the phase comparator is connected with the digital filter, the integer frequency divider and the digital domain fitting module;
the digital filter is connected with the numerical control oscillator;
the numerical control oscillator is connected with the integer frequency divider;
the phase comparator receives the output signal and the spurious-free clock signal, generates the phase error signal and outputs the phase error signal to the digital filter and the digital domain fitting module;
the digital filter filters the phase error signal and outputs the phase error signal to the numerical control oscillator;
the digital control oscillator receives the filtered phase error signal, and the generated digital control clock signal is output to the integer frequency divider;
and the integer frequency divider processes the numerical control clock signal to generate the spurious-free clock signal and outputs the spurious-free clock signal to the phase comparator.
3. The open loop fractional divider of claim 1 wherein the digital domain fitting module segments the phase error signal to obtain a multi-segment correction factor;
the digital domain fitting module determines a target segment correction coefficient when nonlinear fitting is performed in a digital domain according to the multi-bit signal, wherein the target segment correction coefficient is any segment correction coefficient in the multi-segment correction coefficients;
and the digital domain fitting module performs function operation according to the phase error signal, the multi-bit signal and the target segment correction coefficient to obtain the piecewise nonlinear predistortion function.
4. The open-loop fractional divider of claim 1, wherein the control unit generates a frequency control word comprising: a frequency control word high bit signal and a frequency control word low bit signal;
the low-bit signal of the frequency control word is modulated by a DSM modulator to generate a single-bit signal and the multi-bit signal;
and adding the single-bit signal and the high-bit signal of the frequency control word to obtain the frequency signal.
5. The open-loop fractional divider of claim 3, wherein the digital domain fitting module comprises: a 0-th factorial unit, a 1-th factorial unit, a 2-th factorial unit, a first adder and a second adder;
the operation result of the 1-order multiplication unit and the operation result of the 2-order multiplication unit are added through the second adder and output to the first adder;
and the first adder adds the output result of the second adder and the operation result of the 0-th order multiplication unit to obtain the piecewise nonlinear predistortion function.
6. The open-loop fractional divider of claim 5, wherein the 0 factorial unit comprises: a first multiplier, a second multiplier and a first multiplexing unit;
the first multiplier multiplies the phase error signal and a first preset coefficient and outputs the operation result to the first multipath selection unit;
the first multi-path selection unit selects an operation result corresponding to the correction coefficient of the target segment according to the multi-bit signal and outputs the operation result to the second multiplier;
the second multiplier outputs an operation result corresponding to the target segment correction coefficient as an operation result of the 0-th order multiplication unit to the first adder.
7. The open-loop fractional divider of claim 5, wherein the 1 factorial unit comprises: a third multiplier, a fourth multiplier, and a second multiplexing unit;
the third multiplier multiplies the phase error signal, the multi-bit signal and a second preset coefficient and outputs the operation result to the second multi-path selection unit;
the second multi-path selection unit selects an operation result corresponding to the correction coefficient of the target segment according to the multi-bit signal and outputs the operation result to the fourth multiplier;
the fourth multiplier multiplies the multi-bit signal by an operation result corresponding to the correction coefficient of the target segment, and outputs the operation result as an operation result of the 1-th order multiplication unit to the second adder.
8. The open-loop fractional divider of claim 5, wherein the 2-factorial unit comprises: a fifth multiplier, a sixth multiplier, and a third multiplexing unit;
the fifth multiplier multiplies the phase error signal, the square signal of the multi-bit signal and a third preset coefficient, and outputs the operation result to the third multiplexing unit;
the third multi-path selection unit selects an operation result corresponding to the correction coefficient of the target segment according to the multi-bit signal and outputs the operation result to the sixth multiplier;
the sixth multiplier multiplies the operation result of the square signal of the multi-bit signal and the correction coefficient corresponding to the target segment, and outputs the operation result as the operation result of the 2-th order multiplication unit to the second adder.
9. A system-on-chip, the system-on-chip comprising: an open-loop fractional divider supporting nonlinear correction as recited in any one of claims 1-8.
10. An electronic device, the electronic device comprising: an open-loop fractional divider supporting nonlinear correction as recited in any one of claims 1-8.
CN202310147020.0A 2023-02-09 2023-02-09 Open-loop fractional frequency divider supporting nonlinear correction, system on chip and electronic equipment Pending CN116131848A (en)

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