CN116131820A - All-digital programmable delay circuit with simple control - Google Patents
All-digital programmable delay circuit with simple control Download PDFInfo
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- CN116131820A CN116131820A CN202310384641.0A CN202310384641A CN116131820A CN 116131820 A CN116131820 A CN 116131820A CN 202310384641 A CN202310384641 A CN 202310384641A CN 116131820 A CN116131820 A CN 116131820A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an all-digital programmable delay circuit with simple control, which belongs to the technical field of delay circuits and comprises a delay line formed by cascading a plurality of delay units, wherein the delay unit is a programmable delay unit formed by four exclusive-OR gates; the invention adopts the all-digital circuit to realize the delay circuit, can be transplanted to another manufacturing process only by the layout and wiring in a digital mode, and adopts only 4 exclusive-OR gates to build one delay unit. Can be widely applied to the circuit design of the DDR, ONFI, eMMC, SDIO, PSRAM, QDR, RLDRAM physical layer.
Description
Technical Field
The invention relates to the technical field of delay circuits, in particular to an all-digital programmable delay circuit with simple control.
Background
Delay Locked Loops (DLLs) are an essential component of the master physical layer of source synchronous protocols such as DDR, ONFI, eMMC, SDIO, PSRAM, QDR, RLDRAM, LVDS, MIPI DPHY, where delay lines and delay cells and control circuitry are particularly important. The analog circuit is sensitive to power supply noise, has poor portability for different processes, and cannot be applied to scenes with severe area power consumption requirements. By adopting a high-frequency oversampling mode, a PLL with very high frequency is required, so that the design difficulty is increased, and higher power consumption is brought about by too high frequency.
Disclosure of Invention
The present invention is directed to an all-digital programmable delay circuit with simple control to solve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
an all-digital programmable delay circuit with simple control comprises a delay line formed by cascading a plurality of delay units, wherein the delay units are programmable delay units formed by four exclusive-OR gates.
As a further technical scheme of the invention: the delay unit comprises an exclusive-or gate U1, an exclusive-or gate U2, an exclusive-or gate U3 and an exclusive-or gate U4.
As a further technical scheme of the invention: one input end of the exclusive-or gate U1 is connected with the signal in and one input end of the exclusive-or gate U2, the other input end of the exclusive-or gate U1 is connected with one input end of the exclusive-or gate U4, the programming signal nTR and the signal o_en, the output end of the exclusive-or gate U1 outputs a signal pass, the other input end of the exclusive-or gate U2 is connected with the output end of the exclusive-or gate U4, the output end of the exclusive-or gate U2 is connected with one input end of the exclusive-or gate U3, the other input end of the exclusive-or gate U3 is connected with the signal ret, the output end of the exclusive-or gate U3 outputs a signal out, and the other input end of the exclusive-or gate U4 is connected with the signal i_en.
As a further technical scheme of the invention: when the delay unit is at the first stage, the signal out is an output signal, the signal in is an input signal, and the signal pass is the signal in of the delay unit at the later stage; the signal ret is the signal out of the delay unit of the subsequent stage, the signal i_en is 1, and the signal o_en is the signal i_en of the delay unit of the subsequent stage.
As a further technical scheme of the invention: when the delay unit is the middle stage of the delay line, the signal IN is the signal PASS of the delay unit of the previous stage, the signal out is the signal ret of the delay unit of the previous stage, and the signal PASS is the signal IN of the delay unit of the next stage; the signal i_en is the signal out of the delay unit of the previous stage, the signal ret is the signal out of the delay unit of the next stage, and the signal o_en is the signal i_en of the delay unit of the next stage.
As a further technical scheme of the invention: when the delay unit is the last stage of the delay line, the signal in is the signal PASS of the delay unit of the previous stage, the signal out is the signal ret of the delay unit of the previous stage, and the signal PASS is the signal ret of the delay unit of the current stage; the signal i_en is the signal out of the delay unit of the previous stage, and the signal o_en is 0.
The full-digital programmable delay method with simple control adopts the delay circuit, and the specific method is as follows: the programming signal nTR is programmed first to achieve a programmable delay output for signal in, the main delay line is used in DDR, ONFI, eMMC, SDIO, PSRAM, QDR and RLDRAM physical layer circuits to measure the required number of stages for one clock cycle, this number is divided by 4, and the slave delay line is programmed to achieve a 1/4 cycle delay.
Compared with the prior art, the invention has the beneficial effects that: the invention adopts the all-digital circuit to realize the delay circuit, can be transplanted to another manufacturing process only by the layout and wiring in a digital mode, and adopts only 4 exclusive-OR gates to build one delay unit. Can be widely applied to the circuit design of the DDR, ONFI, eMMC, SDIO, PSRAM, QDR, RLDRAM physical layer.
Drawings
Fig. 1 is a schematic diagram of a structure of a delay unit;
fig. 2 is a schematic diagram of the overall structure of the system of the present invention.
Fig. 3 is a schematic diagram of internal conduction of the delay cell when ntr=1.
Fig. 4 is a schematic diagram of internal conduction of the delay cell when tr=0.
Fig. 5 is a schematic diagram of internal conduction of two cascaded delay cells.
Fig. 6 is a schematic diagram of the turn-on of the delay line when the nTR of the delay line is encoded with a single "0".
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In embodiment 1, referring to fig. 1-6, an all-digital programmable delay circuit with simple control includes a delay line formed by cascade connection of a plurality of delay cells, wherein the delay cells are programmable delay cells formed by four exclusive or gates.
The delay unit comprises an exclusive or gate U1, an exclusive or gate U2, an exclusive or gate U3 and an exclusive or gate U4. One input end of the exclusive-or gate U1 is connected with a signal in and one input end of the exclusive-or gate U2, the other input end of the exclusive-or gate U1 is connected with one input end of the exclusive-or gate U4, a programming signal nTR and a signal o_en, the output end of the exclusive-or gate U1 outputs a signal pass, the other input end of the exclusive-or gate U2 is connected with the output end of the exclusive-or gate U4, the output end of the exclusive-or gate U2 is connected with one input end of the exclusive-or gate U3, the other input end of the exclusive-or gate U3 is connected with a signal ret, the output end of the exclusive-or gate U3 outputs a signal out, and the other input end of the exclusive-or gate U4 is connected with a signal i_en.
When the delay unit is at the first stage, the signal out is an output signal, the signal in is an input signal, and the signal pass is the signal in of the delay unit at the later stage; the signal ret is the signal out of the delay unit of the subsequent stage, the signal i_en is 1, and the signal o_en is the signal i_en of the delay unit of the subsequent stage.
When the delay unit is the middle stage of the delay line, the signal IN is the signal PASS of the delay unit of the previous stage, the signal out is the signal ret of the delay unit of the previous stage, and the signal PASS is the signal IN of the delay unit of the next stage; the signal i_en is the signal out of the delay unit of the previous stage, the signal ret is the signal out of the delay unit of the next stage, and the signal o_en is the signal i_en of the delay unit of the next stage.
When the delay unit is the last stage of the delay line, the signal in is the signal PASS of the delay unit of the previous stage, the signal out is the signal ret of the delay unit of the previous stage, and the signal PASS is the signal ret of the delay unit of the current stage; the signal i_en is the signal out of the delay unit of the previous stage, and the signal o_en is 0.
The working principle is as follows: firstly, a basic delay unit shown in fig. 1 is constructed, the delay unit is composed of 4 exclusive-or gates, a plurality of delay units are cascaded to form a delay line shown in fig. 2, the pass output of the delay unit of the last stage is connected to the ret input, and the delay capacity of the delay unit can be selected from a standard cell library according to the delay time of the exclusive-or gates. The delay capability of the delay line can be adjusted by the delay size of the exclusive or gate and the number of stages of the delay cells.
As shown in fig. 3, when ntr=1, the exclusive or gate U1 is turned on, the signal in reaches pass through the delay of the exclusive or gate U1, if i_en=1, the output of the exclusive or gate U4 is 0, and the output of the exclusive or gate U2 is 1, so that the exclusive or gate U3 is turned on, and the ret signal is delayed to out (inverted) through the exclusive or gate U3. However, as shown in fig. 4, when tr=0, the signal in is blocked at the exclusive or gate U1, i2 is output as 1, the signal in flows to the exclusive or gate U4 through the delay of the exclusive or gate U2, and if ret=1, the exclusive or gate U4 is turned on, and the signal in reaches out through the delay of the exclusive or gate U4. As shown in fig. 5, two cascaded delay units, the pre-delay unit (j 0) nTR [ i-1] =0 and the post-delay unit (j 1) nTR [ i ] =1, the output of the exclusive or gate U6 is 0, the output of the exclusive or gate U7 is 1, that is, ret=1 of the delay unit j0, the signal in passes through the exclusive or gate U2, and the two-stage inversion of the exclusive or gate U4 reaches out.
As shown in fig. 6, the signal in is turned around by the delay unit of the stage having the one-bit "0" code, such as 11 … 110111, for example, where the signal in is 2D (n+1) for the delay of one xor gate, assuming that the delay of one xor gate is D, and the sequence number of 0 of the one-bit "0" code is N from the lowest order. Since the number of inverters in this loop is even, out is the delay of signal in and in phase.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (7)
1. An all-digital programmable delay circuit with simple control is characterized by comprising a delay line formed by cascading a plurality of delay units, wherein the delay units are programmable delay units formed by four exclusive-or gates.
2. An all-digital programmable delay circuit of claim 1 wherein said delay cells comprise exclusive or gate U1, exclusive or gate U2, exclusive or gate U3 and exclusive or gate U4.
3. The fully digital programmable delay circuit of claim 2, wherein one input of the exclusive or gate U1 is connected to the signal in and one input of the exclusive or gate U2, the other input of the exclusive or gate U1 is connected to one input of the exclusive or gate U4, the programming signal nTR and the signal o_en, the output of the exclusive or gate U1 outputs the signal pass, the other input of the exclusive or gate U2 is connected to the output of the exclusive or gate U4, the output of the exclusive or gate U2 is connected to one input of the exclusive or gate U3, the other input of the exclusive or gate U3 is connected to the signal ret, the output of the exclusive or gate U3 outputs the signal out, and the other input of the exclusive or gate U4 is connected to the signal i_en.
4. A simple control all-digital programmable delay circuit as claimed in claim 3 wherein when the delay unit is the first stage, the signal out is the output signal, the signal in is the input signal, and the signal pass is the signal in of the delay unit of the subsequent stage; the signal ret is the signal out of the delay unit of the subsequent stage, the signal i_en is 1, and the signal o_en is the signal i_en of the delay unit of the subsequent stage.
5. A fully digital programmable delay circuit of claim 3 wherein when the delay unit is an intermediate stage of the delay line, the signal IN is a signal PASS of a delay unit of a previous stage, the signal out is a signal ret of a delay unit of a previous stage, and the signal PASS is a signal IN of a delay unit of a subsequent stage; the signal i_en is the signal out of the delay unit of the previous stage, the signal ret is the signal out of the delay unit of the next stage, and the signal o_en is the signal i_en of the delay unit of the next stage.
6. The fully digital programmable delay circuit of claim 4 wherein when the delay unit is the last stage of the delay line, the signal in is the signal PASS of the delay unit of the previous stage, the signal out is the signal ret of the delay unit of the previous stage, and the signal PASS is the signal ret of the delay unit of the present stage; the signal i_en is the signal out of the delay unit of the previous stage, and the signal o_en is 0.
7. An all-digital programmable delay method with simple control, characterized in that the delay circuit according to any one of claims 1-6 is used, the specific method is as follows: the programming signal nTR is programmed first to achieve programmable delay output of signal in, the number of stages required for measuring one clock cycle is measured in DDR, ONFI, eMMC, SDIO, PSRAM, QDR and RLDRAM physical layer circuits using a master delay line, the number is divided by 4, and the slave delay line is programmed to achieve a 1/4 cycle delay.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310384641.0A CN116131820B (en) | 2023-04-12 | 2023-04-12 | All-digital programmable delay circuit with simple control |
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| CN202310384641.0A CN116131820B (en) | 2023-04-12 | 2023-04-12 | All-digital programmable delay circuit with simple control |
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| CN116131820A true CN116131820A (en) | 2023-05-16 |
| CN116131820B CN116131820B (en) | 2023-07-11 |
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Citations (10)
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| JPH01232823A (en) * | 1988-03-12 | 1989-09-18 | Iwatsu Electric Co Ltd | Variable digital delay circuit |
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-
2023
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| JPH01232823A (en) * | 1988-03-12 | 1989-09-18 | Iwatsu Electric Co Ltd | Variable digital delay circuit |
| US5239213A (en) * | 1990-04-30 | 1993-08-24 | Advanced Micro Devices, Inc. | Precision timing control programmable logic device |
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| CN208820751U (en) * | 2018-08-31 | 2019-05-03 | 天津大学 | A kind of narrow pulse generating circuit of low cost miniaturization |
| CN111835525A (en) * | 2020-06-24 | 2020-10-27 | 南京航空航天大学 | Configurable RO PUF based on FPGA |
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| CN116131820B (en) | 2023-07-11 |
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