CN116130510A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN116130510A
CN116130510A CN202211710947.2A CN202211710947A CN116130510A CN 116130510 A CN116130510 A CN 116130510A CN 202211710947 A CN202211710947 A CN 202211710947A CN 116130510 A CN116130510 A CN 116130510A
Authority
CN
China
Prior art keywords
silicon
layer
oxidized
oxide layer
silicon carbide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211710947.2A
Other languages
Chinese (zh)
Inventor
三重野文健
周永昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Feicheng Semiconductor Shanghai Co ltd
Original Assignee
Feicheng Semiconductor Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Feicheng Semiconductor Shanghai Co ltd filed Critical Feicheng Semiconductor Shanghai Co ltd
Priority to CN202211710947.2A priority Critical patent/CN116130510A/en
Publication of CN116130510A publication Critical patent/CN116130510A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a semiconductor substrate, wherein a grid groove is formed in the semiconductor substrate; forming a silicon-containing layer to be oxidized on the side wall and the bottom of the grid groove and the surface of the semiconductor substrate; oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer; and forming a gate layer filling the gate trench on the surface of the silicon-containing oxide layer. The application provides a semiconductor structure and a forming method thereof, wherein a grid dielectric layer is not directly formed through a deposition process, but a silicon-containing layer to be oxidized which is easy to oxidize is firstly formed, and then the silicon-containing layer to be oxidized is oxidized to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the grid dielectric layer, so that the performance and the reliability of a silicon carbide device with a trench grid structure can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
A silicon carbide device (SiC MOSFET with trench gate) with a trench gate structure is a semiconductor device that is distinguished from a conventional silicon substrate and horizontal channels. However, the current formation process for such silicon carbide devices with trench gate structures still has drawbacks, resulting in device performance and reliability not being guaranteed.
Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The present application provides a semiconductor structure and a method of forming the same that can improve the performance and reliability of a silicon carbide device having a trench gate structure.
One aspect of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein a grid groove is formed in the semiconductor substrate; forming a silicon-containing layer to be oxidized on the side wall and the bottom of the grid groove and the surface of the semiconductor substrate; oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer; and forming a gate layer filling the gate trench on the surface of the silicon-containing oxide layer.
In some embodiments of the present application, the silicon-containing layer to be oxidized comprises an amorphous silicon layer.
In some embodiments of the present application, the silicon-containing layer to be oxidized comprises an amorphous silicon carbide layer.
In some embodiments of the present application, the silicon-containing layer to be oxidized includes an amorphous silicon carbide layer and an amorphous silicon layer sequentially located on the side wall and the bottom of the gate trench and the surface of the semiconductor substrate.
In some embodiments of the present application, the amorphous silicon carbide layer has a molar ratio of silicon atoms to carbon atoms in the silicon carbide of greater than 50:50.
in some embodiments of the present application, before oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer, further comprising: the amorphous silicon layer and the amorphous silicon carbide layer are processed using an annealing process to convert the amorphous silicon layer and the amorphous silicon carbide layer into a crystalline silicon layer and a crystalline silicon carbide layer.
In some embodiments of the present application, the process parameters of the annealing process include: the temperature is raised from 25 degrees celsius to 700 to 800 degrees celsius over 1 hour, then maintained for 2 hours, and then lowered to 25 degrees celsius over 1 hour.
In some embodiments of the present application, the crystalline silicon layer is fully oxidized and the crystalline silicon carbide layer is partially or fully oxidized during oxidation of the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer.
In some embodiments of the present application, a method of oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer includes: and introducing oxidizing gas to perform oxidation reaction with the crystalline silicon layer and the crystalline silicon carbide layer at the temperature of 750 ℃ for less than 3 hours.
In some embodiments of the present application, the process of oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to a silicon-containing oxide layer and the annealing process are accomplished in the same reaction chamber.
In some embodiments of the present application, the oxidizing gas comprises NO during oxidation of the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer, the crystalline silicon layer is fully converted to a silicon oxide layer, and a portion of the crystalline silicon carbide layer is converted to a silicon oxynitride layer.
In some embodiments of the present application, after oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer, the gate trench sidewalls and bottom and the semiconductor substrate surface are in sequence a crystalline silicon carbide layer and a silicon-containing oxide layer comprising a silicon oxynitride layer and a silicon oxide layer in sequence on the crystalline silicon carbide surface.
In some embodiments of the present application, the crystalline silicon carbide layer has a thickness of 2 to 10 nanometers, the silicon oxynitride layer has a thickness of 10 to 20 nanometers, and the silicon oxide layer has a thickness of 20 to 100 nanometers after oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to a silicon-containing oxide layer.
In some embodiments of the present application, the thickness of the silicon-containing layer to be oxidized is 40 to 100 nanometers, the thickness of the amorphous silicon layer is 50 to 90 percent of the thickness of the silicon-containing layer to be oxidized, and the thickness of the amorphous silicon carbide layer is 10 to 50 percent of the thickness of the silicon-containing layer to be oxidized.
Another aspect of the present application also provides a semiconductor structure, comprising: a semiconductor substrate having a gate trench formed therein; the silicon-containing oxide layer is positioned on the side wall and the bottom of the gate groove and the surface of the semiconductor substrate, or the silicon-containing layer and the silicon-containing oxide layer to be oxidized are sequentially positioned on the side wall and the bottom of the gate groove and the surface of the semiconductor substrate; and the grid electrode layer is positioned on the surface of the silicon-containing oxide layer and fills the grid electrode groove.
In some embodiments of the present application, the silicon-containing oxide layer includes a silicon oxynitride layer and a silicon oxide layer that are located in sequence on the gate trench sidewalls and bottom and the semiconductor substrate surface.
In some embodiments of the present application, the thickness of the silicon-containing layer to be oxidized is 2 to 10 nanometers, the thickness of the silicon oxynitride layer is 10 to 20 nanometers, and the thickness of the silicon oxide layer is 20 to 100 nanometers.
In some embodiments of the present application, the silicon-containing layer to be oxidized comprises a crystalline silicon carbide layer having a molar ratio of silicon atoms to carbon atoms in silicon carbide of greater than 50:50.
the application provides a semiconductor structure and a forming method thereof, wherein a grid dielectric layer is not directly formed through a deposition process, but a silicon-containing layer to be oxidized which is easy to oxidize is firstly formed, and then the silicon-containing layer to be oxidized is oxidized to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the grid dielectric layer, so that the performance and the reliability of a silicon carbide device with a trench grid structure can be improved.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale.
Wherein:
fig. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present application;
fig. 2 to 6 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
Silicon carbide devices (SiC MOSFET with trench gate) with trench gate structures are expected to be converted from silicon IGBT (Insulated Gate Bipolar Transistor). However, the oxidation conditions are different due to the different carbon and silicon surfaces of the SiC surface. Therefore, how to form a high quality gate dielectric layer is a challenge.
In some methods, forming the channel on only one side of the trench gate avoids asymmetric oxidation to form an asymmetric gate dielectric layer, however this reduces the number of channels, which has an impact on device performance. In other methods, a gate dielectric layer is formed using a TEOS CVD and anneal process, but the TEOS material contains carbon, and free carbon atoms in the TEOS layer affect SiO during the anneal after deposition of the TEOS layer 2 SiC interface and interstitial site SiC bulk. The free carbon atoms act as a defect source that causes electrical faults, such as breakdown voltage drop and/or mobility drop, etc.
In summary, the above methods still have drawbacks. Based on the above, the present application provides a semiconductor structure and a forming method thereof, which do not directly form a gate dielectric layer through a deposition process, but form a silicon-containing layer to be oxidized which is easy to oxidize first, and oxidize the silicon-containing layer to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the gate dielectric layer, so that the performance and reliability of a silicon carbide device with a trench gate structure can be improved.
Fig. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present application.
An embodiment of the present application provides a method for forming a semiconductor structure, as shown in fig. 1, including:
step S1: providing a semiconductor substrate, wherein a grid groove is formed in the semiconductor substrate;
step S2: forming a silicon-containing layer to be oxidized on the side wall and the bottom of the grid groove and the surface of the semiconductor substrate;
step S3: oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer;
step S4: and forming a gate layer filling the gate trench on the surface of the silicon-containing oxide layer.
The application provides a semiconductor structure and a forming method thereof, wherein a grid dielectric layer is not directly formed through a deposition process, but a silicon-containing layer to be oxidized which is easy to oxidize is firstly formed, and then the silicon-containing layer to be oxidized is oxidized to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the grid dielectric layer, so that the performance and the reliability of a silicon carbide device with a trench grid structure can be improved.
Fig. 2 to 6 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application. The following describes a method for forming a semiconductor structure according to an embodiment of the present application in detail with reference to the accompanying drawings.
Referring to fig. 2, in step S1, a semiconductor substrate 100 is provided, and a gate trench 110 is formed in the semiconductor substrate 100.
In some embodiments of the present application, the semiconductor structure described herein is, for example, a silicon carbide device (SiC MOSFET with trench gate) having a trench gate structure.
In some embodiments of the present application, the semiconductor substrate 100 includes a silicon carbide substrate 101 and a silicon carbide epitaxial layer 102 on a surface of the silicon carbide substrate 101. The silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 may be doped. The doping type of the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are the same. The doping type of the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 may be set according to the type of the silicon carbide device.
In some embodiments of the present application, the silicon carbide epitaxial layer 102 has a gate trench 110 formed therein. The gate trench 110 is used to form a trench gate structure. The trench gate structure comprises a gate layer and a gate dielectric layer positioned on the side wall and the bottom of the gate layer.
In some embodiments of the present application, a source 103 is formed in the silicon carbide epitaxial layer 102 on at least one side of the gate trench 110. In the embodiment of the present application, the silicon carbide epitaxial layer 102 on both sides of the gate trench 110 is exemplified by the source 103 formed therein.
In some embodiments of the present application, the side of the silicon carbide substrate 101 opposite the silicon carbide epitaxial layer 102 is also provided with a drain metal 104.
It should be noted that the semiconductor structure described in the embodiments of the present application may further include other structures included in the silicon carbide device having the trench gate structure. The embodiments of the present application omit these structures for the sake of brevity only and are not intended to exclude these structures.
Referring to fig. 3, in step S2, a silicon-containing layer 120 to be oxidized is formed on the sidewall and bottom of the gate trench 110 and the surface of the semiconductor substrate 100.
In some embodiments of the present application, the silicon-containing layer 120 to be oxidized includes an amorphous silicon layer 122.
In some embodiments of the present application, the silicon-containing layer to be oxidized 120 includes an amorphous silicon carbide layer 121.
In some embodiments of the present application, the silicon-containing layer 120 to be oxidized includes an amorphous silicon carbide layer 121 and an amorphous silicon layer 122 sequentially located on the sidewall and bottom of the gate trench 110 and the surface of the semiconductor substrate 100.
That is, there are at least three embodiments of the silicon-containing layer 120 to be oxidized. I.e. comprising only amorphous silicon layer 122, only amorphous silicon carbide layer 121 and both amorphous silicon layer 122 and amorphous silicon carbide layer 121.
The silicon-containing layer 120 to be oxidized is used for oxidizing to form a gate dielectric layer, and a common material of the gate dielectric layer is, for example, silicon oxide, so that a silicon-containing material layer is required for oxidation, that is, the silicon-containing layer to be oxidized. The amorphous silicon carbide and the amorphous silicon are easier to oxidize to form the gate dielectric layer, so that the amorphous silicon carbide and the amorphous silicon are selected as oxidation materials. The embodiments of the present application will be described in further detail below only with the case of simultaneously including the amorphous silicon layer 122 and the amorphous silicon carbide layer 121.
In the technical scheme of the application, the gate dielectric layer is not directly formed through a traditional deposition process, but the silicon-containing layer 120 to be oxidized which is easy to oxidize is formed firstly, and then the silicon-containing layer 120 to be oxidized is oxidized to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the gate dielectric layer. The quality of the gate dielectric layer formed by the method is better than that of the gate dielectric layer formed by direct deposition, and the performance and the reliability of the silicon carbide device with the trench gate structure can be improved.
In some embodiments of the present application, when the silicon-containing layer 120 to be oxidized includes an amorphous silicon carbide layer 121 (whether including only the amorphous silicon carbide layer 121 or both the amorphous silicon carbide layer 122 and the amorphous silicon carbide layer 121), the molar ratio of silicon atoms and carbon atoms in the silicon carbide in the amorphous silicon carbide layer 121 is greater than 50:50. for example, the molar ratio of silicon atoms to carbon atoms may be 55: 45. 60: 40. 65:35 or 70:30, etc. Minimizing the carbon atom fraction in amorphous silicon carbide layer 121, where process allows, may reduce the impact of free carbon atoms on device performance. The atomic ratio in amorphous silicon carbide is better adjusted, which is also one reason for choosing amorphous silicon carbide to use.
In some embodiments of the present application, the thickness of the silicon-containing layer to be oxidized 120 is 40 to 100 nanometers, the thickness of the amorphous silicon layer 122 is 50% to 90% of the thickness of the silicon-containing layer to be oxidized 120, and the thickness of the amorphous silicon carbide layer 121 is 10% to 50% of the thickness of the silicon-containing layer to be oxidized 120. The thickness of the silicon-containing layer 120 to be oxidized, the thickness of the amorphous silicon layer 122 and the thickness of the amorphous silicon carbide layer 121 need to be set in combination with practical situations. For example, a suitable thickness ratio is set in conjunction with the difference in oxidation rates of amorphous silicon layer 122 and amorphous silicon carbide layer 121 to ensure that the overall oxidation rate is not too low, reducing process efficiency. For example, in combination with the actually required gate dielectric layer thickness, and the oxidized thickness of amorphous silicon layer 122 and the oxidized thickness of amorphous silicon carbide layer 121, a suitable thickness ratio is set such that the total oxidized thickness of amorphous silicon layer 122 and amorphous silicon carbide layer 121 is the desired gate dielectric layer thickness.
In some embodiments of the present application, the methods of forming the amorphous silicon layer 122 and the amorphous silicon carbide layer 121 include LPCVD or ALD, and the like. In forming the amorphous silicon carbide layer 121, the molar ratio of silicon atoms to carbon atoms in silicon carbide in the amorphous silicon carbide layer 121 can be controlled by controlling the flow rates of the carbon source and the silicon source.
Referring to fig. 4, in some embodiments of the present application, before oxidizing the silicon-containing layer to be oxidized 120 to convert at least a portion of the silicon-containing layer to be oxidized 120 into a silicon-containing oxide layer, further comprises: the amorphous silicon layer 122 and the amorphous silicon carbide layer 121 are treated using an annealing process to convert the amorphous silicon layer 122 and the amorphous silicon carbide layer 121 into a crystalline silicon layer 132 and a crystalline silicon carbide layer 131. After the annealing process is performed, the crystalline silicon layer 132 and the crystalline silicon carbide layer 131 form the silicon-containing layer 120 to be oxidized.
In some embodiments of the present application, the process parameters of the annealing process include: the temperature is raised from 25 degrees celsius to 700 to 800 degrees celsius over 1 hour, then maintained for 2 hours, and then lowered to 25 degrees celsius over 1 hour.
Referring to fig. 5, in step S3, the silicon-containing layer to be oxidized 120 is oxidized to convert at least a portion of the silicon-containing layer to be oxidized 120 into a silicon-containing oxide layer 140.
In some embodiments of the present application, the process of oxidizing the silicon-containing layer to be oxidized 120 to convert at least a portion of the silicon-containing layer to be oxidized 120 to a silicon-containing oxide layer 140 and the annealing process are accomplished in the same reaction chamber.
In some embodiments of the present application, the crystalline silicon layer 132 is fully oxidized and the crystalline silicon carbide layer 131 is partially or fully oxidized during oxidation of the silicon-containing layer to be oxidized 120 to convert at least a portion of the silicon-containing layer to be oxidized 120 to a silicon-containing oxide layer 140. The embodiment of the present application exemplifies only that the crystalline silicon carbide layer 131 is partially oxidized.
In some embodiments of the present application, a method of oxidizing the silicon-containing layer to be oxidized 120 to convert at least a portion of the silicon-containing layer to be oxidized 120 to a silicon-containing oxide layer 140 includes: and introducing oxidizing gas to perform oxidation reaction with the crystalline silicon layer 132 and the crystalline silicon carbide layer 131 at a temperature of 750 ℃ for less than 3 hours.
In some embodiments of the present application, in oxidizing the silicon-containing layer to be oxidized 120 to convert at least a portion of the silicon-containing layer to be oxidized 120 to a silicon-containing oxide layer 140, the oxidizing gas comprises NO, the crystalline silicon layer 132 is all oxidized to a silicon oxide layer 142, and a portion of the crystalline silicon carbide layer 131 is oxidized to a silicon oxynitride layer 141. The silicon oxynitride layer 141 and the silicon oxide layer 142 constitute a gate dielectric layer. A part of the crystalline silicon carbide layer 131 that is oxidized may be entirely formed with the silicon oxynitride layer 141, or may be partially formed with the silicon oxynitride layer 141 and partially formed with the silicon oxide layer 142. Specifically, it may be set according to the desired thickness of the silicon oxynitride layer 141 and the silicon oxide layer 142, or the like.
In some embodiments of the present application, after oxidizing the silicon-containing layer 120 to be oxidized to convert at least a portion of the silicon-containing layer 120 to be oxidized to a silicon-containing oxide layer 140, the gate trench sidewalls and bottom and the semiconductor substrate surface are in turn a crystalline silicon carbide layer 131 and a silicon-containing oxide layer 140, the silicon-containing oxide layer 140 comprising a silicon oxynitride layer 141 and a silicon oxide layer 142 in turn on the crystalline silicon carbide surface 131.
In some embodiments of the present application, after oxidizing the silicon-containing layer to be oxidized 120 to convert at least a portion of the silicon-containing layer to be oxidized 120 into the silicon-containing oxide layer 140, the thickness of the crystalline silicon carbide layer 131 remains from 2 to 10 nm, the thickness of the silicon oxynitride layer 141 is from 10 to 20 nm, and the thickness of the silicon oxide layer 142 is from 20 to 100 nm.
In the technical scheme of the application, the amorphous silicon layer 122 and the amorphous silicon carbide layer 121 are simultaneously adopted as the silicon-containing layer 120 to be oxidized, and the thickness of the amorphous silicon layer 122 is reduced under the condition that the thickness of the silicon-containing layer 120 to be oxidized is certain, so that the amorphous silicon layer 122 can be ensured to be completely oxidized; the thickness of the amorphous silicon carbide layer 121 is also reduced, so that the influence of carbon atoms on the quality of the gate dielectric layer is reduced, and the amorphous silicon carbide layer 121 is partially oxidized, so that the influence of carbon atoms on the quality of the gate dielectric layer during oxidation is further reduced.
In other embodiments of the present application, when the silicon-containing layer 120 to be oxidized includes only the amorphous silicon layer 122, the amorphous silicon layer 122 is completely oxidized to form a silicon oxynitride layer and a silicon oxide layer. In this case, since there is only a single film layer, the control requirement on the oxidation process is low, but it is necessary to ensure that the amorphous silicon layer 122 is completely oxidized, so as to prevent the residual silicon from being located between the gate dielectric layer and the silicon carbide epitaxial layer, which would affect the silicon carbide device.
In other embodiments of the present application, when the silicon-containing layer 120 to be oxidized includes only the amorphous silicon carbide layer 121, since there is only a single film layer, the control requirement on the oxidation process is lower, but the carbon atom weight is more, so that it is difficult to ensure that the carbon atom does not affect the quality of the gate dielectric layer during oxidation.
Referring to fig. 6, in step S4, a gate layer 150 is formed on the surface of the silicon-containing oxide layer 140 to fill the gate trench 110.
In some embodiments of the present application, the material of the gate layer 150 comprises polysilicon. The method of forming the gate layer 150 includes a chemical vapor deposition process or a physical vapor deposition process, etc.
The application provides a semiconductor structure and a forming method thereof, wherein a grid dielectric layer is not directly formed through a deposition process, but a silicon-containing layer to be oxidized which is easy to oxidize is firstly formed, and then the silicon-containing layer to be oxidized is oxidized to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the grid dielectric layer, so that the performance and the reliability of a silicon carbide device with a trench grid structure can be improved.
Embodiments of the present application also provide a semiconductor structure, as shown with reference to fig. 6, including: a semiconductor substrate 100, in which a gate trench is formed in the semiconductor substrate 100; the silicon-containing oxide layer 140 is positioned on the side wall and the bottom of the gate trench and the surface of the semiconductor substrate, or the silicon-containing layer and the silicon-containing oxide layer 140 to be oxidized are sequentially positioned on the side wall and the bottom of the gate trench and the surface of the semiconductor substrate; and a gate layer 150 on the surface of the silicon-containing oxide layer 140 and filling the gate trench.
In some embodiments of the present application, the semiconductor structure described herein is, for example, a silicon carbide device (SiC MOSFET with trench gate) having a trench gate structure.
In some embodiments of the present application, the semiconductor substrate 100 includes a silicon carbide substrate 101 and a silicon carbide epitaxial layer 102 on a surface of the silicon carbide substrate 101. The silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 may be doped. The doping type of the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are the same. The doping type of the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 may be set according to the type of the silicon carbide device.
In some embodiments of the present application, the silicon carbide epitaxial layer 102 has a gate trench 110 formed therein. The gate trench 110 is used to form a trench gate structure. The trench gate structure comprises a gate layer and a gate dielectric layer positioned on the side wall and the bottom of the gate layer.
In some embodiments of the present application, a source 103 is formed in the silicon carbide epitaxial layer 102 on at least one side of the gate trench 110. In the embodiment of the present application, the silicon carbide epitaxial layer 102 on both sides of the gate trench 110 is exemplified by the source 103 formed therein.
In some embodiments of the present application, the side of the silicon carbide substrate 101 opposite the silicon carbide epitaxial layer 102 is also provided with a drain metal 104.
It should be noted that the semiconductor structure described in the embodiments of the present application may further include other structures included in the silicon carbide device having the trench gate structure. The embodiments of the present application omit these structures for the sake of brevity only and are not intended to exclude these structures.
With continued reference to fig. 6, a silicon-containing oxide layer 140 is formed on the sidewalls and bottom of the gate trench 110 and the surface of the semiconductor substrate 100, or a silicon-containing layer to be oxidized and a silicon-containing oxide layer 140 are sequentially located on the sidewalls and bottom of the gate trench and the surface of the semiconductor substrate. That is, the sidewalls and bottom of the gate trench 110 and the surface of the semiconductor substrate 100 may include only the silicon-containing oxide layer 140, or may include both the silicon-containing layer to be oxidized and the silicon-containing oxide layer 140. Embodiments of the present application are merely exemplary of including both the silicon-containing layer to be oxidized and the silicon-containing oxide layer 140.
In some embodiments of the present application, the silicon-containing oxide layer 140 includes a silicon oxynitride layer 141 and a silicon oxide layer 142 that are sequentially located on the gate trench sidewalls and bottom and the semiconductor substrate surface.
In some embodiments of the present application, the thickness of the silicon-containing layer to be oxidized is 2 to 10 nanometers, the thickness of the silicon oxynitride layer 141 is 10 to 20 nanometers, and the thickness of the silicon oxide layer 142 is 20 to 100 nanometers.
In some embodiments of the present application, the silicon-containing layer to be oxidized includes a crystalline silicon carbide layer 131, and the molar ratio of silicon atoms to carbon atoms in silicon carbide in the crystalline silicon carbide layer 131 is greater than 50:50. for example, the molar ratio of silicon atoms to carbon atoms may be 55: 45. 60: 40. 65:35 or 70:30, etc.
With continued reference to fig. 6, a gate layer 150 is formed on the surface of the silicon-containing oxide layer 140 to fill the gate trench 110.
In some embodiments of the present application, the material of the gate layer 150 comprises polysilicon.
The application provides a semiconductor structure and a forming method thereof, wherein a grid dielectric layer is not directly formed through a deposition process, but a silicon-containing layer to be oxidized which is easy to oxidize is firstly formed, and then the silicon-containing layer to be oxidized is oxidized to form a silicon-containing oxide layer, wherein the silicon-containing oxide layer is used as the grid dielectric layer, so that the performance and the reliability of a silicon carbide device with a trench grid structure can be improved.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a grid groove is formed in the semiconductor substrate;
forming a silicon-containing layer to be oxidized on the side wall and the bottom of the grid groove and the surface of the semiconductor substrate;
oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer;
and forming a gate layer filling the gate trench on the surface of the silicon-containing oxide layer.
2. The method of forming a semiconductor structure of claim 1, wherein the silicon-containing layer to be oxidized comprises an amorphous silicon layer.
3. The method of forming a semiconductor structure of claim 1, wherein the silicon-containing layer to be oxidized comprises an amorphous silicon carbide layer.
4. The method of claim 1, wherein the silicon-containing layer to be oxidized comprises an amorphous silicon carbide layer and an amorphous silicon layer sequentially on the sidewalls and bottom of the gate trench and the surface of the semiconductor substrate.
5. The method of forming a semiconductor structure of claim 3 or 4, wherein the amorphous silicon carbide layer has a molar ratio of silicon atoms to carbon atoms in silicon carbide greater than 50:50.
6. the method of forming a semiconductor structure of claim 4, wherein oxidizing the silicon-containing layer to be oxidized further comprises, prior to converting at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer: the amorphous silicon layer and the amorphous silicon carbide layer are processed using an annealing process to convert the amorphous silicon layer and the amorphous silicon carbide layer into a crystalline silicon layer and a crystalline silicon carbide layer.
7. The method of forming a semiconductor structure of claim 6, wherein the process parameters of the annealing process comprise: the temperature is raised from 25 degrees celsius to 700 to 800 degrees celsius over 1 hour, then maintained for 2 hours, and then lowered to 25 degrees celsius over 1 hour.
8. The method of claim 6, wherein the crystalline silicon layer is fully oxidized and the crystalline silicon carbide layer is partially or fully oxidized during oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to a silicon-containing oxide layer.
9. The method of forming a semiconductor structure of claim 6, wherein oxidizing the silicon-containing layer to be oxidized converts at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer comprises: and introducing oxidizing gas to perform oxidation reaction with the crystalline silicon layer and the crystalline silicon carbide layer at the temperature of 750 ℃ for less than 3 hours.
10. The method of claim 9, wherein oxidizing the silicon-containing layer to be oxidized and converting at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer and the annealing are performed in the same reaction chamber.
11. The method of claim 9, wherein oxidizing the silicon-containing layer to be oxidized converts at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer, wherein the oxidizing gas comprises NO, wherein the crystalline silicon layer is completely converted to a silicon oxide layer, and wherein a portion of the crystalline silicon carbide layer is converted to a silicon oxynitride layer.
12. The method of claim 11, wherein after oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer, the gate trench sidewalls and bottom and the semiconductor substrate surface are a crystalline silicon carbide layer and a silicon-containing oxide layer in sequence, the silicon-containing oxide layer comprising a silicon oxynitride layer and a silicon oxide layer in sequence on the crystalline silicon carbide surface.
13. The method of claim 12, wherein after oxidizing the silicon-containing layer to be oxidized to convert at least a portion of the silicon-containing layer to be oxidized to a silicon-containing oxide layer, the crystalline silicon carbide layer has a thickness of 2 to 10 nanometers, the silicon oxynitride layer has a thickness of 10 to 20 nanometers, and the silicon oxide layer has a thickness of 20 to 100 nanometers.
14. The method of claim 4, wherein the thickness of the silicon-containing layer to be oxidized is 40 to 100 nanometers, the thickness of the amorphous silicon layer is 50 to 90 percent of the thickness of the silicon-containing layer to be oxidized, and the thickness of the amorphous silicon carbide layer is 10 to 50 percent of the thickness of the silicon-containing layer to be oxidized.
15. A semiconductor structure, comprising:
a semiconductor substrate having a gate trench formed therein;
the silicon-containing oxide layer is positioned on the side wall and the bottom of the gate groove and the surface of the semiconductor substrate, or the silicon-containing layer and the silicon-containing oxide layer to be oxidized are sequentially positioned on the side wall and the bottom of the gate groove and the surface of the semiconductor substrate;
and the grid electrode layer is positioned on the surface of the silicon-containing oxide layer and fills the grid electrode groove.
16. The semiconductor structure of claim 15, wherein the silicon-containing oxide layer comprises a silicon oxynitride layer and a silicon oxide layer located in sequence on the gate trench sidewalls and bottom and the semiconductor substrate surface.
17. The semiconductor structure of claim 16, wherein the silicon-containing layer to be oxidized has a thickness of 2 to 10 nanometers, the silicon oxynitride layer has a thickness of 10 to 20 nanometers, and the silicon oxide layer has a thickness of 20 to 100 nanometers.
18. The semiconductor structure of claim 15, wherein the silicon-containing layer to be oxidized comprises a crystalline silicon carbide layer having a molar ratio of silicon atoms to carbon atoms in silicon carbide of greater than 50:50.
CN202211710947.2A 2022-12-29 2022-12-29 Semiconductor structure and forming method thereof Pending CN116130510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211710947.2A CN116130510A (en) 2022-12-29 2022-12-29 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211710947.2A CN116130510A (en) 2022-12-29 2022-12-29 Semiconductor structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN116130510A true CN116130510A (en) 2023-05-16

Family

ID=86294970

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211710947.2A Pending CN116130510A (en) 2022-12-29 2022-12-29 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116130510A (en)

Similar Documents

Publication Publication Date Title
US7459365B2 (en) Method for fabricating a semiconductor component
JP4867171B2 (en) Manufacturing method of semiconductor device
US9117836B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
TWI311814B (en) Silicon carbide semiconductor device and method for producing the same
JP5100329B2 (en) Semiconductor device
JP4008860B2 (en) Manufacturing method of semiconductor device
JP5243671B1 (en) Semiconductor device and manufacturing method thereof
JP5638558B2 (en) Semiconductor device and manufacturing method thereof
JP4188637B2 (en) Semiconductor device
TWI502741B (en) Semiconductor device having high performance channel
JP2006066439A (en) Semiconductor device and its manufacturing method
JP2009266871A (en) Silicon carbide semiconductor device and method of manufacturing same
WO2016006341A1 (en) Semiconductor device and method for producing same
JP4842527B2 (en) Manufacturing method of semiconductor device
TW201133641A (en) Method for forming a thick bottom oxide (TBO) in a trench MOSFET
US20200335583A1 (en) Methods for forming device isolation for semiconductor applications
JP2005064520A (en) Trench type mos gate element having strained layer on trench side wall
JP5728153B2 (en) Manufacturing method of semiconductor device
JP5266996B2 (en) Semiconductor device manufacturing method and semiconductor device
EP3022772A2 (en) Enhanced gate dielectric for a field effect device with a trenched gate
JP6035763B2 (en) Method for forming gate oxide film and method for manufacturing silicon carbide semiconductor device
TW201237960A (en) Production method for semiconductor device
KR100634260B1 (en) Method of forming a thin layer and method of forming a semiconductor device using the same
JP2005236160A (en) Semiconductor device and method for manufacturing the same
CN116130510A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination