CN116125353A

CN116125353A - Error correction method for on-chip S parameter measurement system, electronic equipment and storage medium

Info

Publication number: CN116125353A
Application number: CN202211097162.2A
Authority: CN
Inventors: 霍晔; 王一帮; 梁法国; 徐森锋; 吴爱华; 刘晨; 栾鹏; 陈晓华; 孙静; 张立飞
Original assignee: CETC 13 Research Institute
Current assignee: CETC 13 Research Institute
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2023-05-16

Abstract

The application provides an on-chip S parameter measurement system error correction method, electronic equipment and a storage medium. The method comprises the following steps: acquiring a measured value of the on-chip load calibration piece, and repairing the on-chip load calibration piece based on a first predetermined relation; and then calibrating the on-chip S parameter system according to the corrected on-chip load calibration piece. And finally, correcting the crosstalk error of the on-chip S parameter measurement system. The method and the device can improve the measurement reliability of the on-chip S parameter measurement system.

Description

Error correction method for on-chip S parameter measurement system, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of slice S parameter technologies, and in particular, to an error correction method for a slice S parameter measurement system, an electronic device, and a storage medium.

Background

Before the on-chip S parameter measurement system used in the microelectronics industry is used, a proper calibration method is needed to calibrate the system, and the existing on-chip calibration mostly adopts an 8-team error model. The 8-team error model characterizes non-idealities such as system source/load matching, reflection/transmission tracking, directivity, isolation and the like, has high accuracy in the field of slice S parameters, coaxiality and waveguide fields, and is widely applied.

When calibrating an on-chip S parameter measurement system by an 8-team error model, calibration is usually performed directly by using the standard value of the load inductance. However, due to the difference of the pressing needle positions during measurement, the load inductance value also changes in real time, and calibration can have errors only by using the standard value of the load inductance, so that the crosstalk error correction of the slice S parameter measurement system is problematic.

Disclosure of Invention

The application provides an error correction method, electronic equipment and a storage medium of an on-chip S parameter measurement system, which are used for solving the problem that crosstalk error correction of the on-chip S parameter measurement system is problematic due to the fact that errors possibly exist when calibration is performed only by using a standard value of a load inductance.

In a first aspect, the present application provides a method for correcting errors in an on-chip S parameter measurement system, including:

acquiring a measured value of the on-chip load calibration piece, and calculating the current load inductance of the on-chip load calibration piece based on a first predetermined relation so as to correct the on-chip load calibration piece;

calibrating an uncalibrated on-chip S parameter measurement system based on the on-chip straight-through calibration piece, the on-chip reflection calibration piece and the corrected on-chip load calibration piece;

Simulating the crosstalk calibration piece to obtain a crosstalk S parameter;

measuring a crosstalk calibration piece by using the calibrated on-chip S parameter measurement system to obtain parallel S parameters; the parallel S parameters include crosstalk errors;

and determining the crosstalk error of the on-chip S parameter measurement system according to the crosstalk S parameter, the parallel S parameter and the conversion relation between the Y parameter and the S parameter, and correcting the on-chip S parameter system according to the crosstalk error.

In a second aspect, the present application provides an on-chip S parameter measurement system error correction apparatus, including:

the first acquisition module is used for acquiring the measured value of the short-circuit calibration piece;

the first calculation module is used for calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measured value of the on-chip short circuit calibration piece based on a first predetermined relation;

and the calibration module is used for calibrating the measured piece according to the current load inductance of the on-chip load calibration piece.

In a third aspect, the present application provides an electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor implementing the steps of the method for correcting systematic error in slice S parameter measurement system as described above in the first aspect or any one of the possible implementations of the first aspect when the computer program is executed.

In a fourth aspect, the present application provides a computer readable storage medium storing a computer program which when executed by a processor implements the steps of the method for correcting errors in a slice S parameter measurement system according to the first aspect or any one of the possible implementations of the first aspect.

The application provides an on-chip S parameter measurement system error correction method, electronic equipment and a storage medium, which take into account that the load inductance of an on-chip load calibration piece may change due to different pin pressing positions in the process of calibration, so that the measured value of an on-chip short circuit calibration piece is used for extracting the current load inductance of on-chip load calibration, then correcting the on-chip load calibration piece, then correcting the on-chip S parameter measurement system by using the corrected on-chip load calibration piece, and finally correcting crosstalk errors, thereby improving the measurement accuracy of the on-chip S parameter measurement system and further improving the measurement reliability of the on-chip S parameter measurement system.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is an 8-team error model provided by an embodiment of the present application;

FIG. 2 is an 8-team error model expressed in terms of ABCD parameters provided by an embodiment of the present application;

fig. 3 is a flowchart of an implementation of an error correction method of an on-chip S parameter measurement system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the relationship between ABCD parameters and voltage and current in the embodiment of the present application;

FIG. 5 is an equivalent circuit schematic of an on-chip load calibrator in an embodiment of the present application;

FIG. 6 is a measurement result of the S21 parameter provided in the embodiment of the present application;

FIG. 7 is a measurement result of the S11 parameter provided in the embodiment of the present application;

FIG. 8 is a cross-talk error model provided by an embodiment of the present application;

fig. 9 is a schematic structural diagram of an error correction device of an on-chip S parameter measurement system according to an embodiment of the present application;

fig. 10 is a schematic diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the following description will be made with reference to the accompanying drawings by way of specific embodiments. See fig. 1. An 8-team error model provided by embodiments of the present application is shown. As shown in fig. 1, the 8-team error characterizes source/load matching, reflection/transmission tracking, directivity, isolation, etc. imperfections in the slice S parameter measurement system, respectively. Has high accuracy in the field of sheet S parameter measurement, coaxiality and waveguide fields, and is widely applied. SOLT (Short-Open-Load-Threu), short-circuit Open-Load through-connection) calibration methods require accurate knowledge of the definition of four calibration pieces; the TRL (through-reflection-Line) calibration method has higher requirements on the load calibration piece, and the frequency coverage range of the TRL (through-reflection-Line) calibration method is not wide enough due to the fact that the TRL (through-reflection-Line) calibration method has only one transmission Line; the LRRM (Line-reflection-Match) calibration method has fewer requirements on the definition of the calibration piece, the inductance and capacitance of the two reflection calibration pieces are not required to be known, the theoretical delay is only required to be calculated, and the inductance in the load calibration piece is extracted in real time according to the probe position, so that the LRRM calibration method has higher accuracy and is widely applied.

Referring to FIG. 2, an 8-team error model expressed in terms of ABCD parameters provided by embodiments of the present application is shown. As shown in FIG. 2, the eight error models are generally represented by S parameters, and the error networks need to be cascaded in the actual solving process, and the error networks are represented by transfer parameters (ABCD) (the ABCD parameters and the S parameters have a one-to-one correspondence), so that the cascade calculation is facilitated. The conversion relation between the ABCD parameter and the S parameter is shown in the formula (1):

wherein, the liquid crystal display device comprises a liquid crystal display device,S ₁₁ 、S ₁₂ 、S ₂₁ 、S ₂₂ representing the S parameter.

The vector network analyzer is used as an on-chip S parameter measurement system and plays an important role in the field of on-chip S parameters. The process of calibrating the on-chip S parameter measurement system may be as follows:

SS01, measuring the on-chip load calibration piece by using an uncalibrated on-chip S parameter measurement system to obtain an initial on-chip load S parameter; measuring an on-chip short circuit calibration piece by using an uncalibrated on-chip S parameter measurement system to obtain an initial on-chip short circuit S parameter; and measuring the on-chip open-circuit calibration piece by using an uncalibrated on-chip S parameter measurement system to obtain the initial on-chip open-circuit S parameter. Wherein the load inductance of the on-chip load calibration member is a known standard value.

SS02, using the initial on-chip load S parameter, the initial on-chip short circuit S parameter, and the initial on-chip open circuit S parameter, calculates eight errors, namely: a is that ₁ /D ₁ 、B ₁ /D ₁ 、C ₁ /D ₁ 、A ₂ /D ₂ 、B ₂ /D ₂ 、C ₂ /D ₂ D (D) ₁ D ₂ 。

And SS03, calibrating the uncalibrated on-chip S parameter measurement system by using eight errors, thereby obtaining the calibrated on-chip S parameter measurement system.

In the actual calibration process, the on-chip short circuit calibration piece, the on-chip load calibration piece and the on-chip open circuit calibration piece may be affected due to different pin pressing positions during calibration, that is, the nominal value is not necessarily an actual value. And the influence of the needle pressing position on the on-chip short circuit calibration piece and the on-chip open circuit calibration piece is negligible through judgment. However, the influence on the load inductance of the on-chip load calibration member is large, the load inductances corresponding to different press needle positions are different, and under the condition that calibration is not performed, the measured member is directly measured based on the standard load inductance, so that the measurement is inaccurate, and the correction result of the crosstalk error of the system is possibly directly affected.

In order to solve the above-mentioned problems, an embodiment of the present application provides an error correction method for an on-chip S parameter measurement system, which is described in detail below with reference to the accompanying drawings. Referring to fig. 3, a flowchart of an implementation of an error correction method of an on-chip S parameter measurement system according to an embodiment of the present application is shown. As shown in fig. 3, an on-chip S parameter measurement system error correction method may include S101 to S105.

S101, obtaining a measured value of the on-chip load calibration member, and calculating the current load inductance of the on-chip load calibration member based on a first predetermined relation so as to correct the on-chip load calibration member.

The present load inductance of the on-chip load calibration member may be calculated based on a predetermined first relation from the load resistance value of the on-chip load calibration member and the measured value of the on-chip short circuit calibration member to correct the on-chip load calibration member. The on-chip open circuit calibration piece, the on-chip short circuit calibration piece and the on-chip load calibration piece can be respectively measured by using a vector network analyzer, and the measured value of the on-chip short circuit calibration piece is calculated according to the measured result.

For a two-port network, it includes a first port and a second port. Accordingly, the measurement of the on-chip shorting calibration piece may include: the on-chip short circuit calibration feature may be configured to measure a first short circuit at a first port and/or a second short circuit at a second port. The method can be specifically selected and used according to actual conditions.

For example, the process of obtaining a measurement of an on-chip open calibration piece may include:

s1011, measuring an on-chip load calibration piece, an on-chip open-circuit calibration piece and an on-chip short-circuit calibration piece by adopting an on-chip S parameter measurement system to obtain an on-chip load S parameter, an on-chip open-circuit S parameter and an on-chip short-circuit S parameter.

S1012, calculating initial eight errors of the on-chip S parameter measurement system according to the on-chip load S parameter, the on-chip open-circuit S parameter and the on-chip short-circuit S parameter.

S1013, calculating the measured value of the on-chip short circuit calibration member according to the initial eight errors.

Based on the existing mode, the measured value of the on-chip short circuit calibration piece can be obtained according to the initial eight errors. The embodiments of the present application are not described herein.

Alternatively, the load resistance value of the sheet load calibration member is a known standard value, and the load resistance value is affected by negligible influence in the actual measurement process. In order to further ensure the reliability of measurement, a digital multimeter can be used for measuring a load resistance measured value of the on-chip load calibration piece, and then the current load inductance of the load calibration piece is accurately calculated by utilizing the load resistance measured value, so that the calibration precision can be further improved.

The first relation may be expressed as formula (2), as follows:

wherein L is _load,short Representing the current load inductance of an on-chip load calibrator extracted with an on-chip short circuit calibrator, R _load Represents the load resistance value, real (Z _app,short ) Representing the real part of the measurement of the on-chip short-circuit calibration piece, imag (Z _app,short ) The imaginary part of the measured value representing the on-chip short circuit calibration piece.

S102, calibrating an uncalibrated on-chip S parameter measurement system based on the on-chip straight-through calibration piece, the on-chip reflection calibration piece and the corrected on-chip load calibration piece.

Measuring the on-chip straight-through calibration piece by using an uncalibrated on-chip S parameter measurement system to obtain on-chip straight-through S parameters; measuring the corrected on-chip load calibration piece by adopting an uncalibrated on-chip S parameter measurement system to obtain corrected on-chip load S parameters; measuring an on-chip reflection calibration piece by adopting an uncalibrated on-chip S parameter measurement system to obtain an on-chip reflection S parameter;

and determining eight errors measured by the uncalibrated on-chip S parameter measurement system according to the on-chip straight-through S parameter, the corrected on-chip load S parameter, the on-chip reflection S parameter and the corresponding relation between the transfer parameter and the S parameter, and calibrating the uncalibrated on-chip S parameter measurement system according to the eight errors to obtain the on-chip S parameter measurement system.

S103, simulating the crosstalk calibration piece to obtain crosstalk S parameters.

The crosstalk calibration piece has known isotropic properties, a simulation diagram can be obtained by simulating the crosstalk calibration piece, and the crosstalk S parameter can be obtained according to the simulation diagram. The simulation software may be three-dimensional electromagnetic field simulation software such as CST, HFSS, etc.

S104, measuring a crosstalk calibration piece by using the calibrated on-chip S parameter measurement system to obtain parallel S parameters; the parallel S-parameters include crosstalk errors.

In the actual measurement process, the crosstalk calibration piece and the crosstalk error are in a parallel connection relationship, so that the parallel S parameter can be obtained by measuring the crosstalk calibration piece comprising the crosstalk error by adopting the on-chip S parameter measurement system.

S105, determining a crosstalk error of the on-chip S parameter measurement system according to the crosstalk S parameter, the parallel S parameter and the conversion relation between the Y parameter and the S parameter, and correcting the on-chip S parameter system according to the crosstalk error.

The real parameters of the crosstalk calibration member can be obtained according to the crosstalk S parameters and can be expressed as Y _A From the parallel S-parameters, a term for the crosstalk calibration member including crosstalk errors can be obtained, which can be expressed as Y _T The crosstalk error Y of the on-chip S parameter measurement system can be obtained by subtracting the two _C . The computational expression may be Y _C ＝Y _T -Y _A 。

According to the embodiment of the application, the current load inductance of the on-chip load calibration piece is extracted by using the measured value of the on-chip short circuit calibration piece, so that crosstalk error correction is carried out on the on-chip S parameter measurement system, correction time can be shortened on the basis of ensuring correction accuracy, use efficiency can be improved, and reliability of the on-chip S parameter measurement system is further improved.

In some embodiments of the present application, the first relationship comprises at least one of;

the first on-chip short circuit relationship is:

wherein L is _load,short,1 Representing the utilization of on-chip shortagesCurrent load inductance of the on-chip load calibration piece extracted by the road calibration piece at the first port, R _1,load Represents the load resistance value, real (Z _1,app,short ) Representing the real part of the first short measurement of the on-chip short calibration piece at the first port, imag (Z _1,app,short ) Representing the imaginary part of the first short-circuit measurement value, w=2pi f, f representing the frequency of the on-chip S parameter measurement system;

the second on-chip short circuit relationship is:

wherein L is _load,short,2 Representing the current load inductance of the on-chip load calibrator extracted at the second port using the on-chip short circuit calibrator, R _2,load Represents the load resistance value of the on-chip load calibration member at the second port, real (Z _2,app,short ) Representing the real part of the second short measurement of the on-chip short calibration member at the second port, imag (Z _2,app,short ) Representing the imaginary part of the second short measurement.

The reasoning process of the first relation in the embodiment of the present application is given below: referring to fig. 4, a schematic diagram of ABCD parameters versus voltage and current in an embodiment of the present application is shown. Referring to fig. 5, an equivalent circuit schematic of an on-chip load calibration member in an embodiment of the present application is shown.

As shown in fig. 3, ABCD is a parameter indicative of voltage and current, by definition, when measured on a piece calibration piece, yields relationships (5) and (6).

Wherein Z is _1,A Representing the actual impedance value, Z, of the on-chip calibration piece at the first port _1,M Is shown inImpedance measurement, Z, of the sheet calibration member at the first port _2,A Representing the actual impedance value, Z, of the on-chip calibration piece at the first port _2,M Representing the impedance measurement of the on-chip calibration piece at the first port.

As shown in fig. 4, in the rational case, equation (7) can be obtained from equation (5) for the on-chip open calibration piece of the first port; equation (8) can be derived from equation (5) for the on-chip short circuit calibration piece of the first port. For an on-chip open calibration of the second port, equation (9) can be derived from equation (6); equation (10) can be derived from equation (6) for the on-chip short circuit calibration piece of the second port. The method comprises the following steps:

/>

wherein Z is _1,M,open Representing impedance measurements of an on-chip open-circuit calibrator at a first port, Z _1,M,short Representing the impedance measurement, Z, of the on-chip shorting calibration piece at the first port _2,M,open Representing impedance measurements at a second port of the on-chip open-circuit calibration member, Z _2,M,short Representing the impedance measurement, Z, of the on-chip shorting calibration piece at the second port _1,A,open Representing the actual impedance value, Z, of the on-chip open circuit calibrator at the first port _1,A,short Indicating the actual impedance value, Z, of the on-chip shorting calibration member at the first port _2,A,open Representing the actual impedance value, Z, of the on-chip open-circuit calibration piece at the second port _2,A,short Representing the actual impedance value of the on-chip shorting calibrator at the second port.The actual impedance value is known as the nominal impedance value.

From the formulas (5) and (6), formulas (11) and (12) are obtained as follows:

for the on-chip calibration piece of the first port,

there is a corresponding measurement +.>

The formula (13) can be obtained. On-chip calibration for the second port, +.>

There is a corresponding measurement +.>

Equation (14) can be obtained. The following are provided:

the ratio Q1 in the formula (15) can be obtained from the formulas (11) and (13), and the ratio Q2 in the formula (16) can be obtained from the formulas (12) and (14), as follows:

for the on-chip load calibrators of the first port and the second port, equations (17) and (18) are obtained from equations (15) and (16), respectively, as follows:

wherein Z is _1,app,load Representing the measurement of the on-chip load calibration member at the first port, Z _1,A,load Representing the actual value of the on-chip load calibrator at the first port, Z _2,app,load Representing the measured value of the on-chip load calibration member at the second port, Z _2,A,load Representing the actual value of the on-chip load calibrator at the second port.

The measured values of the on-chip load calibrators of the first port and the second port are shown in formulas (19) and (20), respectively, as follows:

Z _1,app,load ＝R _1,load +jwL _1,load (19)

Z _2,app,load ＝R _2,load +jwL _2,load (20)

The actual values of the on-chip load calibration member when the reference surface is in the straight-through middle are shown in formulas (18) and (19), and are as follows:

Z _1,A,load ＝R _1,load (21)

Z _2,A,load ＝R _2,load (22)

in the embodiment of the present application, the procedure for obtaining the first short-circuit relation (3) is as follows:

for the on-chip short circuit calibration piece of the first port, equation (23) is derived from equation (15), as follows:

when the reference plane is in the pass-through middle, the measurement of the on-chip short circuit calibration piece of the first port is expressed as formula (24), as follows:

Z _1,app,short ＝R _1,short +jwL _1,short (24)

wherein L is _1,short Representing the port inductance of the on-chip shorting calibrator at the first port.

The actual value of the on-chip short circuit calibration piece for the first port is expressed as equation (25), as follows:

Z _1,A,short ＝jwL _1,short (25)

and (3) making:

real(Z _1,app,short )＝R _1,short (26)

imag(Z _1,app,short )＝wL _1,short (27)

formulas (28) and (29) are obtained from formulas (17), (19) and formulas (23), (26), (27), as follows:

the first on-chip short-circuit relation (3) is obtained from equation (29), as follows:

in the embodiment of the present application, the procedure for obtaining the second short-circuit relation (4) is as follows:

for the second port on-chip short circuit calibration piece, equation (30) is derived from equation (16), as follows:

when the reference plane is in the pass-through middle, the measurement of the on-chip short circuit calibration piece of the second port is expressed as formula (31), as follows:

Z _2,app,short ＝R _2,short +jwL _2,short (31)

wherein L is _2,short Representing the port inductance of the on-chip shorting calibrator at the second port.

The actual value of the on-chip short circuit calibration piece for the second port is represented by equation (32), as follows:

Z _2,A,short ＝jwL _2,short (32)

And (3) making:

real(Z _2,app,short )＝R _2,short (33)

imag(Z _2,app,short )＝wL _2,short (34)

formulas (35) and (36) are obtained from formulas (18), (20) and formulas (30), (33), (34), as follows:

the second on-chip short-circuit relation (4) is obtained from equation (53), as follows:

in some embodiments of the present application, "calculating the current load inductance of the on-chip load calibration member" in S102 may include:

will L _load,short,1 Actual load inductance as on-chip load calibration, or L _load,short,2 Actual load inductance as on-chip load calibration, or calculate L _load,short,1 And L _load,short,2 And the average value is taken as the actual load inductance of the on-chip load calibration piece.

When the first relation includes only the first on-chip short-circuit relation, L may be _load,short,1 As the current load inductance of the on-chip load calibrator. When the first relationship includes only the second on-chip short-circuit relationship, L may be _load,short,2 As the current load inductance of the on-chip load calibrator. Calculating L when the first relation includes a first on-chip short circuit relation and a second on-chip short circuit relation _load,short,1 And L _load,short,2 And the average value is taken as the current load inductance of the on-chip load calibration piece.

According to the embodiment of the application, by providing at least three calculation modes for calculating the current load inductance of the on-chip load calibration piece, the calculation efficiency of a single relational expression is higher, the calculation accuracy of solving the average value is higher, and the actual situation can be specifically combined for selection.

In some embodiments of the present application, the on-chip short circuit calibration piece and the on-chip open circuit calibration piece may also be utilized to co-extract the current load inductance of the on-chip load calibration piece for greater accuracy. The specific process is as follows:

after obtaining the measurement of the on-chip open calibration piece, the method further comprises:

measurements of the on-chip open calibration piece are obtained.

The on-chip open-circuit calibration piece, the on-chip short-circuit calibration piece and the on-chip load calibration piece can be respectively measured by using a vector network analyzer, and the measured value of the on-chip open-circuit calibration piece is calculated according to the measured result.

For a two-port network, it includes a first port and a second port. Accordingly, the measurement of the on-chip open calibration piece may include: a first open measurement at the first port at the on-chip open calibration member, and/or a second open measurement at the second port at the on-chip open calibration member. The method can be specifically selected and used according to actual conditions.

Accordingly, "correcting the on-chip load calibration member based on the predetermined first relation" in S102 may include:

based on the first relation and a second relation which is preset, calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece, the measured value of the on-chip open circuit calibration piece and the measured value of the on-chip short circuit calibration piece, and correcting the on-chip load calibration piece according to the current load inductance.

The second relation may be expressed as formula (37) as follows:

wherein L is _load,open Representing the current load inductance of an on-chip load calibrator extracted with an on-chip open-circuit calibrator, R _load Represents the load resistance value, real (Z _app,open ) Representing the real part of the measurement of the on-chip open calibration member, imag (Z _app,open ) The imaginary part of the measurement value representing the on-chip open calibration piece, w=2pi f, f represents the frequency of the on-chip S parameter measurement system.

In some embodiments of the present application, the second relationship includes at least one of:

the first on-chip open-circuit relationship is:

wherein L is _load,open,1 Representing on-chip load calibration extracted at a first port using an on-chip open-circuit calibration pieceCurrent load inductance of the standard, R _1,load Represents the load resistance value, real (Z _1,app,open ) Representing the real part of the first open measurement of the on-chip open calibration member at the first port, imag (Z _1,app,open ) Representing the imaginary part of the first open measurement value, w=2pi f, f representing the frequency of the on-chip S parameter measurement system;

the second on-chip open-circuit relationship is:

wherein L is _load,open,2 Representing the current load inductance of the on-chip load calibrator extracted at the second port using the on-chip open-circuit calibrator, R _2,load Represents the load resistance value of the on-chip load calibration member at the second port, real (Z _2,app,open ) Representing the real part of the second open measurement of the on-chip open calibration member at the second port, imag (Z _2,app,open ) Representing the imaginary part of the second open measurement.

The reasoning process of the second relation in the embodiment of the present application is given below:

in an embodiment of the present application, the process of obtaining the first on-chip open relationship (38) is as follows:

for the on-chip open circuit calibration of the first port, equation (40) is derived from (15), as follows:

when the reference plane is in the pass-through middle, the measurement of the on-chip open calibration piece of the first port is expressed as formula (41), as follows:

wherein C is _01,open Representing the port capacitance of the on-chip open calibration member at the first port.

The actual value of the on-chip open calibration of the first port is represented by equation (42), as follows:

and (3) making:

real(Z _1,app,open )＝R _1,open (43)

formulas (45) and (46) are obtained from formulas (14), (16) and formulas (20), (40), (41), as follows:

the first on-chip open relation (3) is obtained from equation (46) as follows:

where w=2pi f, f represents frequency.

In the embodiment of the present application, the procedure for obtaining the second on-chip open relation (39) is as follows:

for the second port on-chip open calibration, equation (47) is derived from equation (16) as follows:

the on-chip open calibration measurement for the second port is expressed as equation (48) when the reference plane is in the pass-through middle, as follows:

Wherein C is _02,open Representing the port capacitance of the on-chip open-circuit calibration piece at the second port.

The actual value of the on-chip open calibration of the second port is represented by equation (49) as follows:

and (3) making:

real(Z _2,app,open )＝R _2,open (50)

formulas (52) and (53) are obtained from formulas (18), (20) and formulas (30), (33), (34), as follows:

the second on-chip open relation (39) is obtained from equation (53), as follows:

the above is a derivation process provided in the embodiments of the present application to obtain the first on-chip open relation (38) and the second on-chip open relation (39). The current load inductance of the on-chip load calibration member may be extracted according to equation (38) and/or equation (39).

According to the method and the device for calibrating the on-chip S parameter, the current load inductance of the on-chip load calibration piece is extracted through the first relational expression, namely the first on-chip open-circuit relational expression and the second on-chip open-circuit relational expression, so that the calculation is convenient and quick, and the calibration efficiency of the on-chip S parameter measurement system can be improved.

will be

Current load inductance as on-chip load calibration, or will +.>

Current load inductance as on-chip load calibration, or calculate L _load,open,1 、L _load,open,2 、L _load,short,1 And L _load,short,2 And the average value is taken as the current load inductance of the on-chip load calibration piece.

When the first relation includes only the first on-chip open relation and the second relation includes only the first on-chip short relation

As the current load inductance of the on-chip load calibrator.

When the first relation includes only the second on-chip open relation and the second relation includes only the second on-chip short relation, the method will

As the current load inductance of the on-chip load calibrator.

Calculating L when the first relation includes a first on-chip open relation and a second on-chip open relation, and the second relation includes a first on-chip short relation and a second on-chip open relation _load,open,1 、L _load,open,2 、L _load,short,1 And L _load,short,2 And take the average as the on-chip load calibrationCurrent load inductance of the piece.

Furthermore, it may further include: when the first relation includes only the first on-chip open relation and the second relation includes only the second on-chip short relation

As the current load inductance of the on-chip load calibrator. When the first relation includes only the second on-chip open relation and the second relation includes only the first on-chip short relation

As the current load inductance of the on-chip load calibrator. Specifically, the selection may be performed according to actual situations, and the embodiments of the present application are not described herein in detail.

In some embodiments of the present application, the load inductance calculated by the second relation may also be used as the current load inductance of the on-chip calibration piece. For example, L can be _load,open,1 Current load inductance as on-chip load calibration, or L _load,open,2 Current load inductance as on-chip load calibration, or to be

As the current load inductance of the on-chip load calibrator. Specifically, the selection can be performed according to actual conditions.

The load inductance has a frequency response as the frequency changes, and the average value of the inductance in the frequency band can reduce the influence introduced by the frequency response. Thus, in some embodiments of the present application, "calculating the current load inductance of the on-chip load calibration member" in S102 above may further include:

and taking an average value of the load inductances in the preset frequency band as the load inductance of the load calibration piece.

Namely:

wherein L is _oad Representing on-chip load calibration membersLoad inductance, L ₁ ，L ₂ ，......，L _n And representing the extraction value of the load inductance of each frequency point in the preset frequency band. The preset frequency band can be a frequency band above 2GHz, and can be specifically selected according to actual conditions.

According to the method and the device, the average value of the load inductance in the preset frequency band is calculated to serve as the current load inductance of the piece calibration piece, the influence of the pressing needle position on the influence of the piece load calibration piece is considered comprehensively, the calculation result is more accurate, and the measuring accuracy of the measured piece is further improved.

For example, referring to fig. 6, measurement results of S21 parameters provided in the embodiments of the present application are shown. Referring to fig. 7, a measurement result of the S11 parameter provided in the embodiment of the present application is shown.

The 10dB attenuator is selected as a measured piece, the load inductance value extracted by the method provided by the embodiment of the application and the LRRM calibration method of the existing method are used for calibrating the same on-chip S parameter measurement system in the frequency band of 100 MHz-67 GHz, the same 10dB attenuator is measured after calibration, the S parameter of the reference surface at the probe end is obtained, and the measurement results are compared.

As shown in fig. 6 and 5, in the drawings, 10db_wincal (S21)/10db_wincal (S11) represents a measurement result of WINCAL; 10dB_1 (S21)/10 dB_1 (S11) represents the measurement result of the on-chip open circuit calibration piece with the first port to extract the load inductance, namely the load inductance is: l (L) _load,open,1 The method comprises the steps of carrying out a first treatment on the surface of the 10dB_2 (S21)/10 dB_2 (S11) represents the measurement result of the on-chip short circuit calibration piece using the first port to extract the load inductance, namely the load inductance is: l (L) _load,short,1 The method comprises the steps of carrying out a first treatment on the surface of the 10dB_3 (S21)/10dB_3 (S11) represents that the on-chip open circuit calibration member and the on-chip short circuit calibration member of the first port are utilized to extract the measurement result of the load inductance, namely the load inductance is:

10dB_4 (S21)/10 dB_4 (S11) represents the measurement result of the on-chip open circuit calibration piece with the second port to extract the load inductance, namely the load inductance is: l (L) _load,open,2 The method comprises the steps of carrying out a first treatment on the surface of the 10dB_5 (S21)/10dB_5 (S11) represents the utilization of the second port atThe sheet short circuit calibration piece extracts a measurement result of the load inductance, namely the load inductance is: l (L) _load,short,2 The method comprises the steps of carrying out a first treatment on the surface of the 10dB_6 (S21)/10dB_6 (S11) represents that the on-chip open circuit calibration member and the on-chip short circuit calibration member of the second port are utilized to extract the measurement result of the load inductance, namely the load inductance is: />

10dB_7 (S21)/10 dB_7 (S11) represents the measurement result of the on-chip open circuit calibration piece using the first port and the second port to extract the load inductance, namely the load inductance is: l (L) _load,open,1 And L _load,open,2 Average value of (2); 10dB_8 (S21)/10 dB_8 (S11) represents the measurement result of the on-chip short circuit calibration piece using the first port and the second port to extract the load inductance, namely the load inductance is: l (L) _load,short,1 And L _load,short,2 Average value of (2);

as can be seen from the results of fig. 6 and 7: the method provided by the embodiment of the application has the maximum deviation of 0.15dB of transmission amplitude and the maximum deviation of 0.08 of reflection amplitude of the same 10dB attenuator as that measured by WINCAL software. The method for extracting the load inductance in real time is reasonable, and meets the requirements of on-chip S parameter calibration and test.

In some embodiments of the present application, the determining the crosstalk error of the on-chip S parameter measurement system according to the crosstalk S parameter, the parallel S parameter, and the conversion relationship between the Y parameter and the S parameter in S105 may include: converting the crosstalk S parameter into the crosstalk Y parameter by utilizing the conversion relation between the Y parameter and the S parameter; converting the parallel S parameter into a parallel Y parameter by utilizing the conversion relation between the Y parameter and the S parameter; and determining the crosstalk error of the calibrated on-chip S parameter measurement system according to the crosstalk Y parameter and the parallel Y parameter.

Optionally, a well-known conversion relationship exists between the Y parameter and the S parameter, so that the crosstalk S parameter is converted into the Y parameter, and the crosstalk Y parameter can be expressed as Y _A Converting the parallel S parameter into a parallel Y parameter, which may be expressed as Y _T And subtracting the parallel Y parameter from the crosstalk Y parameter to obtain the crosstalk error of the on-chip S parameter measurement system.

Exemplary, see FIG. 8, which illustrates the present inventionThe crosstalk error model provided by the present embodiments. As shown in FIG. 8, the crosstalk calibration member is in parallel connection with the crosstalk error, and they have the same voltage U as the input and the output ₁ And U ₂ Relation of currents (I ₁ And I ₂ ) For superposition, the parallel Y parameter is denoted Y _T Wherein:

on-chip S parameter measurement system crosstalk error Y _C Then, any measured piece can be measured, the measured S parameter is converted into Y parameter, and is recorded as Y ^DUT . The transfer Y matrix of the measured part is:

and finally obtaining the real S parameter of the measured piece.

In some embodiments of the invention, the crosstalk calibration member is a preset number;

simulating the crosstalk calibration member to obtain a crosstalk S parameter may include: respectively simulating the crosstalk calibration pieces with the preset number to obtain crosstalk S parameters of the corresponding crosstalk calibration pieces; the crosstalk calibration piece is measured by an on-chip S parameter measurement system to obtain parallel S parameters, and the method comprises the following steps: and respectively measuring a preset number of crosstalk calibration pieces by using an on-chip S parameter measurement system to obtain parallel S parameters of the corresponding crosstalk calibration pieces.

In some embodiments of the invention, after obtaining the crosstalk S parameter of the corresponding crosstalk calibration member and obtaining the parallel S parameter of the corresponding crosstalk calibration member, the method further comprises:

for each crosstalk calibration piece, determining a crosstalk error corresponding to the crosstalk calibration piece according to the crosstalk S parameter of the crosstalk calibration piece, the parallel S parameter of the crosstalk calibration piece and the conversion relation between the Y parameter and the S parameter;

and obtaining average crosstalk errors of the crosstalk errors corresponding to the crosstalk calibration pieces, taking the average crosstalk errors as the crosstalk errors of the on-chip S parameter measurement system, and correcting the on-chip S parameter system according to the crosstalk errors.

Alternatively, the crosstalk error obtained by simulating a plurality of crosstalk calibration pieces and measuring the crosstalk calibration pieces by using the on-chip S parameter measurement system is averaged, and the average value is used as the crosstalk error of the on-chip S parameter measurement system, so that the obtained crosstalk error is more accurate.

In the embodiments of the present application, neither the on-chip through calibration piece nor the on-chip reflection calibration piece are defined, and the on-chip load calibration piece is defined. The definition represents a constant value and the undefined represents an undefined value. For example, the defined on-chip load calibration piece is a standard parameter such as that for which the actual admittance value of the load standard is known, the undefined on-chip pass-through calibration piece is a standard parameter unknown, and the undefined on-chip reflection calibration piece is a relevant standard parameter unknown.

Alternatively, the pass-through definition generally has two definition modes, one is delay time, and the other is ps; the other is the insertion loss definition mode, namely how much dB of insertion loss is inserted at certain specific frequency points. The on-chip S measurement system has two ports for connection to on-chip through calibrators, on-chip load calibrators, or on-chip reflection calibrators, respectively. The measured through S parameter includes S ₁₁ 、S ₁₂ 、S ₂₁ And S is ₂₂ The measured S parameter of the load comprises S ₁₁ And S is ₂₂ The measured reflected S parameter includes S ₁₁ And S is ₂₂ 。

In some embodiments of the present invention, eight errors measured by an uncalibrated on-chip S parameter measurement system are determined according to the on-chip through S parameter, the corrected on-chip load S parameter, the on-chip reflection S parameter, and the correspondence between the transfer parameter and the S parameter, and the uncalibrated on-chip S parameter measurement system is calibrated according to the eight errors, including:

based on the corresponding relation between the transfer parameter and the S parameter, the on-chip direct S parameter and the corrected on-chip negativeOn-chip S parameter and on-chip reflection S parameter determination A ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Is a value of (2);

port interchange is carried out on the on-chip straight-through S parameter, the on-chip load S parameter and the on-chip reflection S parameter, and A is determined according to the result after the port interchange ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ Is a value of (2);

according to A ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Value of A ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ And D is a value of (2) ₁ D ₂ Is calibrated for an uncalibrated on-chip S parameter measurement system.

Optionally, the corresponding relationship between the transfer parameter and the S parameter, where the transfer parameter is a parameter expressed by voltage and current, and the relationship between the ABCD transfer parameter and the S parameter may be expressed as follows:

optionally, the port interchange is to interchange the results of the S parameters measured at the two ports of the slice S parameter measurement system, that is, the results after the port interchange include the interchanged slice through S parameter, the interchanged slice load S parameter, and the interchanged slice reflection S parameter. Determining A according to the result after port exchange ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ The value of (a) is determined according to the exchanged straight-through S parameter, the exchanged load S parameter and the exchanged reflection S parameter ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ Is a value of (2).

Optionally, embodiments of the present invention provideIs generally used for measuring passive devices, the passive devices generally have reciprocal properties, and D is calculated ₁ D ₂ The process of (2) is as follows:

a passive device is measured using an on-chip S parameter measurement system as follows: e (E) _DUT ＝E1*E _{A_DUT} *E2

Wherein E is _DUT Indicating the uncorrected measurement result of the measured piece E _{A_DUT} And representing the actual value of the measured piece by adopting an ABCD matrix.

Considering that passive devices are reciprocal, their ABCD matrix determinant is 1.

Thus, the following formula can be obtained: i E _DUT |＝|E1|*|E2|

Combining the above, D can be obtained ₁ D ₂ Modulus of D ₁ D ₂ The sign of (c) can be obtained by prior art techniques, e.g. in conformity with existing SOLR calibration methods, i.e. D ₁ D ₂ The values of (2) are all found.

In some embodiments of the invention, A is determined based on the correspondence of the transfer parameter to the S parameter, the on-chip pass-through S parameter, the on-chip load S parameter, and the on-chip reflection S parameter ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Comprises:

determining a straight-through original parameter matrix of an uncalibrated on-chip S parameter measurement system according to the corresponding relation between the straight-through S parameter and the transfer parameter and the S parameter, and determining a cascading relation according to the straight-through original parameter matrix;

determining A according to the cascade relation, on-chip load S parameter and on-chip reflection S parameter ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Is a value of (2).

Optionally, an undefined on-chip through calibration piece is measured by using an uncalibrated on-chip S parameter measurement system to obtain on-chip through S parameters, and then a through original parameter matrix is determined according to the on-chip through S parameters, so that a cascade relation exists.

In some embodiments of the invention, the on-chip pass-through alignment feature is one; the on-chip load calibration pieces are a group and comprise a first on-chip load calibration piece and a second on-chip load calibration piece; the on-chip reflection criteria are a set comprising a short circuit calibration feature and an open circuit calibration feature.

Optionally, under ideal conditions, under the condition that the load processing technology is consistent, the system calibration can be realized by only one undefined on-chip through calibration piece, one undefined on-chip reflection calibration piece and one defined on-chip load calibration piece, so that the test accuracy is improved, the test efficiency is improved, and the cost is reduced.

In some embodiments of the invention, the on-chip pass-through alignment feature is one; the on-chip load calibration pieces are a group and comprise a first on-chip load calibration piece and a second on-chip load calibration piece; the on-chip reflectance calibration elements are two groups, the first group of the on-chip reflectance calibration elements comprises two short circuit calibration elements, and the second group of the reflectance calibration elements comprises two open circuit calibration elements.

Optionally, in the embodiment of the present invention, an undefined on-chip through calibration piece, two undefined on-chip reflection calibration pieces, and one defined on-chip load calibration piece are measured by using an uncalibrated on-chip S parameter measurement system, so as to obtain corresponding raw data. Eight errors are calculated through the characteristics of cascade connection of the S parameters and the transfer matrix. The embodiment of the invention only needs to know the definition of the load calibration piece, can realize accurate measurement in the field of on-chip S parameter calibration and test, achieves better indexes, meets the commercial on-chip S parameter calibration and test work in the market, and has certain economic and social benefits.

In some embodiments of the invention, the method further comprises: constructing an admittance relation according to the load S parameter and on-chip load standard; constructing a first error network relation according to a first group of on-chip reflection standards; constructing a second error network relation according to a second set of on-chip reflection criteria; determining A according to the cascade relation, the load S parameter and the reflection S parameter ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Comprises:

according to the cascade relation, admittance relation, first error network relation and second error network relationDetermining A ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Is a value of (2);

wherein, the cascade relation formula is:

E _T ＝E ₁ E ₂

wherein, the liquid crystal display device comprises a liquid crystal display device,

the corresponding relation between the transfer parameter and the S parameter is as follows:

wherein E is ₁ First error network measured for uncalibrated on-chip S parameter system, E ₂ For a second error network of uncalibrated on-chip S-parameter system measurements, S ₁₁ 、S ₁₂ 、S ₂₁ 、S ₂₂ Is S parameter, A _T 、B _T 、C _T 、D _T Is a transfer parameter.

Alternatively, the on-chip load criterion defined by the embodiments of the present invention refers to the actual admittance measurement of the load criterion being known.

The first error network relationship is:

wherein Z is _i,M(j) Representing an impedance value, i being the i-th port, i=1 being the first port, i=2 being the second port, M being a reflection criterion, j being the j-th reflection criterion, j=1 being an open-circuit criterion, j=2 being a short-circuit criterion;

Calculating a first error parameter from the admittance relationship, the first error network relationship, and the second error network relationship, comprising:

for the first error network relation, let

x ₁ ＝A _T Z _2,M(1) -B _T +C _T Z _1,M(1) Z _2,M(2) -D _T Z _1,M(1)

y ₁ ＝2D _T -2C _T Z _2,M(1)

v ₁ ＝2A _T Z _1,M(1) Z _2,M(1) -2B _T Z _1,M(1)

For the second error network relation, let

x ₂ ＝A _T Z _2,M(2) -B _T +C _T Z _1,M(2) Z _2,M(2) -D _T Z _1,M(2)

y ₂ ＝2D _T -2C _T Z _2,M(2)

v ₂ ＝2A _T Z _1,M(2) Z _2,M(2) -2B _T Z _1,M(2)

Then:

alternatively, referring to fig. 2, the first network relation is a relation of a first error network E1 looking from the left toward the measured piece.

Alternatively, A may be obtained by calculating a first error network relationship ₁ /C ₁ Values of (B) ₁ /D ₁ The relation between the values of (A) and the admittance relation can be combined to obtain A ₁ /C ₁ Values of (B) ₁ /D ₁ The sum of the values of (C) ₁ /D ₁ Can be deduced from the relation between the values of A ₁ /D ₁ Values of (B) ₁ /D ₁ Is a value of (2).

Optionally, a first error network relation can be obtained by combining the admittance relation, the cascade relation, and the corresponding relation between the transfer parameter and the S parameter, and the a can be calculated by the first error network relation ₁ /D ₁ Values of (B) ₁ /D ₁ The sum of the values of (C) ₁ /D ₁ Is a value of (2).

In some embodiments of the present application, the "port exchanging the pass-through S parameter, the load S parameter, and the reflection S parameter" may include:

s in the S parameter of the load and the S parameter of the reflection ₁₁ Set to S ₂₂ ，S ₂₂ Set to S ₁₁ ；

Exchanging S parameters measured by two ports in the straight-through S parameters, wherein the exchanged straight-through S parameters are expressed as:

In some embodiments of the invention, the "determining A based on results after port swapping" described above ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ May include:

based on the result after the port exchange, calculating to obtain A in the same way as the first error parameter is calculated ₃ /D ₃ Values of (B) ₃ /D ₃ Values of (C) ₃ /D ₃ Is a value of (2);

according to A ₃ /D ₃ A value of (2),B ₃ /D ₃ Values of (C) ₃ /D ₃ Determining a transfer matrix of the second port after port interchange;

based on the transfer matrix of the second port, the ports are interchanged again, and A is determined ₂ /D ₂ Values of (B) ₂ /D ₂ The sum of the values of (C) ₂ /D ₂ Is a value of (2).

Exemplary, calculate A ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ The process of the values of (2) is as follows:

step one, for the on-chip reflection standard and the on-chip load standard, S measured by the first port ₁₁ Set to S ₂₂ S measured at the second port ₂₂ Set to S ₁₁ 。

And step two, exchanging the S parameter measured by the first port and the S parameter measured by the second port for the on-chip straight-through standard.

For the two-port pass-through standard, the S parameters were measured as:

exchanging the first port and the second port, wherein the S parameters after exchanging are as follows: />

/>

Step three, adopting and calculating A ₁ /D ₁ Values of (B) ₁ /D ₁ The sum of the values of (C) ₁ /D ₁ Calculate A in the same way as the value of (A) ₃ /D ₃ Values of (B) ₃ /D ₃ Values of (C) ₃ /D ₃ Is a value of (2).

In D ₃ Normalized E ₃ The transfer matrix is converted into S parameters as follows:

det (x) represents the value of the determinant.

Step four, converting the S parameter after port interchange (namely S parameter after interchange of the first port and the second port) into a transfer matrix, wherein the steps are as follows:

obtaining

While

Thus, A is calculated ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ Is a value of (2).

See FIG. 3E ₂ 、E3、E ₄ The relation between the two is:

the transition parameter definition is related to the direction of wave transmission (port order). E1 and E2 in FIG. 2 are both seen from left to right, transfer parameter E ₂ If seen from right to left, become E ₃ . Will E ₃ Where the port order is changed, i.e. seen from left to right, then becomes E ₄ 。E ₄ And E is ₂ A proportional relationship, which can be seen here as E ₂ ＝E ₄ 。

Based on the obtained A ₁ /D ₁ Values of (B) ₁ /D ₁ Values of (C) ₁ /D ₁ Value of A ₂ /D ₂ Values of (B) ₂ /D ₂ Values of (C) ₂ /D ₂ D calculated from the reciprocal properties of the passive device ₁ The sum of the values of D ₂ An uncalibrated on-chip S parameter measurement system may be calibrated.

The embodiment of the invention only needs to use two symmetrical unknown reflection standards, an unknown transmission line standard and a pair of known defined load standards. In view of leakage errors existing in microwave probes in chip systems above millimeter wave, circuits characterizing leakage are added to single port load standard circuit models.

The whole calibration process is divided into three parts:

first, the current load inductance of the on-chip load calibration piece is extracted by using the on-chip open-circuit calibration piece so as to calibrate the on-chip load calibration piece.

Secondly, obtaining a basic 8-term error model, namely respectively calculating 6-term basic error terms of the on-chip leakage system through two pairs of reflection standards and a pair of corrected load calibration pieces by adopting an ABCD matrix, then testing unknown two-port passive devices (including the reflection standards or the load standards or other passive devices) and obtaining residual error terms by utilizing the reciprocity characteristics of the unknown two-port passive devices;

and the second part is used for calculating and obtaining a crosstalk system error model by using the existing parallel crosstalk error model. Simulation verification is carried out on the solving algorithm. Compared with the existing commercial calibration method, the calibration piece and the passive attenuator validation of the 110GHz ceramic substrate are developed, the measurement result of the validation piece S11 is improved by 0.02, the test result of S21 is optimized by 1.7dB at maximum, and the information requirement on the definition of the calibration piece is less. Compared with the existing SOLR calibration method, the calibration can be realized without accurately knowing the accurate magnitude of the two sets of on-chip reflection standards, and meanwhile, if the processing technology is consistent, the calibration method can eliminate one set of on-chip reflection standards, thereby improving the test accuracy, improving the test efficiency and reducing the cost.

According to the embodiment of the application, firstly, the ratio of the measured value to the actual value is calculated according to the condition that the on-chip open circuit calibration piece or the on-chip short circuit calibration piece reference surface is in the straight-through middle. And then, calculating to obtain the load inductance value extracted in real time in the sheet S parameter calibration through the S parameter measurement value of the sheet open circuit calibration member, the sheet short circuit calibration member and the direct current resistance measurement value of the sheet load calibration member. Finally, the average value of the load inductance in the frequency-taking band reduces the influence introduced by the frequency response. The crosstalk error correction can be carried out, the accurate measurement of the measured piece can be realized, meanwhile, better indexes can be achieved, the on-chip S parameter calibration and test work can be satisfied, and certain economic and social benefits are achieved.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.

The following are device embodiments of the present application, for details not described in detail therein, reference may be made to the corresponding method embodiments described above.

Fig. 9 is a schematic structural diagram of an error correction device of an on-chip S parameter measurement system according to an embodiment of the present application, and for convenience of explanation, only a portion relevant to the embodiment of the present application is shown, which is described in detail below:

As shown in fig. 9, the in-slice S parameter measurement system error correction device 20 may include:

a first obtaining module 201, configured to obtain a measured value of the on-chip load calibration piece, and calculate a current load inductance of the on-chip load calibration piece based on a predetermined first relation, so as to correct the on-chip load calibration piece;

a first calibration module 202, configured to calibrate an uncalibrated on-chip S parameter measurement system based on the on-chip through calibration piece, the on-chip reflection calibration piece, and the corrected on-chip load calibration piece;

the simulation module 203 is configured to simulate the crosstalk calibration piece to obtain a crosstalk S parameter;

the measurement module 204 is configured to measure the crosstalk calibration piece by using the calibrated on-chip S parameter measurement system, so as to obtain a parallel S parameter; the parallel S parameters include crosstalk errors;

the second calibration module 205 is configured to determine a crosstalk error of the on-chip S parameter measurement system according to the crosstalk S parameter, the parallel S parameter, and a conversion relationship between the Y parameter and the S parameter, and correct the on-chip S parameter system according to the crosstalk error.

the first on-chip short circuit relationship is:

wherein L is _load,short,1 Representing the current load inductance of an on-chip load calibrator extracted at a first port using an on-chip short circuit calibrator, R _1,load Represents the load resistance value, real (Z _1,app,short ) Representing the real part of the first short measurement of the on-chip short calibration piece at the first port, imag (Z _1,app,short ) Representing the imaginary part of the first short-circuit measurement value, w=2pi f, f representing the frequency of the on-chip S parameter measurement system;

the second on-chip short circuit relationship is:

In some embodiments of the present application, the first computing module 202 may also be configured to compare L to _load,short,1 Actual load inductance as on-chip load calibration, or L _load,short,2 Actual load inductance as on-chip load calibration, or calculate L _load,short,1 And L _load,short,2 And the average value is taken as the actual load inductance of the on-chip load calibration piece.

In some embodiments of the present application, the apparatus 20 may further include:

the second acquisition module is used for acquiring the measured value of the on-chip open circuit calibration piece after acquiring the measured value of the on-chip open circuit calibration piece;

And the second calculation module is used for calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece, the measured value of the on-chip open circuit calibration piece and the measured value of the on-chip short circuit calibration piece based on the first relation and a second relation which is preset, and correcting the on-chip load calibration piece according to the current load inductance.

the first on-chip open-circuit relationship is:

wherein L is _load,open,1 Representing the current load inductance of an on-chip load calibrator extracted at a first port using an on-chip open-circuit calibrator, R _1,load Represents the load resistance value, real (Z _1,app,open ) Representing the real part of the first open measurement of the on-chip open calibration member at the first port, imag (Z _1,app,open ) Representing the imaginary part of the first open measurement value, w=2pi f, f representing the frequency of the on-chip S parameter measurement system;

the second on-chip open-circuit relationship is:

In some embodiments of the present application, the first acquisition module 201 may include:

the measuring unit is used for measuring the on-chip load calibration piece, the on-chip open-circuit calibration piece and the on-chip short-circuit calibration piece by adopting the on-chip S parameter measuring system to obtain on-chip load S parameters, on-chip open-circuit S parameters and on-chip short-circuit S parameters;

the first calibration unit is used for calculating initial eight errors of the on-chip S parameter measurement system according to the on-chip load S parameter, the on-chip open-circuit S parameter and the on-chip short-circuit S parameter;

and the first calculation unit is used for calculating the measured value of the on-chip short circuit calibration piece according to the initial eight errors.

In some embodiments of the present application, the second calibration module 205 may also be configured to: converting the crosstalk S parameter into the crosstalk Y parameter by utilizing the conversion relation between the Y parameter and the S parameter; converting the parallel S parameter into a parallel Y parameter by utilizing the conversion relation between the Y parameter and the S parameter; and determining the crosstalk error of the calibrated on-chip S parameter measurement system according to the crosstalk Y parameter and the parallel Y parameter.

Fig. 10 is a schematic diagram of an electronic device provided in an embodiment of the present application. As shown in fig. 10, the electronic device 30 of this embodiment includes: a processor 300 and a memory 301, the memory 301 having stored therein a computer program 302 executable on the processor 300. The processor 300, when executing the computer program 302, implements the steps described above in the embodiment of the slice S parameter measurement system error correction method, such as S101 to S103 shown in fig. 3. Alternatively, the processor 300, when executing the computer program 302, performs the functions of the modules/units of the apparatus embodiments described above, such as the functions of the modules 201 to 203 shown in fig. 9.

By way of example, the computer program 302 may be partitioned into one or more modules/units, which are stored in the memory 301 and executed by the processor 300 to complete the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing particular functions to describe the execution of the computer program 302 in the electronic device 30. For example, the computer program 302 may be split into modules 201 to 203 shown in fig. 9.

The electronic device 30 may be a single-chip microcomputer or a computing device such as a controller. Electronic device 30 may include, but is not limited to, a processor 300, a memory 301. It will be appreciated by those skilled in the art that fig. 10 is merely an example of an electronic device 30 and is not intended to limit the electronic device 30, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., an electronic device may also include an input-output device, a network access device, a bus, etc.

The processor 300 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 301 may be an internal storage unit of the electronic device 30, such as a hard disk or a memory of the electronic device 30. The memory 301 may also be an external storage device of the electronic device 30, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device 30. Further, the memory 301 may also include both internal storage units and external storage devices of the electronic device 30. The memory 301 is used to store computer programs and other programs and data required by the electronic device. The memory 301 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

The embodiment of the application also provides an on-chip S parameter measurement system which comprises a vector network analyzer and the electronic equipment 30. The vector network analyzer is controlled by an electronic device 30.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other manners. For example, the apparatus/electronic device embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the procedures in the methods of the foregoing embodiments, or may be implemented by a computer program for instructing related hardware to implement the steps of each of the embodiments of the error correction method of the on-chip S parameter measurement system, where the computer program may be stored in a computer readable storage medium and the computer program may be executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. An on-chip S parameter measurement system error correction method, comprising:

simulating the crosstalk calibration piece to obtain a crosstalk S parameter;

measuring the crosstalk calibration piece by using a calibrated on-chip S parameter measurement system to obtain parallel S parameters; the parallel S-parameters include crosstalk errors;

2. The on-chip S parameter measurement system error correction method of claim 1, wherein,

the first relation includes at least one of the following;

the first on-chip short circuit relationship is:

wherein L is _load,short,1 Representing a current load inductance of the on-chip load calibrator extracted at the first port using the on-chip short circuit calibrator, R _1,load Representing the on-chip negativesLoad resistor value, real (Z _1,app,short ) Representing the real part of the first short-circuit measurement of the on-chip short-circuit calibration member at the first port, imag (Z _1,app,short ) Representing the imaginary part of the first short-circuit measurement, w=2pi f, f representing the frequency of the on-chip S parameter measurement system;

the second on-chip short circuit relationship is:

wherein L is _load,short,2 Representing the current load inductance of the on-chip load calibrator extracted at the second port using the on-chip short circuit calibrator, R _2,load Representing the load resistance value of the on-chip load calibration member at the second port, real (Z _2,app,short ) Representing the real part of the second short measurement of the on-chip short calibration member at the second port, imag (Z _2,app,short ) Representing the imaginary part of the second short circuit measurement.

3. The on-chip S parameter measurement system error correction method of claim 2, wherein said calculating the current load inductance of the on-chip load calibration piece comprises:

will L _load,short,1 As the actual load inductance of the on-chip load calibration piece, or L _load,short,2 As the actual load inductance of the on-chip load calibration piece, or calculate L _load,short,1 And L _load,short,2 And taking the average value as the actual load inductance of the on-chip load calibration member.

4. The on-chip S parameter measurement system error correction method according to claim 1, wherein after obtaining the measurement value at the short-circuit calibration piece, the method further comprises:

acquiring a measured value of an on-chip open circuit calibration piece;

correspondingly, the calculating the current load inductance of the on-chip load calibration member based on the first predetermined relation to correct the on-chip load calibration member includes:

based on the first relation and a second relation which is determined in advance, calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece, the measured value of the on-chip open circuit calibration piece and the measured value of the on-chip short circuit calibration piece, and correcting the on-chip load calibration piece according to the current load inductance.

5. The on-chip S parameter measurement system error correction method of claim 4, wherein,

the second relation includes at least one of:

the first on-chip open-circuit relationship is:

wherein L is _load,open,1 Representing a current load inductance of the on-chip load calibrator extracted at the first port using the on-chip open circuit calibrator, R _1,load Representing the load resistance value of the on-chip load calibration member at the first port, real (Z _1,app,open ) Representing the real part of the first open measurement of the on-chip open calibration member at the first port, imag (Z _1,app,open ) Representing the imaginary part of the first open measurement value, w=2pi f, f representing the frequency of the on-chip S parameter measurement system;

the second on-chip open-circuit relationship is:

wherein L is _load,open,2 Representing the current load inductance of the on-chip load calibrator extracted at the second port using the on-chip open-circuit calibrator, R _2,load Indicating that the on-chip load calibrator is at the second portLoad resistance value, real (Z _2,app,open ) Representing the real part of the second open measurement of the on-chip open calibration member at the second port, imag (Z _2,app,open ) Representing the imaginary part of the second open circuit measurement.

6. The on-chip S parameter measurement system error correction method according to claim 1, wherein the obtaining the measured value of the on-chip short circuit calibration piece includes:

Measuring an on-chip load calibration piece, the on-chip open-circuit calibration piece and the on-chip short-circuit calibration piece by adopting an on-chip S parameter measurement system to obtain on-chip load S parameters, on-chip open-circuit S parameters and on-chip short-circuit S parameters;

calculating initial eight errors of the on-chip S parameter measurement system according to the on-chip load S parameter, the on-chip open-circuit S parameter and the on-chip short-circuit S parameter;

and calculating the measured value of the on-chip short circuit calibration piece according to the initial eight errors.

7. The on-chip S-parameter measurement system error correction method according to any one of claims 1 to 6, wherein the determining the crosstalk error of the on-chip S-parameter measurement system according to the crosstalk S-parameter, the parallel S-parameter, and the conversion relationship between the Y-parameter and the S-parameter includes:

converting the crosstalk S parameter into a crosstalk Y parameter by utilizing the conversion relation between the Y parameter and the S parameter;

converting the parallel S parameter into a parallel Y parameter by utilizing the conversion relation between the Y parameter and the S parameter;

and determining the crosstalk error of the calibrated on-chip S parameter measurement system according to the crosstalk Y parameter and the parallel Y parameter.

8. An on-chip S parameter measurement system error correction apparatus, comprising:

The first acquisition module is used for acquiring a measured value of the on-chip load calibration piece, and calculating the current load inductance of the on-chip load calibration piece based on a first predetermined relation so as to correct the on-chip load calibration piece;

the first calibration module is used for calibrating an uncalibrated on-chip S parameter measurement system based on the on-chip straight-through calibration piece, the on-chip reflection calibration piece and the corrected on-chip load calibration piece;

the simulation module is used for simulating the crosstalk calibration piece to obtain crosstalk S parameters;

the measuring module is used for measuring the crosstalk calibration piece by adopting the calibrated on-chip S parameter measuring system to obtain parallel S parameters; the parallel S-parameters include crosstalk errors;

the second calibration module is used for determining the crosstalk error of the on-chip S parameter measurement system according to the crosstalk S parameter, the parallel S parameter and the conversion relation between the Y parameter and the S parameter, and correcting the on-chip S parameter system according to the crosstalk error.

9. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that the processor, when executing the computer program, implements the steps of the on-chip S parameter measurement system error correction method according to any of the preceding claims 1 to 7.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the on-chip S parameter measurement system error correction method according to any of the preceding claims 1 to 7.