CN115542013A - Method for extracting load inductance from on-chip S parameters, electronic device and storage medium - Google Patents
Method for extracting load inductance from on-chip S parameters, electronic device and storage medium Download PDFInfo
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- CN115542013A CN115542013A CN202211096674.7A CN202211096674A CN115542013A CN 115542013 A CN115542013 A CN 115542013A CN 202211096674 A CN202211096674 A CN 202211096674A CN 115542013 A CN115542013 A CN 115542013A
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Abstract
The application provides a method for extracting load inductance from an S parameter, electronic equipment and a storage medium. The method comprises the following steps: acquiring a measured value of an on-chip open circuit calibration piece; calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measurement value of the on-chip open circuit calibration piece on the basis of a first predetermined relational expression; and calibrating the tested piece according to the current load inductance of the on-chip load calibration piece. The method and the device can improve the measurement reliability of the on-chip S parameter measurement system.
Description
Technical Field
The present disclosure relates to the field of on-chip S parameter technologies, and in particular, to a method for extracting a load inductance from an on-chip S parameter, an electronic device, and a storage medium.
Background
Before an on-chip S parameter measurement system used in the microelectronic industry is used, a proper calibration method needs to be selected for calibrating the system, and most of the existing on-chip calibration adopts an 8-team error model. The 8-team error model respectively represents the non-idealities of system source/load matching, reflection/transmission tracking, directivity, isolation and the like, and has high accuracy in the chip S parameter field, the coaxial field and the waveguide field, so that the 8-team error model is widely applied.
When the on-chip S parameter measurement system is calibrated through an 8-team error model, the standard value of the load inductance is directly used for calibration. However, since the value of the load inductance also changes in real time due to the difference in the position of the plunger during measurement, there may be an error in calibration using only the standard value of the load inductance.
Disclosure of Invention
The application provides a method for extracting load inductance from chip S parameters, electronic equipment and a storage medium, and aims to solve the problem that errors may exist when calibration is carried out only by using standard values of the load inductance because load inductance values can change in real time due to different positions of press pins during measurement.
In a first aspect, the present application provides a method for extracting load inductance in a slice S parameter, including:
acquiring a measured value of an on-chip open circuit calibration piece;
calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measurement value of the on-chip open circuit calibration piece on the basis of a first predetermined relational expression;
and calibrating the tested piece according to the current load inductance of the on-chip load calibration piece.
In one possible implementation, the first relation includes at least one of:
the first on-chip open-circuit relationship is:
wherein L is load,open,1 Representing the present load inductance of an on-chip load calibration piece extracted at a first port using an on-chip open calibration piece, R 1,load Representing the load resistance value, real (Z) of the on-chip load calibration member at the first port 1,app,open ) Real part, imag (Z) representing the first open measurement at the first port of the open-chip calibration 1,app,open ) Represents the imaginary part of the first open-circuit measurement, w =2 pi f, f represents the frequency of the on-chip S parameter measurement system;
the second on-chip open-circuit relationship is:
wherein L is load,open,2 Representing the present load inductance of an on-chip load calibration taken at the second port using an on-chip open calibration, R 2,load Representing the value of the load resistance, real (Z), of the on-chip load calibration member at the second port 2,app,open ) Real part, imag (Z), representing the second open measurement at the second port of the chip open calibration 2,app,open ) Representing the imaginary part of the second open measurement.
In one possible implementation, calculating a current load inductance of the on-chip load calibration piece includes:
will L load,open,1 Current load inductance as an on-chip load calibration, or L load,open,2 Current load inductance as an on-chip load calibration, or calculating L load,open,1 And L load,open,2 And taking the average as the current load inductance of the on-chip load calibration piece.
In one possible implementation, after obtaining the measurement value at the open chip calibration piece, the method further includes:
acquiring a measured value of an on-chip short circuit calibration piece;
correspondingly, based on a first predetermined relation, calculating the current load inductance of the on-chip load calibration element according to the load resistance value of the on-chip load calibration element and the measurement value of the on-chip open calibration element, comprising:
based on the first relational expression and a second relational expression which is predetermined, the current load inductance of the on-chip load calibration member is calculated according to the load resistance value of the on-chip load calibration member, the measurement value of the on-chip open circuit calibration member and the measurement value of the on-chip short circuit calibration member.
In one possible implementation, the second relation includes at least one of:
the first on-chip short-circuit relation is:
wherein L is load,short,1 Representing the present load inductance, R, of an on-chip load calibration element taken at a first port using an on-chip short calibration element 1,load Representing the load resistance value, real (Z) of the on-chip load calibration member at the first port 1,app,short ) Real part, imag (Z), representing the first short circuit measurement at the first port of the patch short circuit calibration element 1,app,short ) Represents the imaginary part of the first short measurement value, w =2 π f, f represents the frequency of the on-chip S parameter measurement system;
the second on-chip short-circuit relation is:
wherein L is load,short,2 Representing the present load inductance of the on-chip load calibration piece, R, taken at the second port using the on-chip short calibration piece 2,load Representing the value of the load resistance, real (Z), of the on-chip load calibration member at the second port 2,app,short ) Representing the real part of a second short measurement at the second port of the on-chip short calibration piece，imag(Z 2,app,short ) Representing the imaginary part of the second short circuit measurement.
In one possible implementation, obtaining measurements of an open chip calibration piece includes:
respectively measuring an on-chip load calibration piece, an on-chip open circuit calibration piece and an on-chip short circuit calibration piece by using an on-chip S parameter measuring system to obtain an on-chip load S parameter, an on-chip open circuit S parameter and an on-chip short circuit S parameter;
calculating initial eight errors of the on-chip S parameter measuring system according to the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter;
the measurements at the open chip calibration were calculated from the initial eight errors.
In one possible implementation, calibrating the measured object according to the current load inductance of the on-chip load calibration element includes:
calculating the correction eight errors of the on-chip S parameter measuring system based on the current load inductance of the on-chip load calibration piece;
and calibrating the tested piece according to the eight corrected errors.
In a second aspect, the present application provides an apparatus for extracting load inductance in S-parameters, comprising:
the first acquisition module is used for acquiring the measured value of the on-chip open circuit calibration piece;
the first calculation module is used for calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measurement value of the on-chip open circuit calibration piece based on a predetermined first relational expression;
and the calibration module is used for calibrating the tested piece according to the current load inductance of the on-chip load calibration piece.
In a third aspect, the present application provides an electronic device, including a memory and a processor, where the memory stores a computer program operable on the processor, and the processor, when executing the computer program, implements the steps of the method for extracting load inductance in slice S parameters according to the first aspect or any one of the possible implementations of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method for extracting load inductance in slice S parameters as described in the first aspect or any one of the possible implementations of the first aspect.
The application provides a method for extracting load inductance from an on-chip S parameter, electronic equipment and a storage medium, and in consideration of the fact that in the calibration process, different pressing pin positions possibly cause the load inductance of an on-chip load calibration piece to change during measurement, therefore, the current load inductance of the on-chip load calibration is extracted by using the measured value of the on-chip open circuit calibration piece, the on-chip load calibration piece is corrected, the corrected on-chip load calibration piece is finally used for calibration, the measurement accuracy of an on-chip S parameter measurement system can be improved, and the measurement reliability of the on-chip S parameter measurement system is further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is an 8-team error model provided by an embodiment of the present application;
FIG. 2 is a model of 8-team error in ABCD parameters provided in an embodiment of the present application;
fig. 3 is a flowchart illustrating an implementation of a method for extracting load inductance in a slice S parameter according to an embodiment of the present application;
FIG. 4 is a diagram illustrating the relationship between ABCD parameters and voltage and current in an embodiment of the present application;
FIG. 5 is a schematic diagram of an equivalent circuit of a sheet load calibration member in an embodiment of the present application;
FIG. 6 shows the measurement results of the S21 parameter provided in the embodiments of the present application;
FIG. 7 shows the measurement results of the S11 parameter provided in the embodiments of the present application;
fig. 8 is a schematic structural diagram of an apparatus for extracting load inductance in a slice S parameter according to an embodiment of the present application;
fig. 9 is a schematic diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
To make the objects, technical solutions and advantages of the present application more clear, the following description is made by way of specific embodiments with reference to the accompanying drawings.
See fig. 1. Which shows an 8-team error model provided by an embodiment of the present application. As shown in FIG. 1, the 8-team error characterizes imperfections in the on-chip S parameter measurement system in terms of source/load matching, reflection/transmission tracking, directivity, isolation, etc. The method has high accuracy in the field of sheet S parameter measurement, the coaxial field and the waveguide field, and thus is widely applied. The SOLT (Short-Open-Load-Thru) calibration method needs to accurately know the definition of four calibration pieces; the TRL (straight-reflecting-Line) calibration method has a high requirement for a load calibration component, and the frequency coverage range is not wide enough due to only one transmission Line; the LRRM (Line-reflection-Match) calibration method has less definition requirements on calibration pieces, the inductance and capacitance of the two reflection calibration pieces do not need to be known, the theoretical delay of the two reflection calibration pieces only needs to be calculated, and the inductance in the load calibration piece is extracted in real time according to the position of the probe, so that the LRRM calibration method has higher accuracy and is widely applied.
Referring to FIG. 2, an 8-team error model expressed in ABCD parameters provided by the embodiments of the present application is shown. As shown in fig. 2, the eight-term error model is usually represented by using S parameters, and in the actual solution process, error networks need to be cascaded, and the error networks are represented by transfer parameters (ABCD) (there is a one-to-one relationship between ABCD parameters and S parameters), which is convenient for cascade calculation. Wherein, the conversion relation between the ABCD parameter and the S parameter is shown as formula (1):
wherein S is 11 、S 12 、S 21 、S 22 Represents the S parameter.
The vector network analyzer is used as an on-chip S parameter measuring system and plays an important role in the field of on-chip S parameters. The process of calibrating the on-chip S parameter measurement system may be as follows:
SS01, measuring an on-chip load calibration piece by using an uncalibrated on-chip S parameter measuring system to obtain an on-chip load S parameter; measuring an on-chip short circuit calibration piece by using an uncalibrated on-chip S parameter measurement system to obtain an on-chip short circuit S parameter; and measuring the on-chip open circuit calibration piece by using the uncalibrated on-chip S parameter measuring system to obtain the on-chip open circuit S parameter. Wherein the load inductance of the on-chip load calibration piece is a known standard value.
And SS02, calculating eight errors by using the on-chip load S parameter, the on-chip short circuit S parameter and the on-chip open circuit S parameter, namely: a. The 1 /D 1 、B 1 /D 1 、C 1 /D 1 、A 2 /D 2 、B 2 /D 2 、C 2 /D 2 And D 1 D 2 。
And SS03, calibrating the uncalibrated on-chip S parameter measuring system by using the eight errors, thereby obtaining the calibrated on-chip S parameter measuring system.
In the actual calibration process, due to the different positions of the pressing pins during calibration, the on-chip short circuit calibration element, the on-chip load calibration element and the on-chip open circuit calibration element may be affected, i.e. the nominal value is not necessarily the actual value. Through judging, the influence of the pin pressing position on the on-chip short circuit calibration piece and the on-chip open circuit calibration piece can be ignored. However, the influence on the load inductance of the on-chip load calibration piece is large, the load inductances corresponding to different pressing pin positions are different, and the measured piece is measured directly based on the standard load inductance without calibration, and the measurement may be inaccurate.
In order to solve the above problem, embodiments of the present application provide a method for extracting load inductance in slice S parameters, which is described in detail below with reference to the accompanying drawings.
Referring to fig. 3, it shows a flowchart of an implementation of the method for extracting load inductance in the slice S parameter provided in the embodiment of the present application. As shown in fig. 3, a method for extracting load inductance in slice S parameter may include S101 to S103.
And S101, acquiring a measured value of the on-chip open circuit calibration piece.
The on-chip open circuit calibration piece, the on-chip short circuit calibration piece and the on-chip load calibration piece can be measured by a vector network analyzer respectively, and the measurement value of the on-chip open circuit calibration piece is calculated according to the measurement result.
For a two-port network, it includes a first port and a second port. Accordingly, the measurements at the open chip calibration piece may include: a first open measurement at the first port of the chip open calibration element, and/or a second open measurement at the second port of the chip open calibration element. The method can be selected according to actual conditions.
For example, the process of obtaining measurements at an open chip calibration piece may include:
s1011, respectively measuring the on-chip load calibration piece, the on-chip open circuit calibration piece and the on-chip short circuit calibration piece by using the on-chip S parameter measuring system to obtain an on-chip load S parameter, an on-chip open circuit S parameter and an on-chip short circuit S parameter.
Specifically, an on-chip load calibration piece is measured by an on-chip S parameter measurement system to obtain an on-chip load S parameter. And measuring the on-chip short circuit calibration piece by using the on-chip S parameter measuring system to obtain the on-chip short circuit S parameter. And measuring the on-chip open circuit calibration piece by using the on-chip S parameter measuring system to obtain the on-chip open circuit S parameter.
S1012, calculating initial eight errors of the on-chip S parameter measuring system according to the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter.
According to the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter, the initial eight errors of the on-chip S parameter measuring system can be calculated.
And S1013, calculating the measurement value of the on-chip open circuit calibration piece according to the initial eight errors.
Based on the existing mode, the measured value of the on-chip open-circuit calibration piece can be calculated according to the initial eight errors. The embodiments of the present application are not described herein in detail.
S102, based on a first predetermined relational expression, calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measurement value of the on-chip open circuit calibration piece.
The load resistance value of the chip load calibration piece is a known standard value, and the influence on the load resistance value in the actual measurement process is negligible. In order to further ensure the reliability of measurement, a digital multimeter can be used for measuring the load resistance measurement value of the on-chip load calibration piece, and then the current load inductance of the load calibration piece is accurately calculated by using the load resistance measurement value, so that the calibration precision can be further improved.
The first relation may be expressed as equation (2), as follows:
wherein L is load,open Representing the current load inductance, R, of an on-chip load calibration piece extracted using an on-chip open calibration piece load Indicating the value of the load resistance, real (Z), of the on-chip load calibration element app,open ) Real part, imag (Z) representing the measured value at open chip calibration app,open ) The imaginary part of the measured value of the on-chip open calibration element is indicated, w =2 π f, f denotes the frequency of the on-chip S parameter measurement system.
S103, calibrating the tested piece according to the current load inductance of the on-chip load calibration piece.
After the current load inductance of the piece load calibration piece is obtained, eight errors can be recalculated, namely eight corrected errors are obtained, and then the eight corrected errors are used for calibrating the measured value of the measured piece to obtain the true value of the measured piece. The tested piece can be a microwave module, such as a DUT.
Illustratively, the calibration process may include:
and S1031, calculating eight correction errors of the on-chip S parameter measuring system based on the current load inductance of the on-chip load calibration piece.
Eight errors of the on-chip S parameter measuring system can be recalculated according to the current load inductance of the on-chip load calibration piece, the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter, and the eight errors are used as correction eight errors.
And S1032, calibrating the tested piece according to the eight corrected errors.
For each measured piece, the load inductance of the on-chip load calibration piece also changes due to the different positions of the pressing pins during measurement. Therefore, during each measurement, the current load inductance can be obtained through recalculation, then eight errors are calculated and corrected, and further the measured value of the measured piece is corrected to obtain the true value of the measured piece.
According to the embodiment of the application, the current load inductance of the on-chip load calibration piece is extracted by using the measured value of the on-chip open circuit calibration piece, and then the measured value of the measured piece is corrected to obtain the true value of the measured piece, so that the measurement accuracy of the on-chip S parameter measurement system can be improved, and the measurement reliability of the on-chip S parameter measurement system is improved.
In some embodiments of the present application, the first relationship comprises at least one of:
the first on-chip open-circuit relationship is:
wherein L is load,open,1 Showing an on-chip load calibration member extracted at a first port using an on-chip open calibration memberCurrent load inductance of R 1,load Representing the value of the load resistance at the first port, real (Z), of the on-chip load calibration element 1,app,open ) Real part, imag (Z) representing the first open measurement at the first port of the open-chip calibration 1,app,open ) Represents the imaginary part of the first open-circuit measurement, w =2 pi f, f represents the frequency of the on-chip S parameter measurement system;
the second on-chip open-circuit relation is:
wherein L is load,open,2 Representing the present load inductance of an on-chip load calibration taken at the second port using an on-chip open calibration, R 2,load Representing the value of the load resistance, real (Z), of the on-chip load calibration member at the second port 2,app,open ) Real part, imag (Z) representing a second open measurement at a second port of the on-chip open calibration 2,app,open ) Representing the imaginary part of the second open measurement.
The following gives the inference process of the first relation in the embodiment of the present application:
referring to fig. 4, a diagram of ABCD parameter versus voltage and current in the embodiment of the present application is shown. Referring to fig. 5, there is shown an equivalent circuit schematic of the sheet load calibration piece in the embodiment of the present application.
As shown in fig. 3, ABCD is a parameter expressed in terms of voltage and current, and by definition, when measured on a sheet calibration piece, the relationships (5) and (6) are obtained.
Wherein, Z 1,A Representing the actual impedance value, Z, of the on-chip calibration member at the first port 1,M Indicated at the first end of the sheet alignment memberImpedance measurement of the mouth, Z 2,A Representing the actual impedance value, Z, of the on-chip calibration member at the first port 2,M Representing the impedance measurement at the first port of the chip calibration piece.
As shown in fig. 4, in an ideal case, for the on-chip open calibration piece of the first port, equation (7) can be obtained from equation (5); for the on-chip short calibration of the first port, equation (8) can be derived from equation (5). For the on-chip open circuit calibration piece of the second port, equation (9) can be obtained from equation (6); for the on-chip short calibration piece of the second port, equation (10) can be obtained from equation (6). The method comprises the following specific steps:
wherein, Z 1,M,open Representing the measured impedance value, Z, at the first port of the open-chip calibration member 1,M,short Representing the measured impedance value, Z, of the on-chip short calibration element at the first port 2,M,open Representing the measured impedance value, Z, at the second port of the open-chip calibration member 2,M,short Representing the measured impedance value, Z, at the second port of the on-chip short calibration member 1,A,open Representing the actual impedance value, Z, of the open-chip calibration element at the first port 1,A,short Representing the actual impedance value, Z, of the on-chip short calibration piece at the first port 2,A,open Representing the actual impedance value, Z, of the open-chip calibration element at the second port 2,A,short Representing the actual impedance value of the on-chip short calibration at the second port. Wherein the actual impedanceThe value is also known as the nominal value of the impedance.
From formulae (5) and (6), formulae (11) and (12) are obtained as follows:
for an on-chip calibration piece of the first port,
there is a corresponding measured value
Formula (13) can be obtained. For an on-chip calibration piece of the second port,
there is a corresponding measured value
The formula (14) can be obtained. The following:
from equations (11) and (13), a proportional value Q1 in equation (15) can be obtained, and from equations (12) and (14), a proportional value Q2 in equation (16) can be obtained, as follows:
for the on-chip load calibration of the first port and the second port, equations (17) and (18) are obtained from equations (15) and (16), respectively, as follows:
wherein Z is 1,app,load Representing the measurement at the first port of the on-chip load calibration member, Z 1,A,load Representing the actual value of the on-chip load calibration member at the first port, Z 2,app,load Representing the measurement, Z, of the on-chip load calibration member at the second port 2,A,load Representing the actual value of the on-chip load calibration piece at the second port.
The measurements of the on-chip load calibration for the first and second ports are shown in equations (19), (20), respectively, as follows:
Z 1,app,load ＝R 1,load +jwL 1,load (19)
Z 2,app,load ＝R 2,load +jwL 2,load (20)
the actual values of the on-chip load calibration when the reference plane is in the through middle are shown in equations (18), (19) as follows:
Z 1,A,load ＝R 1,load (21)
Z 2,A,load ＝R 2,load (22)
in the embodiment of the present application, the process of obtaining the first on-chip open relation (3) is as follows:
for an on-chip open calibration of the first port, equation (23) is derived from (15), as follows:
when the reference plane is in the through-center, the measurement value of the on-chip open calibration piece for the first port is expressed as equation (24), as follows:
wherein, C 01,open Representing the port capacitance at the first port of the open-chip calibration piece.
The actual value of the on-chip open calibration piece for the first port is expressed as equation (25), as follows:
order:
real(Z 1,app,open )＝R 1,open (26)
equations (25) and (26) are derived from equations (14), (16) and (20), (23), (24), as follows:
a first on-chip open-circuit relation (3) is obtained from equation (29) as follows:
where w =2 pi f, f denotes frequency.
In the embodiment of the present application, the process of obtaining the second on-chip open-circuit relation (4) is as follows:
for the on-chip open calibration piece of the second port, equation (30) is obtained from equation (16) as follows:
when the reference plane is in the through-center, the on-chip open calibration measurement for the second port is represented by equation (31), as follows:
wherein, C 02,open Representing the port capacitance at the second port of the open-chip calibration piece.
The actual value of the on-chip open calibration piece for the second port is expressed as equation (32), as follows:
order:
real(Z 2,app,open )＝R 2,open (33)
equations (35) and (36) are derived from equations (18), (20) and (30), (33), (34), as follows:
a second on-chip open-circuit relational expression (4) is obtained from expression (36) as follows:
the derivation process for obtaining the first on-chip open-circuit relation (3) and the second on-chip open-circuit relation (4) is provided above for the embodiments of the present application. The current load inductance of the on-chip load calibration piece can be extracted according to equation (3) and/or equation (4).
According to the embodiment of the application, the current load inductance of the on-chip load calibration piece is extracted by pre-deducing the first relational expression, namely the first on-chip open-circuit relational expression and the second on-chip open-circuit relational expression, the calculation is convenient and fast, and the calibration efficiency of the on-chip S parameter measurement system can be improved.
In some embodiments of the present application, the "calculating the current load inductance of the on-chip load calibration piece" in S102 may include:
mixing L with load,open,1 Current load inductance as an on-chip load calibration, or L load,open,2 Current load inductance as an on-chip load calibration, or calculating L load,open,1 And L load,open,2 And taking the average as the current load inductance of the on-chip load calibration piece.
When the first relation includes only the first on-chip open-circuit relation, L may be load,open,1 As the current load inductance of the on-chip load calibration.
When the first relation includes only the second on-chip open relation, L may be load,open,2 As the current load inductance of the on-chip load calibration.
Calculating L when the first relation includes a first on-chip open-circuit relation and a second on-chip open-circuit relation load,open,1 And L load,open,2 And the average value is taken as the current load inductance of the on-chip load calibration piece.
According to the embodiment of the application, at least three calculation modes for calculating the current load inductance of the on-chip load calibration piece are provided, the calculation efficiency of a single relational expression is higher, the calculation accuracy for solving the average value is higher, and the calculation modes can be specifically selected by combining actual conditions.
In some embodiments of the present application, the current load inductance of the on-chip load calibration piece may also be extracted jointly with the on-chip short calibration piece and the on-chip open calibration piece for higher accuracy. The specific process is as follows:
after obtaining measurements at the open chip calibration piece, the method further comprises:
measurements of on-chip short calibration are acquired.
The on-chip open circuit calibration piece, the on-chip short circuit calibration piece and the on-chip load calibration piece can be measured by a vector network analyzer respectively, and a measurement value of the on-chip short circuit calibration piece is calculated according to the measurement result.
For a two-port network, it includes a first port and a second port. Accordingly, the measurements of the on-chip shorting calibration may include: a first short measurement at the first port of the on-chip short calibration element, and/or a second short measurement at the second port of the on-chip short calibration element. The specific method can be selected according to actual conditions.
For example, the process of obtaining measurements of the on-chip short calibration piece may include:
an on-chip S parameter measuring system is adopted to measure an on-chip load calibration piece, an on-chip open circuit calibration piece and an on-chip short circuit calibration piece respectively to obtain an on-chip load S parameter, an on-chip open circuit S parameter and an on-chip short circuit S parameter.
And calculating initial eight errors of the on-chip S parameter measuring system according to the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter.
Based on the existing mode, the measured value of the on-chip short circuit calibration piece can be calculated according to the initial eight errors. The embodiments of the present application are not described herein in detail.
Accordingly, the "calculating the current load inductance of the on-chip load calibration member based on the load resistance value of the on-chip load calibration member and the measurement value of the on-chip open calibration member based on the predetermined first relation" in S102 may include:
based on the first relational expression and a second relational expression which is predetermined, the current load inductance of the on-chip load calibration member is calculated according to the load resistance value of the on-chip load calibration member, the measurement value of the on-chip open circuit calibration member and the measurement value of the on-chip short circuit calibration member.
The second relation may be represented as equation (37), as follows:
wherein L is load,short Representing the present load inductance, R, of an on-chip load calibration piece extracted using an on-chip short calibration piece load Indicating the value of the load resistance, real (Z), of the on-chip load calibration element app,short ) Real part, imag (Z) representing the measured value of the on-chip short calibration piece app,short ) The imaginary part of the measurement value of the on-chip short calibration piece is represented.
In some embodiments of the present application, the second relationship comprises at least one of:
the first on-chip short-circuit relation is:
wherein L is load,short,1 Representing the present load inductance, R, of an on-chip load calibration piece extracted at a first port using an on-chip short calibration piece 1,load Representing the load resistance value, real (Z) of the on-chip load calibration member at the first port 1,app,short ) Real part, imag (Z) representing a first short measurement at the first port of the patch short calibration piece 1,app,short ) Denotes the imaginary part of the first short-circuit measurement value, w =2 pi f, f denotes the frequency of the on-chip S-parameter measurement system.
The second on-chip short-circuit relation is:
wherein L is load,short,2 Representing the present load inductance of the on-chip load calibration piece, R, taken at the second port using the on-chip short calibration piece 2,load Representing the value of the load resistance, real (Z), of the on-chip load calibration member at the second port 2,app,short ) Real part, imag (Z), representing a second short circuit measurement at the second port of the on-chip short circuit calibration element 2,app,short ) Representing the imaginary part of the second short circuit measurement.
The following provides an inference process of the second relational expression in the embodiment of the present application.
In an embodiment of the present application, the process of obtaining the first in-short relationship (38) is as follows:
for the on-chip short calibration piece of the first port, equation (40) is obtained from equation (15) as follows:
when the reference plane is in the through-center, the measurement of the on-chip short calibration feature of the first port is expressed as equation (41), as follows:
Z 1,app,short ＝R 1,short +jwL 1,short (41)
wherein L is 1,short Representing the port inductance at the first port of the calibration piece at the chip short.
The actual value of the on-chip short calibration feature for the first port is expressed as equation (42), as follows:
Z 1,A,short ＝jwL 1,short (42)
order:
real(Z 1,app,short )＝R 1,short (43)
imag(Z 1,app,short )＝wL 1,short (44)
formulae (45) and (46) are obtained from formulae (17), (19) and formulae (40), (43), (44) as follows:
a first on-chip short-circuit relational expression (38) is obtained from the expression (46), as follows:
in the embodiment of the present application, the process of obtaining the second short-circuit relationship (39) is as follows:
for the on-chip short calibration piece of the second port, equation (47) is obtained from equation (16) as follows:
when the reference plane is in the through middle, the measurement value of the on-chip short calibration piece of the second port is expressed as equation (48), as follows:
Z 2,app,short ＝R 2,short +jwL 2,short (48)
wherein L is 2,short Representing the port inductance at the second port of the tab short calibration piece.
The actual value of the on-chip short calibration piece for the second port is expressed as equation (49), as follows:
Z 2,A,short ＝jwL 2,short (49)
order:
real(Z 2,app,short )＝R 2,short (50)
imag(Z 2,app,short )＝wL 2,short (51)
from formulae (18), (20) and formulae (47), (50), (51), formulae (52) and (53) result, as follows:
a second on-chip short-circuit relational expression (39) is obtained from expression (53), as follows:
in some embodiments of the present application, the "calculating the current load inductance of the on-chip load calibration piece" in S102 may include:
will be provided with
Current load inductance as an on-chip load calibration, or
Current load inductance as an on-chip load calibration, or calculating L load,open,1 、L load,open,2 、L load,short,1 And L load,short,2 And the average value is taken as the current load inductance of the on-chip load calibration piece.
When the first relation only comprises the first on-chip open-circuit relation and the second relation only comprises the first on-chip short-circuit relation, the first on-chip short-circuit relation will be defined
As the current load inductance of the on-chip load calibration.
When the first relational expression only comprises the second on-chip open-circuit relational expression and the second relational expression only comprises the second on-chip short-circuit relational expression, the first and second on-chip short-circuit relational expressions will be different
As the current load inductance of the on-chip load calibration.
Calculating L when the first relation includes a first on-chip open-circuit relation and a second on-chip open-circuit relation, and the second relation includes a first on-chip short-circuit relation and a second on-chip open-circuit relation load,open,1 、L load,open,2 、L load,short,1 And L load,short,2 And taking the average as the current load inductance of the on-chip load calibration piece.
In addition, the method can further comprise the following steps: when the first relation only comprises a first on-chip open-circuit relation and the second relation only comprises a second on-chip short-circuit relation, the first relation and the second relation are different, and the first relation and the second relation are different
As the current load inductance of the on-chip load calibration. When the first relational expression only comprises the second on-chip open-circuit relational expression and the second relational expression only comprises the first on-chip short-circuit relational expression, the first on-chip short-circuit relational expression will be obtained
As the current load inductance of the on-chip load calibration. Specifically, the selection may be performed according to actual situations, and details are not described herein in this embodiment of the application.
In some embodiments of the present application, the load inductance calculated by the second relational expression may also be taken as the current load inductance of the on-chip calibration piece. For example, L may be load,short,1 Current load inductance as an on-chip load calibration, or L load,short,2 Current load inductance as an on-chip load calibration, or
As the current load inductance of the on-chip load calibration. The selection can be specifically carried out according to the actual situation.
The load inductance has a frequency response as the frequency changes, and averaging the inductance in the frequency band can reduce the influence introduced by the frequency response. Therefore, in some embodiments of the present application, the "calculating the current load inductance of the on-chip load calibration piece" in S102 may further include:
and taking the average value of the load inductances in the preset frequency band as the load inductance of the load calibration piece.
Namely:
wherein L is oad Representing the load inductance of the on-chip load calibration member, L 1 ，L 2 ，......，L n And representing the extracted value of the load inductance of each frequency point in the preset frequency band. The preset frequency band can be a frequency band above 2GHz, and can be specifically selected according to actual conditions.
According to the embodiment of the application, the average value of the load inductance in the preset frequency band is calculated to serve as the current load inductance of the on-chip calibration piece, and the influence of the pressing position on the influence of the on-chip load calibration piece is considered, so that the calculation result is more accurate, and the measurement accuracy of the measured piece is further improved.
For example, refer to fig. 6, which shows the measurement result of the S21 parameter provided in the embodiment of the present application. Referring to fig. 7, a measurement result of the S11 parameter provided in the embodiment of the present application is shown.
The 10dB attenuator is selected as a tested piece, the load inductance value extracted by the method provided by the embodiment of the application and the LRRM calibration method of the existing method are respectively used for calibrating the same on-chip S parameter measurement system in the frequency band of 100 MHz-67 GHz, the same 10dB attenuator is measured after calibration is finished, the S parameter of the reference surface at the probe end is obtained, and the measurement results are compared.
As shown in FIGS. 6 and 5, 10dB _WINCAL (S21)/10dB _WINCAL (S11) indicates the measurement result of WINCAL; 10db _1 (S21)/10db _1 (S11) indicates that the measurement result of extracting the load inductance using the on-chip open calibration piece of the first port, that is, the load inductance is: l is a radical of an alcohol load,open,1 (ii) a 10db _2 (S21)/10db _2 (S11) represents the result of the measurement of the load inductance extracted using the on-chip short calibration piece of the first port, i.e., the load inductance is: l is load,short,1 ；10dB_3(S21) A/10db_3 (S11) indicates that the measurement results of the load inductance are extracted by using the on-chip open-circuit calibration piece and the on-chip short-circuit calibration piece of the first port, namely that the load inductance is as follows:
10db _4 (S21)/10db _4 (S11) represents the result of extracting the measurement of the load inductance using the on-chip open calibration piece of the second port, i.e., the load inductance is: l is load,open,2 (ii) a 10db _5 (S21)/10db _5 (S11) represents the result of the measurement of the load inductance extracted using the on-chip short calibration piece of the second port, i.e., the load inductance is: l is load,short,2 (ii) a 10db _6 (S21)/10db _6 (S11) indicates that the measurement results of the load inductance are extracted using the on-chip open circuit calibration piece and the on-chip short circuit calibration piece of the second port, i.e., the load inductance is:
10db _7 (S21)/10db _7 (S11) indicates that the measurement result of the load inductance is extracted using the on-chip open calibration piece of the first port and the second port, that is, the load inductance is: l is a radical of an alcohol load,open,1 And L load,open,2 Average value of (d); 10db _8 (S21)/10db _8 (S11) indicates that the measurement of the load inductance is extracted using the on-chip short circuit calibration pieces of the first port and the second port, i.e., the load inductance is: l is load,short,1 And L load,short,2 Average value of (d);
from the results of fig. 6 and 7, it can be seen that: the method provided by the embodiment of the application is the same as the WINCAL software measurement, and the maximum transmission amplitude deviation of the 10dB attenuator is 0.15dB and the maximum reflection amplitude deviation is 0.08. The method for extracting the load inductance in real time is reasonable, and meets the requirements of on-chip S parameter calibration and test.
According to the embodiment of the application, the ratio of the measured value to the actual value is calculated according to the condition that the reference surface of the on-chip open circuit calibration piece or the on-chip short circuit calibration piece is in the straight-through middle. And then, calculating to obtain the load inductance value extracted in real time in the on-chip S parameter calibration through the on-chip open circuit calibration piece, the S parameter measurement value of the on-chip short circuit calibration piece and the direct current resistance measurement value of the on-chip load calibration piece. And finally, taking the average value of the load inductance in the frequency band to reduce the influence introduced by the frequency response. The method can realize accurate measurement of the tested piece, can achieve better indexes, meets the on-chip S parameter calibration and test work of the requirement, and has certain economic and social benefits.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by functions and internal logic of the process, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the following, embodiments of the apparatus of the present application are provided, and for details which are not described in detail therein, reference may be made to the corresponding method embodiments described above.
Fig. 8 shows a schematic structural diagram of an apparatus for extracting load inductance in a slice S parameter provided in an embodiment of the present application, and for convenience of description, only the portions related to the embodiment of the present application are shown, which is detailed as follows:
as shown in fig. 8, the device 20 for extracting the load inductance in the slice S parameter may include:
a first obtaining module 201, configured to obtain a measurement value of an on-chip open calibration part;
a first calculating module 202, configured to calculate a current load inductance of the on-chip load calibration element according to a load resistance value of the on-chip load calibration element and a measurement value of the on-chip open calibration element based on a predetermined first relation;
and the calibration module 203 is used for calibrating the tested piece according to the current load inductance of the on-chip load calibration piece.
In some embodiments of the present application, the first relationship comprises at least one of:
the first on-chip open-circuit relationship is:
wherein L is load,open,1 Representing the present load inductance of an on-chip load calibration piece extracted at a first port using an on-chip open calibration piece, R 1,load Representing the value of the load resistance at the first port, real (Z), of the on-chip load calibration element 1,app,open ) Real part, imag (Z), representing the first open measurement at the first port of the chip open calibration 1,app,open ) Represents the imaginary part of the first open-circuit measurement, w =2 pi f, f represents the frequency of the on-chip S parameter measurement system;
the second on-chip open-circuit relation is:
wherein L is load,open,2 Representing the present load inductance, R, of an on-chip load calibration element taken at the second port using an on-chip open calibration element 2,load Representing the value of the load resistance, real (Z), of the on-chip load calibration member at the second port 2,app,open ) Real part, imag (Z) representing a second open measurement at a second port of the on-chip open calibration 2,app,open ) Representing the imaginary part of the second open measurement.
In some embodiments of the present application, the first calculation module 202 may be further configured to calculate L load,open,1 Current load inductance as an on-chip load calibration, or L load,open,2 Current load inductance as an on-chip load calibration, or calculating L load,open,1 And L load,open,2 And taking the average as the current load inductance of the on-chip load calibration piece.
In some embodiments of the present application, the apparatus 20 may further include:
the second acquisition module is used for acquiring the measured value of the on-chip short-circuit calibration piece after acquiring the measured value of the on-chip open-circuit calibration piece;
and the second calculation module is used for calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece, the measured value of the on-chip open circuit calibration piece and the measured value of the on-chip short circuit calibration piece based on the first relational expression and a predetermined second relational expression.
In some embodiments of the present application, the second relationship comprises at least one of:
the first on-chip short-circuit relation is:
wherein L is load,short,1 Representing the present load inductance, R, of an on-chip load calibration piece extracted at a first port using an on-chip short calibration piece 1,load Representing the value of the load resistance at the first port, real (Z), of the on-chip load calibration element 1,app,short ) Real part, imag (Z) representing a first short measurement at the first port of the patch short calibration piece 1,app,short ) Denotes the imaginary part of the first short circuit measurement, w =2 pi f, f denotes the frequency of the on-chip S parameter measurement system;
the second on-chip short-circuit relation is:
wherein L is load,short,2 Representing the present load inductance of the on-chip load calibration piece, R, taken at the second port using the on-chip short calibration piece 2,load Representing the value of the load resistance, real (Z), of the on-chip load calibration member at the second port 2,app,short ) Real part, imag (Z) representing a second short measurement at the second port of the patch short calibration piece 2,app,short ) Representing the imaginary part of the second short circuit measurement.
In some embodiments of the present application, the obtaining module 201 may include:
the measuring unit is used for respectively measuring an on-chip load calibrating piece, an on-chip open circuit calibrating piece and an on-chip short circuit calibrating piece by adopting an on-chip S parameter measuring system to obtain an on-chip load S parameter, an on-chip open circuit S parameter and an on-chip short circuit S parameter;
the first calibration unit is used for calculating initial eight errors of the on-chip S parameter measurement system according to the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter;
and the first calculating unit is used for calculating the measurement value of the open chip calibration part according to the initial eight errors.
In some embodiments of the present application, the calibration module 203 may include:
the second calculation unit is used for calculating eight corrected errors of the on-chip S parameter measurement system based on the current load inductance of the on-chip load calibration piece;
and the second calibration unit is used for calibrating the tested piece according to the eight corrected errors.
Fig. 9 is a schematic diagram of an electronic device provided in an embodiment of the present application. As shown in fig. 9, the electronic apparatus 30 of this embodiment includes: a processor 300 and a memory 301, the memory 301 having stored therein a computer program 302 executable on the processor 300. The processor 300, when executing the computer program 302, implements the steps in the above-described method embodiment of extracting the load inductance in the slice S parameter, such as S101 to S103 shown in fig. 3. Alternatively, the processor 300, when executing the computer program 302, implements the functions of each module/unit in each apparatus embodiment described above, for example, the functions of the modules 201 to 203 shown in fig. 8.
Illustratively, the computer program 302 may be partitioned into one or more modules/units, which are stored in the memory 301 and executed by the processor 300 to complete the present application. One or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 302 in the electronic device 30. For example, the computer program 302 may be divided into the modules 201 to 203 shown in fig. 8.
The electronic device 30 may be a computing device such as a single chip or a controller. The electronic device 30 may include, but is not limited to, a processor 300, a memory 301. Those skilled in the art will appreciate that fig. 9 is merely an example of an electronic device 30 and does not constitute a limitation of the electronic device 30 and may include more or fewer components than shown, or combine certain components, or different components, e.g., the electronic device may also include input-output devices, network access devices, buses, etc.
The Processor 300 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 301 may be an internal storage unit of the electronic device 30, such as a hard disk or a memory of the electronic device 30. The memory 301 may also be an external storage device of the electronic device 30, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like provided on the electronic device 30. Further, the memory 301 may also include both an internal storage unit and an external storage device of the electronic device 30. The memory 301 is used to store computer programs and other programs and data required by the electronic device. The memory 301 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The embodiment of the present application further provides an on-chip S parameter measuring system, which includes the vector network analyzer and the electronic device 30 as above. The vector network analyzer is controlled by an electronic device 30.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other ways. For example, the above-described apparatus/electronic device embodiments are merely illustrative, and for example, a module or a unit may be divided into only one logic function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above may be implemented by a computer program instructing related hardware to complete, and the computer program may be stored in a computer readable storage medium, and when being executed by a processor, the computer program may implement the steps of the above method embodiments for extracting load inductance in the S parameter. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for extracting load inductance in S parameters is characterized by comprising the following steps:
acquiring a measured value of an on-chip open circuit calibration piece;
calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measurement value of the on-chip open circuit calibration piece on the basis of a first predetermined relational expression;
and calibrating the tested piece according to the current load inductance of the on-chip load calibration piece.
2. The method for extracting load inductance on-chip S parameter according to claim 1,
the first relation comprises at least one of:
the first on-chip open-circuit relationship is:
wherein L is load,open,1 Representing the present load inductance, R, of an on-chip load calibration piece extracted at a first port using said on-chip open calibration piece 1,load Representing a load resistance value, real (Z), of said on-chip load calibration member at said first port 1,app,open ) Real part, imag (Z) representing a first open measurement of said on-chip open calibration at said first port 1,app,open ) Represents the imaginary part of the first open-circuit measurement, w =2 π f, f represents the frequency of an on-chip S parameter measurement system;
the second on-chip open-circuit relationship is:
wherein L is load,open,2 Representing the present load inductance, R, of an on-chip load calibration element taken at the second port using an on-chip open calibration element 2,load Representing a load resistance value, real (Z), of said on-chip load calibration member at said second port 2,app,open ) Real part, imag (Z) representing a second open measurement of said on-chip open calibration at said second port 2,app,open ) Represents an imaginary part of the second open measurement.
3. The method for extracting load inductance according to claim 2, wherein the calculating the current load inductance of the on-chip load calibration piece comprises:
will L load,open,1 As the current load inductance of the on-chip load calibration piece, or L load,open,2 As the current load inductance of the on-chip load calibration piece, or calculating L load,open,1 And L load,open,2 And taking the average as the current load inductance of the on-chip load calibration piece.
4. The method for extracting load inductance at S-parameters of claim 1, wherein after obtaining the measurement values at the open-chip calibration, the method further comprises:
acquiring a measured value of an on-chip short circuit calibration piece;
correspondingly, the calculating the current load inductance of the on-chip load calibration part according to the load resistance value of the on-chip load calibration part and the measurement value of the on-chip open circuit calibration part based on the predetermined first relation comprises:
and calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece, the measurement value of the on-chip open circuit calibration piece and the measurement value of the on-chip short circuit calibration piece based on the first relational expression and a second relational expression which is predetermined.
5. The method for extracting load inductance in S parameters on a chip according to claim 4,
the second relationship includes at least one of:
the first on-chip short-circuit relation is:
wherein L is load,short,1 Representing a present load inductance, R, of an on-chip load calibration element taken at a first port using said on-chip short calibration element 1,load Representing a load resistance value, real (Z), of said on-chip load calibration member at said first port 1,app,short ) Real part, imag (Z) representing a first short measurement at said first port of said on-chip short calibration means 1,app,short ) Represents the imaginary part of the first short circuit measurement value, w =2 pi f, f represents the frequency of the on-chip S parameter measurement system;
the second on-chip short-circuit relation is:
wherein L is load,short,2 Representing the present load inductance, R, of an on-chip load calibration element taken at the second port using the on-chip short calibration element 2,load Representing a load resistance value, real (Z), of said on-chip load calibration member at said second port 2,app,short ) Real part, imag (Z), representing a second short circuit measurement of said on-chip short circuit calibration member at said second port 2,app,short ) Representing an imaginary part of the second short circuit measurement.
6. The method for extracting load inductance according to any one of claims 1 to 5, wherein the obtaining of the measurement value of the on-chip open circuit calibration piece comprises:
respectively measuring an on-chip load calibration piece, the on-chip open circuit calibration piece and an on-chip short circuit calibration piece by using an on-chip S parameter measurement system to obtain an on-chip load S parameter, an on-chip open circuit S parameter and an on-chip short circuit S parameter;
calculating initial eight errors of the on-chip S parameter measuring system according to the on-chip load S parameter, the on-chip open circuit S parameter and the on-chip short circuit S parameter;
and calculating the measurement value of the on-chip open circuit calibration piece according to the initial eight errors.
7. The method for extracting load inductance according to the on-chip S parameter of claim 6, wherein the calibrating the piece to be tested according to the current load inductance of the on-chip load calibration piece comprises:
calculating eight correction errors of the on-chip S parameter measuring system based on the current load inductance of the on-chip load calibration piece;
and calibrating the tested piece according to the eight corrected errors.
8. An apparatus for extracting load inductance in S-parameters, comprising:
the first acquisition module is used for acquiring the measured value of the on-chip open circuit calibration piece;
the first calculation module is used for calculating the current load inductance of the on-chip load calibration piece according to the load resistance value of the on-chip load calibration piece and the measurement value of the on-chip open-circuit calibration piece on the basis of a first predetermined relational expression;
and the calibration module is used for calibrating the tested piece according to the current load inductance of the on-chip load calibration piece.
9. An electronic device comprising a memory and a processor, the memory having stored therein a computer program operable on the processor, wherein the processor when executing the computer program implements the steps of the method of extracting load inductance at S-parameters as claimed in any of the preceding claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method of extracting load inductance at a S-parameter as claimed in any one of the claims 1 to 7 above.
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