CN116110990A - 一种基于soi结构的雪崩光电二极管器件及其制备方法 - Google Patents
一种基于soi结构的雪崩光电二极管器件及其制备方法 Download PDFInfo
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Abstract
本发明公开一种基于SOI结构的雪崩光电二极管器件及其制备方法。该基于SOI结构的雪崩光电二极管器件包括：SOI衬底，其包括背衬底、埋氧化层和顶层硅；在顶层硅中形成有P‑区，在P‑区上部的一侧形成P+区，在P‑区上部的另一侧形成有N+区，以及邻接N+区且位于P+区和N+区间的P区；源极和漏极，分别形成在顶层硅的P+区和N+区上方，并与之相接触；氧化层，覆盖除源极和漏极外的顶层硅表面。通过在N+区附近增加了浅p阱区，消除了由曲率效应引起的边缘击穿现象，同时保证了侧向PN+结发生雪崩倍增，实现了吸收区和倍增区分离。
Description
技术领域
本发明涉及半导体技术领域，具体涉及一种基于SOI结构的雪崩光电二极管器件及其制备方法。
背景技术
雪崩光电二极管(APD)是利用半导体中载流子的雪崩倍增效应(强电场作用下)放大弱光信号并提高检测灵敏度的光电转换器件。目前，APD由于具有内部增益和高速的优点，常被用作低功率光信号的理想检测器。
与其他类型的APD如4H-SiC APD和GaN APD相比，Si-APD由于成本低、全光谱波长的高检出率和良好的互补金属氧化物半导体(CMOS)工艺兼容性，在3D成像、雷达测距和光通信等应用中更受欢迎。
目前Si-APD通常采用平面器件结构，将不同的离子注入到体硅中形成p-n结。然而，这将引入p-n结的球形边界或圆柱形边界边缘，导致早期边缘击穿，降低APD稳定性。
发明内容
本发明提出了一种具有横向分离吸收倍增(SAM)结构的CMOS兼容的基于SOI结构的电子注入型Si-APD器件。该基于SOI结构的雪崩光电二极管器件包括：SOI衬底，其包括背衬底、埋氧化层和顶层硅；在顶层硅中形成有P-区，在P-区上部的一侧形成P+区，在P-区上部的另一侧形成有N+区，以及邻接N+区且位于P+区和N+区间的P区；源极和漏极，分别形成在顶层硅的P+区和N+区上方，并与之相接触；氧化层，覆盖源极和漏极外的顶层硅表面。
本发明的基于SOI结构的雪崩光电二极管器件中，优选为，所述P-区的掺杂浓度为5×1016cm-3～4×1017cm-3。
本发明的基于SOI结构的雪崩光电二极管器件中，优选为，所述P+区的掺杂浓度为1×1019cm-3～5×1019cm-3，所述N+区的掺杂浓度为2×1019cm-3～9×1019cm-3。
本发明的基于SOI结构的雪崩光电二极管器件中，优选为，所述P区的掺杂浓度为4×1017cm-3～1×1018cm-3。
本发明的基于SOI结构的雪崩光电二极管器件中，优选为，所述P区的长度为50nm～200nm。
本发明还公开一种基于SOI结构的雪崩光电二极管器件制备方法，包括以下步骤：准备SOI衬底，其包括背衬底、埋氧化层和顶层硅；在顶层硅中进行离子注入形成P-区；进行离子注入在P-区上部的一侧形成P+区；进行离子注入在P-区上部的另一侧形成有N+区，进行离子注入在邻接N+区且位于P+区和N+区间形成P区；在顶层硅表面覆盖氧化层；光刻定义源漏区域，刻蚀去除源漏区域上的氧化层，随后沉积金属电极，使之分别与顶层硅的P+区和N+区相接触。
本发明的基于SOI结构的雪崩光电二极管器件制备方法中，优选为，所述P-区的掺杂浓度为5×1016cm-3～4×1017cm-3。
本发明的基于SOI结构的雪崩光电二极管器件制备方法中，优选为，所述P+区的掺杂浓度为1×1019cm-3～5×1019cm-3，所述N+区的掺杂浓度为2×1019cm-3～9×1019cm-3。
本发明的基于SOI结构的雪崩光电二极管器件制备方法中，优选为，所述P区的掺杂浓度为4×1017cm-3～1×1018cm-3。
本发明的基于SOI结构的雪崩光电二极管器件制备方法中，优选为，所述P区的长度为50nm～200nm。
有益效果：
1、在N+区附近增加了浅p阱区，消除了由曲率效应引起的边缘击穿现象，同时保证了侧向PN+结发生雪崩倍增，实现了吸收区和倍增区分离。
2、与基于正本负极(PIN)的APD相比，该APD通过靠近阳极(带正偏置)的单一雪崩区实现了纯电子注入。
3、埋氧化层有效地阻挡了在深层衬底中产生的载流子，并保持了稳定的工作带宽。
附图说明
图1是基于SOI结构的雪崩光电二极管器件制备方法的流程图。
图2是基于SOI结构的雪崩光电二极管器件结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“垂直”“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
图1是基于SOI结构的雪崩光电二极管器件制备方法的流程图。如图1所示，基于SOI结构的雪崩光电二极管器件制备方法包括以下步骤：
步骤S1，准备5μm厚的SOI衬底，包括背衬底100、埋氧化层101和顶层硅102，其中埋氧化层厚度为600nm，顶硅层厚度为300nm。采用标准CMOS工艺对顶层硅102进行蚀刻，刻蚀出硅岛。基于SOI结构的APD可以解决体硅APD结构中较大的衬底漏电流，降低响应时间并优化带宽。埋氧化层的存在使得器件的漏源寄生电容大大减小，提高了器件频率特性。同时，基于SOI结构的APD具有更小的亚阈值摆幅和高跨导，提升器件和电路速度的同时也减低了功耗。
步骤S2，然后对顶层硅102进行离子注入，掺杂浓度为1×1017cm-3，形成P-区。
步骤S3，以2.7×1019cm-3的掺杂浓度注入，在P-区上部的一侧形成P+区。随后进行离子注入，在P-区上部的另一侧形成掺杂浓度为7.5×1019cm-3N+区，以及掺杂浓度为7×1017cm-3，邻接N+区且位于P+区和N+区间的P区。在N+区附近增加了浅p阱区，消除了由曲率效应引起的边缘击穿现象，提高了器件的稳定性。
上述离子注入，P型掺杂剂主要包括硼等，N型掺杂剂主要包括磷，砷等。
步骤S4，随后在顶层硅102表面沉积氧化层103，主要包括氧化硅等。
步骤S5，通过光刻定义源漏区域，将源漏区域上的氧化层刻蚀，随后沉积金属电极104,105，形成最终的器件，如图2所示。图2中示意性的标注了器件各部分的尺寸，P+区的长度L1为150nm，P+区和N+区的间距L2为250nm，器件整体长度L3为500nm，P区的长度L4为50nm。该APD器件具有低暗电流、高响应、低击穿电压和大带宽等优点，在未来的光探测和传感领域具有广阔的应用前景。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，例如P-区的掺杂浓度可以为5×1016cm-3～4×1017cm-3。P+区的掺杂浓度可以为1×1019cm-3～5×1019cm-3，N+区的掺杂浓度可以为2×1019cm-3～9×1019cm-3。P区的掺杂浓度可以为4×1017cm-3～1×1018cm-3。P区的长度可以为50nm～200nm。此外，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。
Claims (10)
1.一种基于SOI结构的雪崩光电二极管器件，其特征在于，
包括：
SOI衬底，其包括背衬底、埋氧化层和顶层硅；
在顶层硅中形成有P-区，在P-区上部的一侧形成P+区，在P-区上部的另一侧形成有N+区，以及邻接N+区且位于P+区和N+区间的P区；
源极和漏极，分别形成在顶层硅的P+区和N+区上方，并与之相接触；
氧化层，覆盖除源极和漏极外的顶层硅表面。
2.根据权利要求1所述的基于SOI结构的雪崩光电二极管器件，其特征在于，
所述P-区的掺杂浓度为5×1016cm-3～4×1017cm-3。
3.根据权利要求1所述的基于SOI结构的雪崩光电二极管器件，其特征在于，
所述P+区的掺杂浓度为1×1019cm-3～5×1019cm-3，所述N+区的掺杂浓度为2×1019cm-3～9×1019cm-3。
4.根据权利要求1所述的基于SOI结构的雪崩光电二极管器件，其特征在于，
所述P区的掺杂浓度为4×1017cm-3～1×1018cm-3。
5.根据权利要求1所述的基于SOI结构的雪崩光电二极管器件，其特征在于，
所述P区的长度为50nm～200nm。
6.一种基于SOI结构的雪崩光电二极管器件制备方法，其特征在于，
包括以下步骤：
准备SOI衬底，其包括背衬底、埋氧化层和顶层硅；
在顶层硅中进行离子注入形成P-区；
进行离子注入在P-区上部的一侧形成P+区；
进行离子注入在P-区上部的另一侧形成有N+区，
进行离子注入在邻接N+区且位于P+区和N+区间形成P区；
在顶层硅表面覆盖氧化层；
光刻定义源漏区域，刻蚀去除源漏区域上的氧化层，随后沉积金属电极，使之分别与顶层硅的P+区和N+区相接触。
7.根据权利要求6所述的基于SOI结构的雪崩光电二极管器件制备方法，其特征在于，
所述P-区的掺杂浓度为5×1016cm-3～4×1017cm-3。
8.根据权利要求6所述的基于SOI结构的雪崩光电二极管器件制备方法，其特征在于，
所述P+区的掺杂浓度为1×1019cm-3～5×1019cm-3，所述N+区的掺杂浓度为2×1019cm-3～9×1019cm-3。
9.根据权利要求6所述的基于SOI结构的雪崩光电二极管器件制备方法，其特征在于，
所述P区的掺杂浓度为4×1017cm-3～1×1018cm-3。
10.根据权利要求6所述的基于SOI结构的雪崩光电二极管器件制备方法，其特征在于，
所述P区的长度为50nm～200nm。
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