CN116093056A - 三维封装结构和方法 - Google Patents

三维封装结构和方法 Download PDF

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CN116093056A
CN116093056A CN202210745651.8A CN202210745651A CN116093056A CN 116093056 A CN116093056 A CN 116093056A CN 202210745651 A CN202210745651 A CN 202210745651A CN 116093056 A CN116093056 A CN 116093056A
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support layer
upper plate
integrated circuit
circuit die
package structure
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蒋航
姜剑
韩笛
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本申请公开了一种三维封装结构和方法。所述三维封装结构包括：支撑层，包含有金属线；第一磁性层，附着于支撑层的第一表面；上板，被堆叠在支撑层之上；第一磁性层，附着于支撑层的第二表面和上板之间，其中所述支撑层的第一表面和第二表面互为对立面；集成电路裸片，被堆叠在上板之上，所述集成电路裸片包含有稳压器。所述三维封装结构和方法加大了功率输出量、弱化了辐射、并显著减小了封装尺寸。

Description

三维封装结构和方法
技术领域
本发明涉及一种半导体封装，更具体地说，本发明涉及一种三维封装结构和方法。
背景技术
隔离功率模块封装包含变压器、集成电路裸片、电容及其他元器件。其中集成电路裸片里集成有稳压器，并与变压器并排放置在印制电路板上，使得封装尺寸变大。此外，变压器通常采用无磁铁的空气变压器，该变压器在功率等级和电磁干扰(EMI)性能方面均较差。
因此，本领域一直致力于提供更好的封装结构以解决上述问题。
发明内容
因此本发明的目的在于解决现有技术的上述技术问题，提出一种三维封装结构，包括：支撑层，包含有金属线；第一磁性层，附着于支撑层的第一表面；上板，被堆叠在支撑层之上；第一磁性层，附着于支撑层的第二表面和上板之间，其中所述支撑层的第一表面和第二表面互为对立面；集成电路裸片，被堆叠在上板之上，所述集成电路裸片包含有稳压器。
根据本发明的实施例，还提出了一种三维封装结构，包括：支撑层，包含有金属线；第一磁性层和第二磁性层，分别附着于支撑层的第一表面和第二表面，所述第一表面和第二表面互为对立面；集成电路裸片，装配在第一磁性层之上，所述集成电路裸片包含有稳压器。
根据本发明的实施例，还提出了一种三维封装方法，包括：将第一磁性层附着于支撑层的第一表面，所述支撑层包含有金属线；将第二磁性层附着于支撑层的第二表面和上板之间，其中上板被堆叠在支撑层之上，支撑层的第一表面和第二表面互为对立面；将集成电路裸片堆叠在上板之上，所述集成电路裸片包含有稳压器；将其他无源器件装配在上板之上。
根据本发明各方面的上述三维封装结构和方法，加大了功率输出量、弱化了辐射、并显著减小了封装尺寸。
附图说明
图1为根据本发明实施例的三维封装结构100的结构示意图；
图2为根据本发明实施例的三维封装结构200的结构示意图；
图3为根据本发明实施例的三维封装结构300的结构示意图；
图4示意性示出了根据本发明实施例的三维封装方法的流程图400。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。应当理解，当称元件“耦接到”或“连接到”另一元件时，它可以是直接耦接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接耦接到”或“直接连接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1为根据本发明实施例的三维封装结构100的结构示意图。在图1所示实施例中，所述三维封装结构100包括：支撑层103，包含金属线(如图1虚线所示的铜线)110；第一磁性层101和第二磁性层102，分别附着于支撑层103的第一表面1031和第二表面1032；集成电路裸片104，被装配在第一磁性层101之上，所述集成电路裸片104包含有稳压器。其中第一表面1031和第二表面1032互为对立面，即第一表面1031与第二表面1032相对。
本领域的技术人员应当意识到，本发明所谓的三维通常指x、y、z三个方向的空间维度。
在本发明的一个实施例中，第一磁性层101和第二磁性层102可经由粘胶层附着于支撑层103。在本发明的另一个实施例中，第一磁性层101和第二磁性层102被嵌入支撑层103。
在本发明的一个实施例中，封装结构100被装配在引线框120上，如，支撑层103和集成电路裸片104通过键合线耦接至引线框120。
在本发明的一个实施例中，支撑层103包括多个层，如支撑层103可以包括一个多层基片。
图2为根据本发明实施例的三维封装结构200的结构示意图。在图2所示实施例中，所述三维封装结构200包括：支撑层103，包含金属线110；第一磁性层101，附着于支撑层103的第一表面；上板105，被堆叠在支撑层103之上；第二表面102，附着于支撑层103的第二表面1032和上板105之间；集成电路裸片104，被堆叠在上板105之上，所述集成电路裸片104包含有稳压器。其中支撑层103的第一表面1031和第二表面1032互为对立面，即第一表面1031与第二表面1032相对。
在本发明的一个实施例中，上板105包括多个层，如上板105可以包括一个多层基片。
在本发明的一个实施例中，集成电路裸片104可包括倒装晶片，经由金属接触(如焊料凸块)电耦接至上板105。
在本发明的一个实施例中，支撑层103可包括基板，金属线可嵌入在基板里面。
在图2所示实施例中，上板105经过键合线电耦接至支撑层103和引线框120。
在本发明的实施例中，集成电路裸片104可包含其他类型的封装，如集成电路裸片可具有球栅阵列封装(BGA)、或面栅阵列封装(LGA)、或方形扁平无引脚封装(QFN)、或芯片级封装(CSP)。
图3为根据本发明实施例的三维封装结构300的结构示意图。图3所示三维封装结构300与图2所示三维封装结构200相似，与图2所述三维封装结构200不同的是，在图3所示实施例中，集成电路裸片104经由键合线耦接至上板105、支撑层103和引线框120。
在图2和图3所示实施例中，其他无源器件(如电容)被装配在上板105之上。
图4示意性示出了根据本发明实施例的三维封装方法的流程图400。所述方法包括：
步骤401，将第一磁性层附着于支撑层的第一表面，所述支撑层包含有金属线。
步骤402，将第二磁性层附着于支撑层的第二表面和上板之间，其中上板被堆叠在支撑层之上，支撑层的第一表面和第二表面互为对立面。
步骤403，将集成电路裸片堆叠在上板之上，所述集成电路裸片包含有稳压器。
步骤404，将其他无源器件装配在上板之上。
在本发明的实施例中，所述方法还包括：将封装装配在引线框上。
在本发明的一个实施例中，所述集成电路裸片包括倒装晶片，通过金属接触电耦接至上板；所述支撑层和上板经由键合线电耦接至引线框。
在本发明的另一个实施例中，所述集成电路裸片经由键合线电耦接至上板、支撑层和引线框。
在本发明的一个实施例中，支撑层和上板可包括多个层，金属线可嵌入进支撑层。
前述根据本发明多个实施例的三维封装结构提供了更好的变压器设计。不同于现有技术，前述根据本发明多个实施例的三维封装结构，其金属线在上下两个方向均被磁性层覆盖，该结构形成了有效的变压器。因此，功率输出量得到加倍，变压器绕组的辐射被弱化。此外，由于集成电路裸片、支撑层、磁性层和上板在垂直方向上堆叠在一起，因此封装尺寸被显著减小。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (9)

1.一种三维封装结构，包括：
支撑层，包含有金属线；
第一磁性层，附着于支撑层的第一表面；
上板，被堆叠在支撑层之上；
第一磁性层，附着于支撑层的第二表面和上板之间，其中所述支撑层的第一表面和第二表面互为对立面；
集成电路裸片，被堆叠在上板之上，所述集成电路裸片包含有稳压器。
2.如权利要求1所述的三维封装结构，其中：
所述支撑层包括基板；
所述金属线被嵌入进所述基板内。
3.如权利要求1所述的三维封装结构，其中：
所述集成电路裸片包括倒装晶片，经由金属接触电耦接至上板。
4.如权利要求1所述的三维封装结构，其中：
所述封装结构被装配在引线框上；
所述上板经由键合线电耦接至支撑层和引线框。
5.如权利要求1所述的三维封装结构，其中：
所述集成电路裸片经由键合线电耦接至上板、支撑层和引线框。
6.一种三维封装结构，包括：
支撑层，包含有金属线；
第一磁性层和第二磁性层，分别附着于支撑层的第一表面和第二表面，所述第一表面和第二表面互为对立面；
集成电路裸片，装配在第一磁性层之上，所述集成电路裸片包含有稳压器。
7.如权利要求6所述的三维封装结构，其中：
所述支撑层包括基板；
所述金属线被嵌入进基板。
8.一种三维封装方法，包括：
将第一磁性层附着于支撑层的第一表面，所述支撑层包含有金属线；
将第二磁性层附着于支撑层的第二表面和上板之间，其中上板被堆叠在支撑层之上，支撑层的第一表面和第二表面互为对立面；
将集成电路裸片堆叠在上板之上，所述集成电路裸片包含有稳压器；
将其他无源器件装配在上板之上。
9.如权利要求8所述的三维封装方法，进一步包括：
将封装装配在引线框上；其中：所述集成电路裸片包括倒装晶片，经由金属接触电耦接至上板；所述支撑层和上板经由键合线电耦接至引线框。
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