CN116093050A - Semiconductor substrate structure and device - Google Patents

Semiconductor substrate structure and device Download PDF

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Publication number
CN116093050A
CN116093050A CN202211104825.9A CN202211104825A CN116093050A CN 116093050 A CN116093050 A CN 116093050A CN 202211104825 A CN202211104825 A CN 202211104825A CN 116093050 A CN116093050 A CN 116093050A
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Prior art keywords
substrate
insulating layer
semiconductor
base structure
combination
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CN202211104825.9A
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Chinese (zh)
Inventor
武震宇
王栎皓
苏泳全
刘艺晨
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Priority to CN202211104825.9A priority Critical patent/CN116093050A/en
Priority to PCT/CN2023/072523 priority patent/WO2024051066A1/en
Publication of CN116093050A publication Critical patent/CN116093050A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor base structure and a device, which comprise a substrate, a conductive column, a transverse insulating layer and a vertical insulating layer, wherein vertical electrical conduction can be realized through the conductive column, and electrical insulation can be realized through the transverse insulating layer and the vertical insulating layer; the semiconductor substrate structure can realize 3D interconnection, has the advantages of strong process compatibility, flexible design, suitability for high-temperature processes and the like, can be used as a substrate structure of an integrated circuit device, can realize isolation among circuit element structures, reduce parasitic capacitance among transistors or leads, and can enhance the irradiation resistance of the device; the method can also be used for designing MEMS devices, realizing the electrical extraction of the devices, simplifying the packaging structure of the devices and enhancing the array capability of the devices; the method can also be used for a CMOS-MEMS monolithic integrated device, for example, to improve the device integration level, reduce crosstalk between an IC circuit and the MEMS device and improve the substrate utilization rate.

Description

Semiconductor substrate structure and device
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a semiconductor substrate structure and a device.
Background
In the semiconductor field, a single crystal silicon material is generally used as a substrate, and various semiconductor devices are manufactured based on the single crystal silicon substrate. However, single crystal silicon substrates have some technical limitations, and thus, silicon on insulator (Silicon on Insulator, SOI) substrates have been widely used as a functional type substrate because they have an intermediate insulating layer, which can provide an electrical isolation layer in an IC integrated circuit, reduce leakage current of a device, strengthen irradiation characteristics of a device, and provide an etch stop layer in MEMS processes, increase process uniformity, and the like. However, the conventional SOI substrate includes only a horizontal insulating layer, and cannot be electrically conducted in the vertical direction.
With the increase of the integration level of semiconductor devices, more and more semiconductor devices need to be electrically interconnected vertically, that is, elements or structures located on both sides of a substrate need to be electrically interconnected through the substrate itself. Conventional vertical electrical interconnection is typically implemented using a through silicon via (Through Silicon Vias, TSV) substrate. However, the existing through-silicon-via technology is mostly realized by means of deep hole etching and metal electroplating filling on a substrate, and the through-silicon-via substrate is only suitable for a low-temperature process below 500 ℃, is mostly used as an electrical packaging substrate, and cannot be compatible with a previous high-temperature process above 700 ℃; and secondly, the structure only comprises vertical insulation and conduction structures, and the structure does not have the advantage of an SOI substrate.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor base structure and a device for solving the problem of limitation of substrate application in the prior art.
To achieve the above and other related objects, the present invention provides a semiconductor base structure comprising:
a substrate comprising a first face and an opposing second face;
the conductive column penetrates from the first surface of the substrate to the second surface of the substrate;
the transverse insulating layers are positioned in the substrate and are distributed at intervals or continuously along the transverse direction of the substrate;
the vertical insulating layers are located in the substrate, are distributed along the vertical intervals of the substrate, penetrate through the first surface of the substrate to the second surface of the substrate and are located on the periphery of the conductive column, and a space is reserved between the vertical insulating layers and the transverse insulating layers.
Optionally, the material of the conductive column comprises one or a combination of monocrystalline silicon, polycrystalline silicon, silicon dioxide and silicon nitride; the resistivity of the conductive column is less than 5×10 -3 Ω·cm。
Optionally, the material of the substrate comprises one or a combination of monocrystalline silicon, polycrystalline silicon, silicon carbide, diamond, and a iii-v semiconductor; the thickness of the substrate comprises 100-800 mu m.
Optionally, an included angle between the lateral insulating layer and the vertical insulating layer includes 30 ° to 150 °.
Optionally, the shape of the cross section of the conductive post includes one or a combination of a circle, an ellipse, an arc, and a polygon; the shape of the cross section of the transverse insulating layer comprises one or a combination of a circle, an ellipse, an arc and a polygon; the shape of the cross section of the vertical insulating layer comprises one or a combination of a circle, an ellipse, an arc and a polygon.
Optionally, the material of the lateral insulating layer includes one or a combination of oxide, nitride, carbide and polymer; the vertical insulating layer is made of one or a combination of oxide, nitride, carbide and polymer; wherein the oxide comprises silicon oxide, the nitride comprises silicon nitride, and the carbide comprises silicon carbide.
Optionally, the process temperature for the semiconductor base structure comprises 25 ℃ to 1200 ℃.
Optionally, in any of the above semiconductor substrate structures, the lateral insulating layer is formed by a combination of an insulating dielectric housing and a cavity.
The invention also provides a semiconductor device comprising any of the above semiconductor base structures.
Optionally, the semiconductor device comprises one or a combination of a MEMS device or an integrated circuit device.
As described above, the semiconductor base structure of the present invention includes the substrate, the conductive pillars through which vertical electrical conduction at the upper and lower surfaces of the substrate can be achieved, the conductive pillars through which isolation of the element structure at the upper and lower surfaces of the substrate can be achieved, and the vertical insulating layer through which the conductive pillars can be electrically isolated from the substrate.
The semiconductor substrate structure can realize 3D interconnection, has the advantages of strong process compatibility, flexible design, suitability for high-temperature processes and the like, can be used as a substrate structure of an integrated circuit device, such as CMOS, so as to realize isolation among element structures in a circuit, reduce parasitic capacitance among transistors or leads, and enhance the irradiation resistance of the device; the method can also be used for designing MEMS devices, realizing the electrical extraction of the devices, simplifying the packaging structure of the devices and enhancing the array capability of the devices; the method can also be used for a CMOS-MEMS monolithic integrated device, for example, to improve the device integration level, reduce crosstalk between an IC circuit and the MEMS device and improve the substrate utilization rate.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor substrate structure according to a first embodiment of the present invention.
Fig. 2 is a schematic top view of a portion of the semiconductor substrate structure of fig. 1.
Fig. 3 is a schematic diagram of another partial top view of the semiconductor substrate structure of fig. 1.
Fig. 4 is a schematic structural diagram of a semiconductor substrate structure according to a second embodiment of the invention.
Fig. 5 is a schematic structural diagram of an integrated circuit device according to a third embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a MEMS device according to a fourth embodiment of the present invention.
Description of element reference numerals
100. Substrate and method for manufacturing the same
101. Lateral insulating layer
1011. Insulating medium shell
1012. Cavity cavity
102. Conductive column
103. Vertical insulating layer
110. Integrated circuit element
111. First MEMS element
112. Second MEMS element
113. Rewiring layer
114. Electrical extraction electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In this regard, when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Such as "between … …" may be used herein, the expression including both end values, and such as "a plurality" may be used, the expression indicating two or more, unless specifically defined otherwise. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Example 1
Referring to fig. 1, the present embodiment provides a semiconductor base structure, which includes a substrate 100, a lateral insulating layer 101, a conductive pillar 102, and a vertical insulating layer 103.
Wherein the substrate 100 includes a first face and an opposite second face; the conductive posts 102 penetrate from the first surface of the substrate 100 to the second surface of the substrate 100 to expose opposite ends of the conductive posts 102, so that vertical electrical conduction between the upper and lower surfaces of the substrate 100 can be realized through the conductive posts 102; the lateral insulating layers 101 are located in the substrate 100, and are arranged at intervals along the lateral direction of the substrate 100 as shown in fig. 2, or are arranged continuously along the lateral direction of the substrate 100 as shown in fig. 3, and the lateral insulating layers 101 can be used to isolate the element structures on the upper and lower surfaces of the substrate 100, and can define the distance between the lateral insulating layers 101 and the upper and lower surfaces of the substrate 100; the vertical insulating layers 103 are located in the substrate 100, are arranged along the vertical interval of the substrate 100, penetrate from the first surface of the substrate 100 to the second surface of the substrate 100, and encircle the periphery of the conductive column 102, and through the vertical insulating layers 103, the electrical insulation between the conductive column 102 and the substrate 100 can be realized, and the vertical insulating layers 103 and the transverse insulating layers 101 have a space therebetween, that is, the transverse insulating layers 101 and the vertical insulating layers 103 are mutually independent and are arranged in a non-contact manner, so that the semiconductor substrate structure has good mechanical properties and electrical properties.
By way of example, the material of the substrate 100 may include one or a combination of single crystal silicon, polycrystalline silicon, silicon carbide, diamond, and a group iii-v semiconductor.
Specifically, the material of the substrate 100 may be selected according to the need, for example, the substrate 100 may be a single-layer substrate, such as any one of a single-crystal silicon substrate, a polycrystalline silicon substrate, a silicon carbide substrate, a diamond substrate, and a iii-v semiconductor substrate, or the substrate 100 may be a composite laminated substrate, that is, a stacked combination of two or more layers of different materials, where the thickness of the substrate 100 is preferably 100 μm to 800 μm, such as 100 μm, 200 μm, 400 μm, 600 μm, 800 μm, etc., and the specific material and structure of the substrate 100 may be selected according to the need, and are not limited herein excessively.
As an example, the material of the lateral insulating layer 101 may include one or a combination of oxide, nitride, carbide, and polymer; the material of the vertical insulating layer 103 may include one or a combination of oxide, nitride, carbide, and polymer; wherein the oxide may comprise silicon oxide, the nitride may comprise silicon nitride, and the carbide may comprise silicon carbide.
Specifically, the material of the lateral insulating layer 101 may be the same as or different from the material of the vertical insulating layer 103, which is not limited herein. The specific types, sizes, distributions and morphologies of the lateral insulating layer 101 and the vertical insulating layer 103 may be selected according to needs, and are not excessively limited herein.
As an example, the included angle between the lateral insulating layer 101 and the vertical insulating layer 103 includes 30 ° to 150 °.
Specifically, in order to shorten the transmission path and reduce the loss, it is preferable that the lateral insulating layer 101 is disposed along the horizontal direction of the substrate 100, and the vertical insulating layer 103 is disposed vertically to the lateral insulating layer 101, so that a vertical included angle is formed between the lateral insulating layer 101 and the vertical insulating layer 103, but not limited thereto, and the included angle between the lateral insulating layer 101 and the vertical insulating layer 103 may be, for example, 30 °, 45 °, 60 °, 135 °, 150 ° or the like, as required, so as to provide a flexible and changeable semiconductor substrate for 3D interconnection, and the value of the included angle between the lateral insulating layer 101 and the vertical insulating layer 103 is not excessively limited herein.
As an example, the material of the conductive pillars 102 may include one or a combination of single crystal silicon, polysilicon, silicon dioxide, and silicon nitride; wherein the resistivity of the conductive pillars 102 is less than 5×10 -3 Ω·cm。
Specifically, the material of the conductive pillars 102 is selected to be doped with a silicon-based material, so as to provide the conductive pillars 102 with a low resistivity for electrical connection, wherein the resistivity of the conductive pillars 102 is preferably less than 5×10 -3 Omega cm, e.g. 4.5X10 -3 Ω·cm、2×10 -3 Ω·cm、1×10 -3 Omega cm, etc. The conductive pillars 102 are made of doped silicon-based material, not metal, such as copper, and can make the semiconductor substrate structure have a larger temperature application range on the basis of satisfying the electrical connection, so that the semiconductor substrate structure is suitable for a high-temperature environment, such as a processing process above 700 ℃ in a semiconductor process, for example, the processing environment is 700 ℃, 800 ℃, 900 ℃, 1000 ℃, 1200 ℃, etc., and the semiconductor substrate structure can be suitable for a normal-temperature or low-temperature environment, such as 25 ℃, 100 ℃, 200 ℃, 400 ℃, 500 ℃, 600 ℃, etc.
As an example, the shape of the cross-section of the conductive post 102 may include one or a combination of a circle, an ellipse, an arc, and a polygon; the shape of the cross section of the lateral insulating layer 101 may include one or a combination of a circle, an ellipse, an arc, and a polygon; the shape of the cross section of the vertical insulating layer 103 may include one or a combination of a circle, an ellipse, an arc, and a polygon.
Specifically, as shown in fig. 2 and 3, the cross-section of the conductive pillar 102 may be circular, elliptical, arc-shaped, triangular, quadrilateral, hexagonal, etc. as required; similarly, the cross-sectional shape of the lateral insulating layer 101 may include a circle, an ellipse, an arc, a triangle, a quadrangle, a hexagon, etc.; the cross-sectional shape of the vertical insulating layer 103 may also include a circle, an ellipse, an arc, a triangle, a quadrangle, a hexagon, etc., and may be specifically selected according to the need without being excessively limited thereto. The semiconductor base structure in this embodiment can provide an isolation layer of the substrate 100 in the lateral direction through the lateral insulating layer 101, reduce leakage current of devices, strengthen irradiation characteristics of devices, and can be applied as an etching stop layer to ensure etching uniformity; the conductive pillars 102 and the vertical insulating layer 103 can expand the applicable temperature range of the semiconductor substrate structure, especially the high temperature process, while implementing vertical electrical interconnection; the lateral insulating layers 101 and the vertical insulating layers 103 that are disposed at intervals may also enable the semiconductor substrate structure to have good mechanical properties and electrical properties.
Example two
Referring to fig. 4, the present embodiment provides a semiconductor substrate structure, which is different from the first embodiment mainly in that: the lateral insulating layer 101 in the semiconductor base structure is formed by combining an insulating medium housing 1011 and a cavity 1012. In this embodiment, the materials, structures, etc. of the substrate 100, the conductive pillars 102, and the vertical insulating layer 103 in the semiconductor base structure can be referred to as embodiment one, and the description thereof is omitted herein.
The material of the insulating medium housing 1011 may be the same as that of the lateral insulating layer in the first embodiment, such as one or a combination of oxide and silicon nitride, and the oxide may include one or a combination of silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, and the like. The cavity 1012 may be a vacuum sealed cavity, and the vacuum level of the cavity 1012 may be set as desired, although the cavity 1012 may be a sealed cavity only, or an open cavity, without being excessively limited. The specific dimensions, distribution and morphology of the dielectric housing 1011 and the cavity 1012 may be selected as desired and are not overly limited herein.
The arrangement of the cavity 1012 according to the first embodiment can make the semiconductor substrate structure have a good heat dissipation channel, and can be applied to devices such as integrated circuits, e.g., CMOS and MEMS, to expand the application range of the semiconductor substrate structure.
Example III
Referring to fig. 5, the present embodiment provides a semiconductor device employing the semiconductor base structure of the first embodiment. The semiconductor device includes the semiconductor base structure, an integrated circuit element 110, such as CMOS, on a first side of the substrate 100, a re-wiring layer 113 on a second side of the substrate 100, and an electrical extraction electrode 114 electrically connected to the re-wiring layer 113, so as to perform electrical conduction in a vertical direction through the semiconductor base structure.
The type of device element provided on the semiconductor substrate structure is not limited thereto, and may be a passive element such as a resistor, a capacitor, or the like, or may be an active element such as a MEMS element, or a combination of an integrated circuit element and a MEMS element, or the like. The location of the rewiring layer 113 is not limited thereto, and the rewiring layer 113 may be disposed on the first surface of the semiconductor substrate structure or on both opposite surfaces of the semiconductor substrate structure, and may be disposed as desired.
Example IV
Referring to fig. 6, the present embodiment provides a semiconductor device employing the semiconductor substrate structure having the cavity 1012 in the second embodiment. The semiconductor device comprises the semiconductor base structure, a first MEMS element 111 and a second MEMS element 112 which are positioned on the first surface of the substrate 100, a rewiring layer 113 positioned on the second surface of the substrate 100 and an electrical extraction electrode 114 electrically connected with the rewiring layer 113, so that electrical conduction in the vertical direction is performed through the semiconductor base structure.
The type of device element disposed on the semiconductor substrate structure is not limited thereto, and may be a passive element such as a resistor, a capacitor, or the like, or may be an active element such as an integrated circuit element, or a combination of an integrated circuit element and a MEMS element, or the like. The location of the rewiring layer 113 is not limited thereto, and the rewiring layer 113 may be disposed on the first surface of the semiconductor substrate structure or on both opposite surfaces of the semiconductor substrate structure, and may be disposed as desired.
In summary, the semiconductor base structure of the present invention includes the substrate, the conductive pillars, the lateral insulating layer, and the vertical insulating layer, through which vertical electrical conduction on the upper and lower surfaces of the substrate can be achieved, through which isolation of the element structure on the upper and lower surfaces of the substrate can be achieved, and through which the conductive pillars and the substrate can be electrically isolated.
The semiconductor substrate structure can realize 3D interconnection, has the advantages of strong process compatibility, flexible design, suitability for high-temperature processes and the like, can be used as a substrate structure of an integrated circuit device, such as CMOS, so as to realize isolation among element structures in a circuit, reduce parasitic capacitance among transistors or leads, and enhance the irradiation resistance of the device; the method can also be used for designing MEMS devices, realizing the electrical extraction of the devices, simplifying the packaging structure of the devices and enhancing the array capability of the devices; the method can also be used for a CMOS-MEMS monolithic integrated device, for example, to improve the device integration level, reduce crosstalk between an IC circuit and the MEMS device and improve the substrate utilization rate.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor base structure, the semiconductor base structure comprising:
a substrate comprising a first face and an opposing second face;
the conductive column penetrates from the first surface of the substrate to the second surface of the substrate;
the transverse insulating layers are positioned in the substrate and are distributed at intervals or continuously along the transverse direction of the substrate;
the vertical insulating layers are located in the substrate, are distributed along the vertical intervals of the substrate, penetrate through the first surface of the substrate to the second surface of the substrate and are located on the periphery of the conductive column, and a space is reserved between the vertical insulating layers and the transverse insulating layers.
2. The semiconductor base structure of claim 1, wherein: the material of the conductive column comprises one or a combination of monocrystalline silicon, polycrystalline silicon, silicon dioxide and silicon nitride; the resistivity of the conductive column is less than 5×10 -3 Ω·cm。
3. The semiconductor base structure of claim 1, wherein: the material of the substrate comprises one or a combination of monocrystalline silicon, polycrystalline silicon, silicon carbide, diamond and III-V semiconductor; the thickness of the substrate comprises 100-800 mu m.
4. The semiconductor base structure of claim 1, wherein: the included angle between the transverse insulating layer and the vertical insulating layer comprises 30-150 degrees.
5. The semiconductor base structure of claim 1, wherein: the shape of the cross section of the conductive column comprises one or a combination of a circle, an ellipse, an arc and a polygon; the shape of the cross section of the transverse insulating layer comprises one or a combination of a circle, an ellipse, an arc and a polygon; the shape of the cross section of the vertical insulating layer comprises one or a combination of a circle, an ellipse, an arc and a polygon.
6. The semiconductor base structure of claim 1, wherein: the material of the transverse insulating layer comprises one or a combination of oxide, nitride, carbide and polymer; the vertical insulating layer is made of one or a combination of oxide, nitride, carbide and polymer; wherein the oxide comprises silicon oxide, the nitride comprises silicon nitride, and the carbide comprises silicon carbide.
7. The semiconductor base structure of claim 1, wherein: the process temperature suitable for the semiconductor substrate structure comprises 25-1200 ℃.
8. The semiconductor base structure according to any one of claims 1 to 7, wherein: the transverse insulating layer is formed by combining an insulating medium shell and a cavity.
9. A semiconductor device, characterized in that: the semiconductor device comprising the semiconductor base structure of any one of claims 1-8.
10. The semiconductor device according to claim 9, wherein: the semiconductor device comprises one or a combination of a MEMS device or an integrated circuit device.
CN202211104825.9A 2022-09-09 2022-09-09 Semiconductor substrate structure and device Pending CN116093050A (en)

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PCT/CN2023/072523 WO2024051066A1 (en) 2022-09-09 2023-01-17 Semiconductor substrate structure and device

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