WO2023137839A1

WO2023137839A1 - Metal interconnection layout structure and semiconductor structure

Info

Publication number: WO2023137839A1
Application number: PCT/CN2022/079738
Authority: WO
Inventors: 祖江娇
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-01-19
Filing date: 2022-03-08
Publication date: 2023-07-27
Also published as: CN116504738A

Abstract

The present invention relates to the technical field of semiconductors. Disclosed are a metal interconnection layout structure and a semiconductor structure. The metal interconnection layout structure comprises: a substrate, a functional layer and a plurality of metal layers. The functional layer is located on the substrate, and the plurality of metal layers are arranged above the substrate at intervals from each other, wherein the plurality of metal layers at least comprise two metal layers having different layout structures.

Description

Metal interconnect layout structure and semiconductor structure

This disclosure is based on the Chinese patent application with the application number 202210058162.5, the filing date is January 19, 2022, and the application name is "Metal Interconnection Layout Structure and Semiconductor Structure", and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference into this disclosure.

technical field

The disclosure relates to a metal interconnection layout structure and a semiconductor structure.

Background technique

With the continuous development of semiconductor technology, the critical dimensions of semiconductor structures are also shrinking, making it relatively difficult to increase the number of semiconductor devices in a two-dimensional semiconductor structure. Therefore, stacked packaging technology has become a method that can effectively improve the integration of semiconductor structures. Current stacked packaging technologies include chip stacking based on wire bonding, package stacking and 3D stacking based on silicon vias.

Among them, the Through-Silicon-Via (TSV) technology is a technology for realizing interconnection between chips or between wafers by forming vertical conduction channels between chips or between wafers. TSV can increase the density of chips stacked in the three-dimensional direction, reduce the overall size, and can effectively improve the chip operating speed and power consumption performance.

However, there is a large thermal expansion coefficient between the filling material in the TSV and the silicon substrate of the chip in the prior art, so a stress region will be formed in the region of the silicon substrate close to the TSV, and a semiconductor structure cannot be formed in the stress region, which will waste the area of the semiconductor structure while affecting the performance of the semiconductor structure.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a metal interconnection layout structure and a semiconductor structure.

A first aspect of the present disclosure provides a metal interconnection layout structure, including:

Substrate;

a functional layer, the functional layer being located on the substrate;

a multi-layer metal layer, the multi-layer metal layer is arranged above the substrate at intervals;

Wherein, the multi-layer metal layer includes at least two metal layers with different layout structures.

According to some embodiments of the present disclosure, the functional layer has a first hole, and the shape of the first hole includes a regular polygon.

According to some embodiments of the present disclosure, the multi-layer metal layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer sequentially disposed above the substrate from bottom to top.

According to some embodiments of the present disclosure, layout structures of the first metal layer and the fourth metal layer are the same;

The layout structures of the second metal layer and the third metal layer are different.

According to some embodiments of the present disclosure, both the first metal layer and the fourth metal layer are non-porous entire metal layers.

According to some embodiments of the present disclosure, the first metal layer includes a stacked tungsten layer and an oxide layer, and the oxide layer is disposed on a side of the tungsten layer away from the substrate.

According to some embodiments of the present disclosure, the second metal layer includes a plurality of first metal lines and connection regions extending along the first direction and arranged at intervals;

Wherein, the plurality of first metal wires passing through the connection area are electrically connected in the connection area.

According to some embodiments of the present disclosure, an orthographic projection of the first hole in the functional layer on the second metal layer is located within the connection area.

According to some embodiments of the present disclosure, the third metal layer includes a plurality of second metal lines extending along a second direction and arranged at intervals, and the second direction is orthogonal to the first direction.

According to some embodiments of the present disclosure, the second metal layer and the third metal layer are made of the same material.

According to some embodiments of the present disclosure, the metal interconnection layout structure further includes a conductive layer, and the conductive layer is located between adjacent metal layers in the multi-layer metal layers, so as to realize electrical connection between the multi-layer metal layers;

Wherein, the conductive layer includes a first conductive structure, the first conductive structure penetrates the functional layer, the substrate and the first metal layer in the multi-layer metal layer, and is connected to the second metal layer.

According to some embodiments of the present disclosure, the conductive layer further includes a second conductive structure and a third conductive structure;

Wherein, the second conductive structure connects the second metal layer and the third metal layer;

The third conductive structure connects the third metal layer and the fourth metal layer.

According to some embodiments of the present disclosure, the metal interconnection layout structure further includes an insulating layer covering the fourth metal layer, the insulating layer has a via hole, and a conductive structure electrically connected to the fourth metal layer is formed in the via hole.

A second aspect of the present disclosure provides a semiconductor structure, including the above-mentioned metal interconnection layout structure;

The semiconductor structure further includes a first conductive pad and a second conductive pad, and the metal interconnection layout structure is located between the first conductive pad and the second conductive pad and is electrically connected to the first conductive pad and the second conductive pad.

According to some embodiments of the present disclosure, the semiconductor structure further includes a static protection ring, the static protection ring is located on the periphery of the first conductive pad and is spaced apart from the first conductive pad.

According to some embodiments of the present disclosure, multiple semiconductor structures may be stacked, and the conductive pads of adjacent semiconductor structures are connected by metal bonding.

In the metal interconnection layout structure and the semiconductor structure provided by the embodiments of the present disclosure, a through-silicon via structure is formed by arranging at least two metal layers with different layout structures in the multilayer metal layer, thereby effectively improving the conductivity between the two semiconductor structures stacked up and down, making the semiconductor structure including the metal interconnection layout structure in the present disclosure lighter in weight, lower in power consumption, and improving the device performance of the metal interconnection layout structure.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some, but not all, embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

FIG. 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

Fig. 2 is a schematic diagram of a functional layer in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 3 is a schematic diagram of a first metal layer in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 4 is a cross-sectional view of a first metal layer in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 5 is a schematic diagram of a second metal layer in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 6 is a schematic diagram of a third metal layer in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 7 is a schematic diagram of a fourth metal layer in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 8 is a cross-sectional view of the first conductive structure in the metal interconnection layout structure according to an exemplary embodiment.

Fig. 9 is a schematic diagram of a second conductive structure in a metal interconnection layout structure according to an exemplary embodiment.

Fig. 10 is a schematic diagram illustrating the electrical connection between a metal interconnection layout structure and a semiconductor structure according to an exemplary embodiment.

Reference signs:

10. Substrate; 20. Functional layer;

30. The first metal layer; 40. The second metal layer;

50. The third metal layer; 60. The fourth metal layer;

70, conductive layer; 80, insulating layer;

90. Conductive structure; 100. First conductive pad;

101. The first surface; 102. The second surface;

110, the second conductive pad; 120, the static protection ring;

210, the first hole; 220, the polysilicon line;

310, tungsten layer; 320, oxide layer;

410, the first metal wire; 420, the connection area;

510. The second metal wire; 710. The first conductive structure;

720. The second conductive structure; 730. The third conductive structure;

810. Through hole; A. Metal interconnection layout structure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

The filling material in the TSV of the semiconductor structure is generally copper, and there is a large thermal expansion coefficient between the copper and the silicon substrate of the chip, which will form a stress zone in the area of the silicon substrate close to the TSV, and the semiconductor structure cannot be formed in the stress zone, which will not only affect the performance of the semiconductor structure, but also waste the area of the semiconductor structure.

In order to solve one of the above technical problems, an exemplary embodiment of the present disclosure provides a metal interconnection layout structure. As shown in FIG. 1 , FIG. 1 shows a schematic diagram of a metal interconnection layout structure provided according to an exemplary embodiment. The metal interconnection layout structure will be described below with reference to FIG. 1 to FIG. 9 .

As shown in FIG. 1 , an exemplary embodiment of the present disclosure provides a metal interconnection layout structure. The metal interconnection layout structure includes a substrate 10, a functional layer 20 and multiple metal layers.

1, the substrate 10 has a first surface 101 and a second surface 102 oppositely arranged, wherein the first surface 101 can be the top surface or the bottom surface of the substrate 10, and the second surface 102 can be the bottom surface or the top surface of the substrate 10. It should be noted that when the first surface 101 is the top surface of the substrate 10, the second surface 102 is the bottom surface of the substrate 10.

The substrate 10 can be used as a supporting component of the metal interconnection layout structure for supporting other components disposed thereon. The substrate 10 can be made of semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound. In this embodiment, the substrate 10 is made of silicon material, and the use of silicon material as the substrate 10 in this embodiment is for the convenience of those skilled in the art to understand the subsequent semiconductor structure, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.

The functional layer 20 is located on the substrate 10 . Referring to FIG. 1 , in some embodiments, the functional layer 20 can be disposed on the first surface 101 of the substrate 10 ; or, the functional layer 20 can also be disposed on the second surface 102 of the substrate 10 . Wherein, the functional layer 20 can be formed on the first surface 101 or the second surface 102 by an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process.

In this embodiment, the functional layer 20 may be formed using any conductive material, for example, the functional layer 20 may include but not limited to a polysilicon layer. It should be noted that the functional layer 20 may be a polysilicon layer of a gate structure in a semiconductor structure.

Continuing to refer to FIG. 1 , multiple metal layers are disposed above the substrate 10 at intervals. Wherein, the multi-layer metal layer includes at least two metal layers with different layout structures.

It should be noted that the metal interconnect layout structure in the present disclosure may be used to connect the substrate 10 and any metal layer in the semiconductor structure; or, the metal interconnect layout structure is used to connect two metal layers in the same semiconductor structure; or, the metal interconnect layout structure is used to connect conductive layers in two different semiconductor structures.

In this embodiment, a functional layer is disposed on the first surface of the substrate, and a multilayer metal layer is disposed on the functional layer, wherein the multilayer metal layer includes at least two metal layers with different layout structures, thereby forming a through-silicon via structure, so as to effectively improve the conductivity between the two semiconductor structures stacked up and down, so that the semiconductor structure including the metal interconnection layout structure in this embodiment is lighter in weight and lower in power consumption, and improves the device performance of the metal interconnection layout structure.

As shown in FIG. 2 , in some embodiments, the functional layer 20 has a first hole 210 , and the shape of the first hole 210 includes a regular polygon. Wherein, based on the layout design of the metal interconnection layout structure, in order to make the area provided with the first hole 210 meet the design requirements of the structural size, and at the same time, considering the exposure process of the first hole 210, the shape of the first hole 210 is designed as a regular polygon. Wherein, regular polygons may include equilateral triangles, squares, regular pentagons, regular hexagons and more.

In one example, in order to reduce the complexity of the formation process of the first hole 210, the shape of the first hole 210 is designed as a regular hexagon. It should be noted that, during the formation of the first hole 210 of the regular hexagon, for example, when the first hole 210 is formed by an etching process, the etching gas or etching solution will etch the angle between any adjacent two sides of the first hole 210 of the regular hexagon, so that the area where the first hole 210 is located is close to a full circle, so as to meet the design requirements. It is also convenient to subsequently form a conductive structure or other semiconductor devices penetrating through the first hole 210 .

It should be noted that, referring to FIGS. 1 and 2, when the functional layer 20 is a polysilicon layer, taking the direction perpendicular to the top surface of the functional layer 20 as the longitudinal section, the functional layer 20 is composed of a plurality of polysilicon lines 220 arranged at intervals along the second direction Y, and adjacent polysilicon lines 220 can be isolated by an isolation material. Wherein, referring to FIG. 2 , taking the orientation shown in the figure as an example, the second direction Y is a direction perpendicular to the front side of the substrate 10 . The isolation material may include but not limited to silicon oxide or oxynitride, such as silicon oxide, silicon dioxide, silicon oxynitride, and the like.

As shown in FIG. 1 , in some embodiments, along the third direction Z, the multilayer metal layer includes a first metal layer 30, a second metal layer 40, a third metal layer 50, and a fourth metal layer 60 disposed above the substrate 10 in sequence, and the first metal layer 30 is disposed close to the functional layer 20. Wherein, referring to FIG. 1, taking the orientation shown in the figure as an example, the third direction Z is the extending direction from the bottom surface of the substrate 10 to the top surface of the substrate 10, that is, the third direction Z is the extending direction from bottom to top.

It should be noted that the first metal layer 30, the second metal layer 40, the third metal layer 50 and the fourth metal layer 60 can all be formed by a physical vapor deposition process (such as evaporation, electroplating or sputtering, etc.), a chemical vapor deposition process or an atomic layer deposition process.

The two adjacent metal layers in the first metal layer 30, the second metal layer 40, the third metal layer 50 and the fourth metal layer 60 are electrically connected through a conductive structure to meet the conductive performance of the metal interconnection layout structure, thereby effectively increasing the device performance of the metal interconnection layout structure while reflecting the advantages of the through-silicon via structure.

As shown in FIG. 3 and FIG. 7 , in some embodiments, in order to reduce the cost of the manufacturing process of the metal interconnection layout structure and ensure good electrical connectivity between the metal interconnection layout structure and adjacent semiconductor structures or metal layers, the layout structures of the first metal layer 30 and the fourth metal layer 60 can be made the same.

Referring to FIG. 5 and FIG. 6 , the layout structures of the second metal layer 40 and the third metal layer 50 are different. In this embodiment, in order to enhance the overall structural strength of the metal interconnection layout structure, the layout structures of the second metal layer 40 and the third metal layer 50 are designed into different structures. On the other hand, the second metal layer 40 and the third metal layer 50 with different layout structures can also be matched with metal layers in other semiconductor structures to improve the applicability of the metal interconnection layout structure.

As shown in FIG. 3 and FIG. 7 , in some embodiments, both the first metal layer 30 and the fourth metal layer 60 are full-layer metal layers without holes, so as to reduce the design cost of the metal interconnection layout structure and the complexity of the manufacturing process.

Wherein, the first metal layer 30, as the first layer of metal, can be a complete layer of metal layer, that is, structures such as through holes are not reserved on the first metal layer 30, so as to improve the conductive connectivity between the first metal layer 30 and adjacent semiconductor structures or metal layers. The material of the first metal layer 30 may include, but is not limited to, titanium, tantalum, palladium, nickel, platinum, cobalt, tungsten, zirconium, molybdenum, and the like.

Continuing to refer to FIG. 3 and FIG. 7 , the fourth metal layer 60 is also a complete metal layer, so as to improve the electrical connection between the fourth metal layer 60 and adjacent semiconductor structures or metal layers. Wherein, the material of the fourth metal layer 60 may include but not limited to titanium, tantalum, palladium, nickel, platinum, cobalt, tungsten, zirconium, molybdenum and so on.

It should be noted that, in an example, the material of the first metal layer 30 and the material of the fourth metal layer 60 may be the same, so as to reduce the complexity of the manufacturing process of the metal interconnection layout structure.

As shown in FIG. 4 , in some embodiments, the first metal layer 30 includes a stacked tungsten layer 310 and an oxide layer 320 , and the oxide layer 320 is disposed on a side of the tungsten layer 310 away from the substrate 10 .

It should be noted that the tungsten layer 310 and the oxide layer 320 in this embodiment form a complete structural layer during the preparation process. In the subsequent manufacturing process, through holes for the subsequent first conductive structure to pass through can be prepared on the first metal layer 30 through an etching process, so as to ensure good connectivity between the first metal layer 30 and the subsequently prepared first conductive structure. On the other hand, in the formation process of the first metal layer 30, the tungsten layer 310 can be deposited first, and then the oxide layer 320 can be formed on the tungsten layer 310 by using the deposition process. After the first metal layer 30 is formed by the deposition process, the flatness of the top surface of the first metal layer 30 can be effectively guaranteed, and there is no need to perform a chemical mechanical polishing process on the top surface of the first metal layer 30, which saves the process cost of the metal interconnection layout structure. Among them, the deposition process includes atomic layer deposition process, physical vapor deposition process and chemical vapor deposition process.

As shown in FIG. 5 , in some embodiments, the second metal layer 40 includes a plurality of first metal lines 410 and connection regions 420 extending along the first direction X and arranged at intervals. Wherein, referring to FIG. 5 , taking the orientation shown in the figure as an example, the first direction X is a direction parallel to the front side of the substrate 10 . The material of the second metal layer 40 may include but not limited to copper, titanium, tantalum, palladium, nickel, platinum, cobalt, tungsten, zirconium, molybdenum and the like.

Wherein, the plurality of first metal wires 410 passing through the connection region 420 are electrically connected at the connection region 420 . The connection area 420 is located in the middle of the plurality of first metal lines 410 in the middle area. Moreover, the connection region 420 corresponds to the first conductive structure formed subsequently.

It should be noted that the plurality of first metal lines 410 are arranged at intervals along the first direction X, which can make the top surface of the second metal layer 40 more planar after the chemical mechanical polishing of the top surface of the second metal layer 40 is completed.

When the second metal layer 40 forms a whole-layer metal structure during the preparation process, when the top surface of the second metal layer 40 is chemically mechanically polished, the topography of the second metal layer 40 will form a plane with a depression, that is, along the extension direction of the third direction Z, the thickness at the edge of the second metal layer 40 is greater than the thickness at its center, resulting in poor flatness of the top surface of the second metal layer 40.

Therefore, in this embodiment, the second metal layer 40 is designed to have a structure of a plurality of first metal lines 410 and connection regions 420 arranged at intervals, so that the concavity in the concave plane of the entire layer structure is evenly distributed to the top surfaces of the plurality of second metal lines 410 and the top surfaces of the connection regions 420, thereby effectively improving the flatness of the top surface of the second metal layer 40 after chemical mechanical polishing, and facilitating the subsequent process steps.

Wherein, in some embodiments, the higher the arrangement density of the first metal lines 410 is, the closer the top surface of the entire second metal layer 40 is to a plane after the chemical mechanical polishing process, thereby improving the device performance and yield of the metal interconnection layout structure.

In some embodiments, the orthographic projection of the first hole 210 in the functional layer 20 on the second metal layer 40 is located in the connection region 420 . Because the connection region 420 corresponds to the first conductive structure formed subsequently, that is to say, the first hole 210 also corresponds to the first conductive structure. For example, the first conductive structure passes through the first hole 210, and the first conductive structure is used to electrically connect some metal layers in the multi-layer metal layers, thereby forming a through-silicon via structure, thereby increasing the device performance of the metal interconnection layout structure while reflecting the advantages of the through-silicon via structure.

It should be noted here that the material of the second metal layer 40 can be the same as that of the first conductive structure formed subsequently, which can reduce the difficulty of the manufacturing process of the metal interconnection layout structure on the one hand, and increase the good electrical connection performance between the second metal layer 40 and the first conductive structure on the other hand.

As shown in FIG. 6 , in some embodiments, the third metal layer 50 includes a plurality of second metal lines 510 arranged at intervals along the second direction Y. Referring to FIG. 6 , taking the orientation shown in the figure as an example, the second direction Y is a direction perpendicular to the front side of the substrate 10 . Wherein, the second direction Y is orthogonal to the first direction X.

In this embodiment, along the second direction Y, a plurality of second metal lines 510 are arranged at intervals, that is, the extending direction of the second metal lines 510 and the extending direction of the first metal lines 410 are perpendicular to each other. Therefore, the internal stress of each metal layer in the metal interconnection layout structure can be reduced during the formation process, and the connection strength of the overall structure of the metal interconnection layout structure can also be improved, thereby improving the device performance of the metal interconnection layout structure.

It should be noted here that, in some embodiments, the second direction Y and the first direction X may also intersect at a preset angle, as long as the extending direction of the second metal wire 510 is different from that of the first metal wire 410 .

On the other hand, arranging a plurality of second metal lines 510 at intervals along the second direction Y can make the top surface of the third metal layer 50 more planar after the chemical mechanical polishing of the top surface of the third metal layer 50 is completed.

When the third metal layer 50 forms a whole-layer metal structure during the preparation process, when the top surface of the third metal layer 50 is chemically mechanically polished, the topography of the third metal layer 50 will form a plane with a depression, that is, along the extension direction of the third direction Z, the thickness at the edge of the third metal layer 50 is greater than the thickness at the center thereof, resulting in poor flatness of the top surface of the third metal layer 50 .

Therefore, in this embodiment, the third metal layer 50 is designed as a plurality of second metal lines 510 arranged at intervals, so that the concavity in the concave plane of the entire layer structure is evenly distributed to the top surfaces of the plurality of third metal lines 510, thereby effectively improving the flatness of the top surface of the third metal layer 50 after chemical mechanical polishing, and facilitating subsequent process steps.

What needs to be said is that the higher the arrangement density of the second metal lines 510 is, the closer the top surface of the entire third metal layer 50 is to a plane after the chemical mechanical polishing process, which improves the device performance and yield of the metal interconnection layout structure. Wherein, the material of the third metal layer 50 may include but not limited to copper, titanium, tantalum, palladium, nickel, platinum, cobalt, tungsten, zirconium, molybdenum and the like.

As shown in FIG. 5 and FIG. 6 , in one example, the materials of the second metal layer 40 and the third metal layer 50 are the same. Using the same material to make the second metal layer 40 and the third metal layer 50 can be formed successively without changing materials, thereby reducing the manufacturing process of the metal interconnection layout structure. In the implementation process, both the second metal layer 40 and the third metal layer 50 can be made of copper metal, and the second metal layer 40 facilitates the subsequent filling and formation of the first conductive structure, thereby reducing the complexity of the manufacturing process of the metal interconnection layout structure.

In another example, the material of the second metal layer 40 and the third metal layer 50 may also be the same as that of the subsequently formed first conductive structure. For example, the second metal layer 40, the third metal layer 50 and the first conductive structure are all made of copper metal, so as to effectively reduce the difficulty of making the metal interconnection layout structure, and at the same time, ensure and provide the conductive connectivity between the above three.

As shown in FIG. 1 , in some embodiments, the metal interconnection layout structure further includes a conductive layer 70 . The conductive layer 70 is located between adjacent metal layers in the multi-layer metal layers, so as to realize the electrical connection between the multi-layer metal layers.

Wherein, in some embodiments, the conductive layer 70 includes a first conductive structure 710 . One end (such as the lower end) of the first conductive structure 710 penetrates through the functional layer 20 , the substrate 10 and the first metal layer 30 in the multi-layer metal layers. Based on this, the first conductive structure 710 cooperates with the first metal layer 30 , the substrate 10 and the functional layer 20 to form a through silicon via structure.

In the prior art, in the process of forming the TSV structure, the through-hole formed in the substrate of the semiconductor structure is filled with conductive materials, such as copper, tungsten, aluminum, etc., due to the large difference in thermal expansion coefficient between the conductive material and the substrate, it may cause serious stress effects, resulting in problems such as cracks between the TSV structure and the surrounding semiconductor structure, which greatly reduces the performance of the semiconductor structure.

Therefore, in this embodiment, the through-silicon via structure of the entire copper pillar structure in the prior art is changed to the combination form of the first conductive structure 710, the first metal layer 30, the substrate 10 and the functional layer 20 in this embodiment, so as to effectively reflect the advantages of the through-silicon via structure, improve the conductive connectivity of the structure, make the subsequent metal interconnection layout structure lighter in weight and lower power consumption, and improve the device performance of the metal interconnection layout structure.

As shown in FIG. 1 , in some embodiments, the conductive layer 70 further includes a second conductive structure 720 and a third conductive structure 730 .

Wherein, as shown in FIG. 8 , the second conductive structure 720 connects the second metal layer 40 and the third metal layer 50 , and the second conductive structure 720 is used to realize and ensure good electrical conductivity between the second metal layer 40 and the third metal layer 50 . The third conductive structure 730 connects the third metal layer 50 and the fourth metal layer 60 , and the third conductive structure 730 is used to realize and ensure good electrical conductivity between the third metal layer 50 and the fourth metal layer 60 .

It should be noted here that the second conductive structure 720 may include a plurality of first TSV structures arranged according to a first preset rule. The third conductive structure 730 may include a plurality of second TSV structures arranged according to a second preset rule. Wherein, the first preset rule may be the same as the second preset rule, for example, both are arranged in an array, or both are arranged in a circular array; or, the first preset rule is different from the second preset rule.

As shown in FIG. 1 , in some embodiments, the metal interconnection layout structure further includes an insulating layer 80 . The insulating layer 80 covers the fourth metal layer 60 , wherein, along the direction opposite to the third direction Z, the insulating layer 80 covers and wraps the top surface and the sidewall of the fourth metal layer 60 . A through hole 810 is formed on the insulating layer 80 , and a conductive structure 90 electrically connected to the fourth metal layer 60 is formed in the through hole 810 . Wherein, the material of the insulating layer 80 may include but not limited to silicon nitride, silicon dioxide, borophosphosilicate glass and the like.

In this embodiment, the fourth metal layer 60 can be well insulated and protected by the insulating layer 80 , thereby effectively ensuring the performance of the fourth metal layer 60 .

It should be noted here that, in the metal interconnection layout structure, a multi-layer isolation layer may also be provided, and the multi-layer isolation layer is used for isolating adjacent metal layers, or isolating the metal layer and the functional layer.

As shown in FIGS. 1 and 10 , an exemplary embodiment of the present disclosure provides a semiconductor structure, which includes the above-mentioned metal interconnection layout structure A (refer to the dotted line box in FIG. 10 ), a first conductive pad 100 and a second conductive pad 110 . Wherein, the metal interconnection layout structure A is located between the first conductive pad 100 and the second conductive pad 110 , and the metal interconnection layout structure is electrically connected to the first conductive pad 100 and the second conductive pad 110 respectively. The first conductive pad 100 may be disposed on the top of the metal interconnection layout structure, or the first conductive pad 100 may be disposed on the bottom end of the metal interconnection layout structure.

In this embodiment, a metal interconnection layout structure is used to electrically connect the first conductive pad and the second conductive pad, thereby forming a through-silicon via structure, so as to realize the stacking connection between two semiconductor structures (such as chips, wafers, or dies, etc.) to form a three-dimensional stacked structure, thereby making the formed semiconductor structure or three-dimensional stacked structure lighter in weight and lower in function, and improving device performance and yield of the semiconductor structure.

As shown in FIG. 1 , in some embodiments, the semiconductor structure further includes an ESD protection ring 120 . The static protection ring 120 is located on the periphery of the first conductive pad 100 , and the static protection ring 120 is spaced apart from the first conductive pad 100 . Wherein, the static protection ring 120 may include a bare copper grounding protection ring, which is used to protect the device performance of the semiconductor structure from being disturbed.

As shown in FIG. 1 and FIG. 10 , in some embodiments, multiple semiconductor structures can be stacked, and the conductive pads of adjacent semiconductor structures are connected by metal bonding.

It should be noted here that, referring to FIG. 10 , the semiconductor structure may include multiple metal layers, such as metal layer M0 , metal layer M1 , metal layer M2 and metal layer M3 . Wherein, the number of metal layers in different semiconductor structures may be the same or different. Moreover, the reference number 10 in FIG. 10 can be understood as a substrate of a metal interconnection layout structure or a substrate in a semiconductor structure.

In one example, the first conductive pad 100 of the upper semiconductor structure is connected to the second conductive pad of the lower semiconductor structure through metal bonding. Alternatively, the second conductive pad 110 of the upper semiconductor structure is connected to the first conductive pad of the lower semiconductor structure through metal bonding. Thus, a three-dimensional stacking structure is formed to realize high-density stacking in three-dimensional directions among multiple semiconductor structures, thereby improving the operating speed and power consumption performance of the chip.

Each embodiment or implementation manner in this specification is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In the description of this specification, descriptions with reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "exemplary embodiment", "example" and the like mean that specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present disclosure.

In one or more drawings, like elements are indicated with like reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of devices, are described for a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present disclosure.

Industrial Applicability

In the metal interconnection layout structure and the semiconductor structure of the embodiment of the present disclosure, at least two metal layers with different layout structures are provided in the multilayer metal layer, thereby effectively improving the conductivity between the two semiconductor structures stacked up and down, making the semiconductor structure including the metal interconnection layout structure in the present disclosure lighter in weight, lower in power consumption, and improving the device performance of the metal interconnection layout structure.

Claims

A metal interconnect layout structure, comprising:

Substrate;

a functional layer, the functional layer being located on the substrate;

a multi-layer metal layer, the multi-layer metal layer is arranged above the substrate at intervals;

Wherein, the multi-layer metal layer includes at least two metal layers with different layout structures.
The metal interconnection layout structure according to claim 1, wherein the functional layer has a first hole, and the shape of the first hole includes a regular polygon.
The metal interconnection layout structure according to claim 2, wherein the multi-layer metal layer comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer disposed above the substrate sequentially from bottom to top.
The metal interconnection layout structure according to claim 3, wherein the layout structure of the first metal layer and the fourth metal layer are the same;

The layout structures of the second metal layer and the third metal layer are different.
The metal interconnection layout structure according to claim 4, wherein both the first metal layer and the fourth metal layer are non-porous whole-layer metal layers.
The metal interconnection layout structure according to claim 4, wherein the first metal layer comprises a stacked tungsten layer and an oxide layer, and the oxide layer is disposed on a side of the tungsten layer away from the substrate.
The metal interconnection layout structure according to claim 3, wherein the second metal layer comprises a plurality of first metal lines and connection regions extending along the first direction and arranged at intervals;

Wherein, the plurality of first metal wires passing through the connection area are electrically connected in the connection area.
The metal interconnection layout structure according to claim 7, wherein the orthographic projection of the first hole in the functional layer on the second metal layer is located in the connection area.
The metal interconnection layout structure according to claim 7, wherein the third metal layer comprises a plurality of second metal lines extending along a second direction and arranged at intervals, and the second direction is orthogonal to the first direction.
The metal interconnection layout structure according to claim 3, wherein the second metal layer and the third metal layer are made of the same material.
The metal interconnect layout structure according to any one of claims 3-10, wherein the metal interconnect layout structure further comprises a conductive layer, the conductive layer is located between adjacent metal layers in the multi-layer metal layers, so as to realize electrical connection between the multi-layer metal layers;

Wherein, the conductive layer includes a first conductive structure, the first conductive structure penetrates the functional layer, the substrate and the first metal layer in the multi-layer metal layer, and is connected to the second metal layer.
The metal interconnect layout structure according to claim 11, wherein the conductive layer further comprises a second conductive structure and a third conductive structure;

Wherein, the second conductive structure connects the second metal layer and the third metal layer;

The third conductive structure connects the third metal layer and the fourth metal layer.
The metal interconnection layout structure according to claim 12, wherein the metal interconnection layout structure further comprises an insulating layer, the insulating layer covers the fourth metal layer, the insulating layer has a through hole, and a conductive structure electrically connected to the fourth metal layer is formed in the through hole.
A semiconductor structure, comprising the metal interconnection layout structure according to any one of claims 1-13;

The semiconductor structure further includes a first conductive pad and a second conductive pad, and the metal interconnection layout structure is located between the first conductive pad and the second conductive pad and is electrically connected to the first conductive pad and the second conductive pad.
The semiconductor structure according to claim 14, wherein the semiconductor structure further comprises a static protection ring, the static protection ring is located on the periphery of the first conductive pad and is spaced apart from the first conductive pad.
The semiconductor structure according to claim 14, wherein a plurality of said semiconductor structures are stacked, and the conductive pads of adjacent said semiconductor structures are connected by metal bonding.