CN107068653A - A kind of test structure of semiconductor - Google Patents
A kind of test structure of semiconductor Download PDFInfo
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- CN107068653A CN107068653A CN201710318801.6A CN201710318801A CN107068653A CN 107068653 A CN107068653 A CN 107068653A CN 201710318801 A CN201710318801 A CN 201710318801A CN 107068653 A CN107068653 A CN 107068653A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention discloses a kind of test structure of semiconductor, including semiconductor base, the first test metal level, the second test metal level, the first insulating barrier and the first conductive metal layer on the semiconductor substrate surface, silicon through hole in semiconductor base, the hole around silicon through hole and the gas vacuole in hole；The first test metal level and the second test metal interlevel are provided with the first insulating barrier；First conductive metal layer is located on the second surface of semiconductor base；Some silicon through hole are crossed in the semiconductor base, the silicon through hole includes the second insulating barrier and conductive material, and second insulating barrier is located on the side wall of silicon through hole, and the conductive material is filled to the second insulating barrier；Set around the silicon through hole in hole, described hole filled with the foster layer of silicon.The present invention not only improves the parasitic capacitance between the stability and reliability of silicon through hole, and reduction silicon through hole, improves the service behaviour of semiconductor devices.
Description
Technical field
The invention belongs to technical field of semiconductors, it is related to a kind of test structure of semiconductor.
Background technology
With continuing to develop for semiconductor technology, partly lead at present not device characteristic size oneself through becoming very small, but
In order to which to improve the integrated level of semiconductor chip, integrated level is increased using silicon through hole, have following three using silicon through hole
Individual advantage：1st, High Density Integration；2nd, the length of electrical interconnection is significantly shortened；3rd, the integrated chip with difference in functionality can be existed
Come together to realize the multi-functional of encapsulation chip.Thus, say benefit using the technology of silicon through hole stacked structure and more flowed as one kind
Capable chip encapsulation technology.
Silicon through hole is a kind of conductor structure through silicon substrate, major function be for interconnecting integrated circuit chip, its
Preparation method is generally first, in each chip book office formation vertical through hole, insulating barrier to be formed in each through hole, in insulating barrier
Upper formation crystal seed layer, then fills up metal, then expose one end of silicon through hole with brilliant back-grinding with electro-plating method by through hole
Come.Wafer after cutting, multiple IC chips can storehouse on package substrate, formed 3 D stereo chip package, warp
Realized and be connected with each other in vertical direction by silicon through hole.Chip size can be significantly reduced in this way, improve chip
Transistor density, improves interlayer electrical interconnection performance, lifts the chip speed of service, reduces the power consumption of chip.But adjacent two wear
The parasitic capacitance that can not be ignored is also easy to produce between silicon hole, the presence of parasitic capacitance largely effects on the running of semiconductor devices.
In addition, in chip testing structure, being related to annealing steps, silicon through hole structure and semiconductor base is caused to hold
By certain temperature, and in silicon through hole filling conductive material (such as copper), and semiconductor-based bottom materials (such as silicon), due to copper
Thermal coefficient of expansion be more than the thermal coefficient of expansion of silicon, cause the metal level being connected with silicon through hole to be distorted deformation, or even tear
Split, causing the reliability of semiconductor chip reduces, and performance is unstable.
In order to improve the performance of silicon through hole in semiconductor chip, a kind of test structure of semiconductor is now designed.
The content of the invention
It is an object of the invention to provide a kind of test structure of semiconductor, by being surveyed in the first test metal level and second
Examination metal interlevel is provided with insulating barrier, it is to avoid the silicon through hole caused by the thermal coefficient of expansion difference of semiconductor base and silicon through hole
Interior conductive material is flowed into semiconductor base；If by being provided with dry gas hole around silicon through hole, and in gas hole not
The full silicon of filling supports layer, to form gas vacuole, and the stability for solving silicon through hole in semiconductor chip is poor, poor reliability and work
The problem of poor performance.
The purpose of the present invention can be achieved through the following technical solutions：
A kind of test structure of semiconductor, including semiconductor base, first on the semiconductor substrate surface surveys
Metal level, the second test metal level, the first insulating barrier and the first conductive metal layer are tried, the silicon of wearing in semiconductor base leads to
Hole, the hole around silicon through hole and the gas vacuole in hole；
The first test metal level, the second test metal level and the first insulating barrier are located at the first surface of semiconductor base
On, the first test metal level and the second test metal interlevel are provided with the first insulating barrier；The first conductive metal layer position
In on the second surface of semiconductor base；
Some silicon through hole are crossed in the semiconductor base, the silicon through hole includes the second insulating barrier and conduction material
Material, second insulating barrier is located on the side wall of silicon through hole, and the conductive material is filled to the second insulating barrier；
Set around the silicon through hole in hole, described hole filled with the foster layer of silicon.
Further, the first surface and second surface of the semiconductor base are relative designs.
Further, the first test metal level is rectangular configuration, and the second test metal level is semi-closed structure
Or full-closed structure, and it is described first test metal level be arranged in the second test metal level.
Further, the thickness of first insulating barrier is less than the thickness of the first test metal level and the second test metal level
Degree.
Further, the quantity of first conductive metal layer is identical with the quantity of silicon through hole.
Further, one end of some silicon through hole is connected with first conductive metal layer respectively, described some
The other end of silicon through hole is connected with the first test metal level.
Further, the silicon supports the unfilled hole of layer so that gas vacuole, the gas vacuole cross sectional shape are formed with hole
For ellipsoidal structure.
Beneficial effects of the present invention：
The present invention is by being respectively arranged with the first test metal level and the second test metal on a surface of semiconductor base
Layer, and insulating barrier is provided between the first test metal level and the second test metal level, it can be effectively prevented from because of semiconductor
Conductive material in the silicon through hole that the thermal coefficient of expansion difference of substrate and silicon through hole is caused is flowed into semiconductor base, significantly
Improve the stability and reliability of silicon through hole；If by being provided with dry gas hole around silicon through hole, and in gas hole not
The full silicon of filling supports layer, to form gas vacuole, can not only reduce the thermal expansion of the thermal coefficient of expansion and semiconductor base of silicon through hole
Gap between coefficient, further improves the stability and reliability of silicon through hole, and can reduce posting between silicon through hole
Raw electric capacity, improves the service behaviour of semiconductor devices.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, used required for being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other attached
Figure.
Fig. 1 is a kind of test structure overall schematic of semiconductor of the invention；
Fig. 2 is the part composition schematic diagram of the test structure of semiconductor in the present invention；
Fig. 3 is the top view of the test structure of semiconductor in the present invention；
Fig. 4 is gas hole in the present invention and silicon through hole schematic diagram；
Fig. 5 is gas vacuole position view in the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is all other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Refer to shown in Fig. 1, the present invention is a kind of test structure of semiconductor, including semiconductor base 100, positioned at partly leading
The the first test test of metal level 101, second metal level 102, the first insulating barrier 103 and first on the surface of body substrate 100 is conductive
Metal level 201, the silicon through hole 300 in semiconductor base 100, hole 400 and position around silicon through hole 300
In the gas vacuole 401 in hole 400；
Semiconductor base 100 includes first surface and second surface, and first surface design relative with second surface, such as schemes
2nd, shown in 3, the first test test metal level 102 and first insulating barrier 103 of metal level 101, second is located at semiconductor base 100
On first surface, the first test metal level 101 is rectangular configuration, and the second test metal level 102 is semi-closed structure or totally-enclosed
Structure, and first test metal level 101 be arranged in the second test metal level 102, first test metal level 101 and second test
The first insulating barrier 103 is provided between metal level 102, wherein the thickness of the first insulating barrier 103 is less than the first test He of metal level 101
The thickness of second test metal level 102；First conductive metal layer 201 is located on the second surface of semiconductor base 100.
As shown in Figure 4,5, some silicon through hole 300 are crossed in semiconductor base 100, the section of silicon through hole 300 is circle
Shape, one end of some silicon through hole 300 is connected with first conductive metal layer 201 respectively, some silicon through hole 300 it is another
End is connected with the first test metal level 101, and silicon through hole 300 includes the second insulating barrier 302 and conductive material 301, and second is exhausted
Edge layer 302 is located on the side wall of silicon through hole 300, and radius of the thickness less than silicon through hole 300 of the second insulating barrier 302, leads
Electric material 301 is filled to the second insulating barrier 302.
Hole 400 is set around silicon through hole 300, it is ensured that at least one hole between adjacent two silicon through hole 300
Hole 400, increases gas permeability, and layer 402 is supported filled with silicon in hole 400, and silicon supports layer 402 and is not full of hole 400, thus
Gas vacuole 401 is formed with hole 400, wherein silica layer 402 can be formed using chemical vapor deposition method, or can profit
Formed with spin-on glasses technique, wherein, the cross sectional shape of gas vacuole 401 can be ellipsoidal structure.
In addition, according to filling perforation hole 400 can also be carried out using advanced low-k materials, also can select low-k material
The bed of material completely fills out hole 400, without forming air cell.
Silicon through hole 300, due to the processing of the high-temperature technologies such as annealing, is caused in silicon through hole 300 during making
The conductive material 301 and the expanded by heating of semiconductor base 100 in portion, the coefficient of expansion of conductive material 301 are more than semiconductor base 100
The coefficient of expansion, and then first test metal level 101 arch upward upwards, cause the first test metal level 101 and the second insulating barrier 302
Between there is gap, conductive material 301 is flowed out by gap so that the semiconductor structure exist during test leakage current show
As, meanwhile, conductive material 302 is entered in semiconductor base 100 by interstitial diffusion, is exaggerated the unstable of silicon through hole 300
Property and unreliability, in order to improve the reliability of silicon through hole 300, can first test metal level 101 and second test metal
First insulating barrier 103 is set between layer 102.
The present invention is by being respectively arranged with the first test metal level and the second test metal on a surface of semiconductor base
Layer, and insulating barrier is provided between the first test metal level and the second test metal level, it can be effectively prevented from because of semiconductor
Conductive material in the silicon through hole that the thermal coefficient of expansion difference of substrate and silicon through hole is caused is flowed into semiconductor base, significantly
Improve the stability and reliability of silicon through hole；If by being provided with dry gas hole around silicon through hole, and in gas hole not
The full silicon of filling supports layer, to form gas vacuole, can not only reduce the thermal expansion of the thermal coefficient of expansion and semiconductor base of silicon through hole
Gap between coefficient, further improves the stability and reliability of silicon through hole, and can reduce posting between silicon through hole
Raw electric capacity, improves the service behaviour of semiconductor devices.
Above content is only the design example and explanation to the present invention, affiliated those skilled in the art
Various modifications or supplement are made to described specific embodiment or is substituted using similar mode, without departing from invention
Design or surmount scope defined in the claims, protection scope of the present invention all should be belonged to.
Claims (7)
1. a kind of test structure of semiconductor, it is characterised in that：Including semiconductor base (100), positioned at the semiconductor base
(100) the first test metal level (101), the second test metal level (102), the first insulating barrier (103) and first on surface is led
Metal layer (201), the silicon through hole (300) in semiconductor base (100), the hole around silicon through hole (300)
Hole (400) and the gas vacuole (401) in hole (400)；
The first test metal level (101), the second test metal level (102) and the first insulating barrier (103) are located at semiconductor-based
On the first surface at bottom (100), first is provided between the first test metal level (101) and the second test metal level (102)
Insulating barrier (103)；First conductive metal layer (201) is located on the second surface of semiconductor base (100)；
Some silicon through hole (300) are crossed in the semiconductor base (100), the silicon through hole (300) includes the second insulation
Layer (302) and conductive material (301), second insulating barrier (302) are located on the side wall of silicon through hole (300), the conduction
In material (301) filling to the second insulating barrier (302)；
Set around the silicon through hole (300) in hole (400), described hole (400) filled with the foster layer (402) of silicon.
2. a kind of test structure of semiconductor according to claim 1, it is characterised in that：The semiconductor base (100)
First surface and second surface is relative designs.
3. a kind of test structure of semiconductor according to claim 1, it is characterised in that：The first test metal level
(101) it is rectangular configuration, described second tests metal level (102) for semi-closed structure or full-closed structure, and described first surveys
Examination metal level (101) is arranged in the second test metal level (102).
4. a kind of test structure of semiconductor according to claim 1, it is characterised in that：First insulating barrier (103)
Thickness be less than first test metal level (101) and second test metal level (102) thickness.
5. a kind of test structure of semiconductor according to claim 1, it is characterised in that：First conductive metal layer
(201) quantity is identical with the quantity of silicon through hole (300).
6. a kind of test structure of semiconductor according to claim 1, it is characterised in that：Some silicon through hole
(300) one end is connected with first conductive metal layer (201) respectively, and the other end of some silicon through hole (300) is equal
It is connected with the first test metal level (101).
7. a kind of test structure of semiconductor according to claim 1, it is characterised in that：The silicon is supported layer (402) and not filled out
Full hole (400) so that gas vacuole (401) is formed with hole (400), gas vacuole (401) cross sectional shape is tied for ellipse
Structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710318801.6A CN107068653A (en) | 2017-05-08 | 2017-05-08 | A kind of test structure of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710318801.6A CN107068653A (en) | 2017-05-08 | 2017-05-08 | A kind of test structure of semiconductor |
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| CN107068653A true CN107068653A (en) | 2017-08-18 |
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| CN201710318801.6A Pending CN107068653A (en) | 2017-05-08 | 2017-05-08 | A kind of test structure of semiconductor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113241335A (en) * | 2021-04-07 | 2021-08-10 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367280A (en) * | 2012-03-26 | 2013-10-23 | 南亚科技股份有限公司 | Through silicon via structure and manufacture method thereof |
| CN105206600A (en) * | 2014-06-30 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure |
-
2017
- 2017-05-08 CN CN201710318801.6A patent/CN107068653A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367280A (en) * | 2012-03-26 | 2013-10-23 | 南亚科技股份有限公司 | Through silicon via structure and manufacture method thereof |
| CN105206600A (en) * | 2014-06-30 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113241335A (en) * | 2021-04-07 | 2021-08-10 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and semiconductor device |
| CN113241335B (en) * | 2021-04-07 | 2022-03-22 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and semiconductor device |
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Application publication date: 20170818 |
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