US20150340435A1 - Multi-chip Package Module And A Doped Polysilicon Trench For Isolation And Connection - Google Patents

Multi-chip Package Module And A Doped Polysilicon Trench For Isolation And Connection Download PDF

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US20150340435A1
US20150340435A1 US14/727,768 US201514727768A US2015340435A1 US 20150340435 A1 US20150340435 A1 US 20150340435A1 US 201514727768 A US201514727768 A US 201514727768A US 2015340435 A1 US2015340435 A1 US 2015340435A1
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Prior art keywords
die
layer
trench
top surface
doped
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US14/727,768
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Benedict C.K. Choy
Ching Chu
Haibing (Robin) Liu
Ming-Yuan Yeh
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Microchip Technology Inc
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Microchip Technology Inc
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Priority to US14/727,768 priority Critical patent/US20150340435A1/en
Publication of US20150340435A1 publication Critical patent/US20150340435A1/en
Assigned to JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT reassignment JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICROCHIP TECHNOLOGY INCORPORATED
Assigned to JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT reassignment JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ATMEL CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., SILICON STORAGE TECHNOLOGY, INC.
Assigned to WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT reassignment WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ATMEL CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., SILICON STORAGE TECHNOLOGY, INC.
Assigned to SILICON STORAGE TECHNOLOGY, INC., MICROSEMI CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI STORAGE SOLUTIONS, INC., ATMEL CORPORATION reassignment SILICON STORAGE TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Assigned to MICROCHIP TECHNOLOGY INCORPORATED reassignment MICROCHIP TECHNOLOGY INCORPORATED RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Assigned to ATMEL CORPORATION, MICROSEMI CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, SILICON STORAGE TECHNOLOGY, INC., MICROSEMI STORAGE SOLUTIONS, INC. reassignment ATMEL CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
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    • H01L2924/102—Material of the semiconductor or solid state bodies
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    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a multi-chip package module in which an intra-chip signal routing path is used to facilitate the connection of a wire bond from one chip across another chip to a lead.
  • the present invention also relates to a doped polysilicon trench for use either as a connection to a buried layer or substrate in a vertical circuit component or as an isolation structure.
  • Multi-chip packaged modules are well known in the art.
  • a multi-chip packaged module a plurality of integrated circuit dies are placed on a surface of a die attach pad, which is surrounded by leads.
  • Each die has a plurality of bonding pads.
  • Electrical leads such as wire bonds, connect certain bonding pads of the dies to certain leads, surrounding the die attach pad.
  • the bonding wire has to cross over the second die. This can lead to several problems. First, the wire bond must be lengthy.
  • the wire bond may interfere electrically with the operation of the circuit elements on the second die.
  • the wire bond may even short to other electrical terminals (including other wire bonds) over the second die. Further, in some cases, due to the presence of the adjacent die, it may not even be possible to cross the wire bond over the adjacent die.
  • a further problem with the prior art is if one of the dies contains a vertically oriented circuit element, such as a bipolar transistor or a vertical DMOS transistor. In that event, the bottom surface of that die is a terminal, and must be connected to a voltage other than ground. Thus, the dies cannot be connected on the same die attach pad (which is typically made of a metal), due to the potential differences between the bottom surfaces of the dies.
  • a vertically oriented circuit element such as a bipolar transistor or a vertical DMOS transistor.
  • One prior art solution is to use multiple die attach pads, with each die attach pad for a different die, and the multiple die attach pads are then packaged in a single package.
  • Another prior art solution is to create a re-distribution layer (RDL) with the bonding pads of the different dies connected to the RDL, and the RDL re-routing the signals to different circuit elements.
  • RDL re-distribution layer
  • Another prior art solution is to connect the dies on a printed circuit board (PCB) with the PCB packaged in a die attach pad.
  • PCB printed circuit board
  • one object of the present invention is to reduce the cost of multi-chip packaging, and in particular to reduce the cost for a multi-chip packaging of multiple dies, where one of the dies contains a vertical circuit element.
  • a circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface.
  • a nonconductive adhesive is on the surface.
  • a plurality of electronic circuit dies are attached to the nonconductive adhesive on the surface of the die attach pad.
  • Each die has a top surface and a bottom surface with the bottom surface on the adhesive.
  • the top surface has a plurality of bonding pads.
  • a first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad.
  • a first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die.
  • a second bonding wire connects the second bonding pad of the first electronic circuit die to a lead.
  • the present invention also relates to a semiconductor device which comprises a silicon layer of substantially single crystal, and has a bottom surface and a top surface.
  • a doped layer forms a terminal along the bottom surface of the layer.
  • a trench filled with doped polysilicon extends from the top surface to the terminal.
  • the present invention also relates to a semiconductor device that comprises a silicon layer of substantially single crystal, with a bottom surface and a top surface.
  • a plurality of vertical circuit components are in the layer between the top surface and the bottom surface.
  • a trench filled with doped polysilicon extends from the top surface to the bottom surface and isolates and separates the plurality of circuit components from one another.
  • FIG. 1 is a top view of a multi-chip package module of the present invention.
  • FIG. 2 is a side view of the module of the present invention shown in FIG. 1 .
  • FIG. 3 is a cross-sectional view of a semiconductor die with a doped polysilicon trench of the present invention to connect to a buried layer.
  • FIG. 4( a ) is a cross-sectional view of a first embodiment of a die with which the polysilicon trench of the present invention may be used.
  • FIG. 4( b ) is a cross-section view of the trench of the present invention connected to the substrate in the die shown in FIG. 4( a ).
  • FIG. 5( a ) is a cross-sectional view of a second embodiment of a die with which the polysilicon trench of the present invention may be used for isolation.
  • FIG. 5( b ) is a cross-section view of the trench of the present invention connected to the buried layer in the die shown in FIG. 5( a ) for isolation.
  • FIG. 6( a ) is a cross-sectional view of a third embodiment of a die with which the polysilicon trench of the present invention may be used.
  • FIG. 6( b ) is a cross-section view of the trench of the present invention connected to the buried layer in the die shown in FIG. 6( a ).
  • FIG. 1 there is shown a top view of the multi-chip packaged module 10 of the present invention.
  • the module 10 comprises a die attach pad 12 having a surface 12 surrounded by a plurality of leads 14 ( a - p ).
  • the leads 14 surround the surface 12 .
  • Two dies 18 a and 18 b are shown, although the present invention is not limited to two dies.
  • Each die 18 comprises at least one circuit element.
  • Each die 18 has a top surface 32 and a bottom surface 34 .
  • On the top surface 32 are a plurality of bonding pads, e.g. 16 a and 16 b for die 18 a .
  • the dies 18 a and 18 b are attached to the surface 12 of the die attach pad along the bottom surface 34 of the die 18 with a layer of non-conductive adhesive 24 between the bottom surface 34 and the surface 12 of the die attach pad.
  • wire bonds such as 20 c , 20 d and 20 e , connect various bonding pads of the die 18 to the leads 14 .
  • die 18 b further comprises a signal routing layer 30 , on the top surface 32 of die 18 b .
  • the routing layer 30 connects a bonding pad 22 a of the die 18 b to the bonding pad 22 b .
  • routing layer 30 does not connect to any of the electrical components in the die 18 b , and is used solely to route signals.
  • the bonding pad 22 a is located near a side surface which is on one side of the die 18 b
  • the bonding pad 22 b is near a side surface of the die 18 b which is opposite to that of the bonding pad 22 a .
  • the side surfaces to which the bonding pads 22 a and 22 b are near are parallel to one another, with the signal routing layer 30 routing signals from one side of the die 18 b to another side of the die 18 b .
  • An intra-chip wire bond 20 a connects bonding pad 16 b of die 18 a to bonding pad 22 a of die 18 b .
  • a bonding wire 20 b connects the bonding pad 22 b to lead 14 a . In this manner, signals from the die 18 a at the bonding pad 16 b can be electrically connected to the lead 14 a , without “crossing” over the die 18 b.
  • one of the dies can contain a vertical circuit element, such as a vertical DMOS transistor.
  • a vertical circuit element such as a vertical DMOS transistor.
  • FIG. 3 there is shown a cross-sectional view of a die 18 a with a vertical circuit element, such as a vertical DMOS transistor.
  • the bottom surface 34 of the die 18 a is a doped layer 33 .
  • the doped layer of the die 18 a is a N+ layer 33 .
  • the bottom surfaces 34 of the dies 18 a and 18 b are attached to the surface 12 of the die attach pad by a non-conductive adhesive 24 , the bottom surfaces 34 will not short one another.
  • this is achieved by the use of a vertical trench 50 cut in the die 18 a but filled with doped polysilicon.
  • the doped layer 33 is the drain of a vertical transistor, such as a bipolar transistor.
  • the connection to the drain 33 is done by connecting the die with its bottom surface 34 on a printed circuit board (PCB) substrate and then routing the signal on the PCB to the other die.
  • PCB printed circuit board
  • a trench 50 filled with doped polysilicon connects to the drain 33 , and then with the connection to the trench 50 can be made on the same front surface 32 of the die 18 a as the rest of the electrical connections.
  • the signal from the drain 33 can be routed to virtually any of the leads in the die attach pad.
  • the die 18 a comprises a single crystalline substrate 52 , such as single crystalline silicon (although other complex single crystalline compounds, such as GaAS, may also be used).
  • the substrate 52 is typically doped with P type or N type to render it conductive to act as the bottom most layer of a vertical device, such as a bipolar transistor, with the bottom surface 34 of the die 18 a being the bottom of the substrate 52 .
  • a layer 54 of silicon is epitaxially grown on the substrate 52 . Because the layer 54 is epitaxially grown, it will also be single crystalline, and will match the crystalline lattice structure of the substrate 52 .
  • the top surface of the epitaxial layer 54 forms the top surface 32 of the die 18 a .
  • a layer 60 of silicon (di)oxide or other insulator is grown or deposited on the top surface 32 .
  • a trench 50 is cut into the die 18 a , through the oxide layer 60 , through the epitaxial layer 54 and into the substrate 52 .
  • the trench 50 can be cut by well known techniques such as first forming a mask with a photoresist to cut into the oxide layer 60 . Thereafter using the exposed portion of the photoresist and the oxide 60 as a mask, the epitaxial layer 54 is cut anisotropically by reactive ion etch into the substrate 52 . Polysilicon is then deposited into the trench 50 .
  • the polysilicon in the trench 50 is then doped with a dopant to render it conductive.
  • the doping can be done by ion implant or by diffusion or may be doped in-situ with the deposition of the polysilicon in the trench 50 .
  • the level of doping of the polysilicon in the trench 50 can be controlled to match the doping level of the substrate 52 to which electrical contact is desired to be made.
  • LPCVD Low pressure Chemical Vapor Deposition
  • a second layer of LPCVD of polysicliocn can then be deposited into the trench 50 filling it.
  • This second deposition of LPCVD can be doped to a level slightly different than the first layer of LPCVD polysilicon.
  • the resultant structure is shown in FIG. 4( b ).
  • FIG. 5( a ) there is shown a cross-section view of another die 18 a with which the trench 50 of the present invention may be used for isolation purpose.
  • the die 18 a shown in FIG. 5( a ) is similar to the die shown in FIG. 4( a ).
  • the die 18 a shown in FIG. 5( a ) comprises a layer of single crystalline substrate 52 of a first conductivity type.
  • a buried layer 56 is formed by selectively implanting the substrate 52 to a second conductivity type.
  • An epitaxial layer 54 is then grown on the substrate 52 .
  • the epitaxial layer 54 is of the same conductivity as the substrate 52 .
  • the buried layer 56 is not a different layer, but is simply portions of the epitaxial layer 54 and the substrate 52 doped to form the connection to the vertical circuit element. In addition, the buried layer 56 does not extend along the entire epitaxial layer 54 /substrate 52 interface. Similar to the embodiment shown in FIGS. 4( a ) and 4 ( b ) described hereinabove, trenches 50 are then cut into the oxide layer 60 through the epitaxial layer 54 and into the buried layer 56 . The trenches 50 are then filled with polysilicon, doped to the same conductivity type as the buried layer 56 to make electrical contact with the buried layer 56 .
  • FIG. 6( a ) there is shown a cross-section view of another embodiment of a die 18 a for use with the trench 50 of the present invention.
  • the die 18 a shown in FIG. 6( a ) is similar to the die 18 a shown in FIG. 5( a ), and comprises a substrate 52 , with an epitaxial layer 54 , and a buried layer 56 therebetween.
  • the buried layer 56 extends across the entire interface region between the epitaxial layer 54 and the substrate 52 .
  • FIG. 6( b ) there is shown a cross section view of the die 18 a with the trench 50 made through the oxide layer 60 , the epitaxial layer 54 and into the buried layer 56 .
  • the trench 60 is then filled with doped polysilicon to make an electrical connection to the buried layer 56 .
  • a doped polysilicon trench 50 of the present invention may also be used as an isolation structure to electrically isolate a one circuit component, such as a vertical component from other electrical components in the integrated circuit die.

Abstract

A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This patent application is a divisional of U.S. application Ser. No. 12/834,853, issued as U.S. Pat. No. 9,048,104, filed on Jul. 12, 2010, and titled “A Multi-Chip Package Module and a Doped Polysilicon Trench for Isolation and Connection,” which is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • The present invention relates to a multi-chip package module in which an intra-chip signal routing path is used to facilitate the connection of a wire bond from one chip across another chip to a lead. The present invention also relates to a doped polysilicon trench for use either as a connection to a buried layer or substrate in a vertical circuit component or as an isolation structure.
    • BACKGROUND OF THE INVENTION
  • Multi-chip packaged modules are well known in the art. In a multi-chip packaged module, a plurality of integrated circuit dies are placed on a surface of a die attach pad, which is surrounded by leads. Each die has a plurality of bonding pads. Electrical leads, such as wire bonds, connect certain bonding pads of the dies to certain leads, surrounding the die attach pad. In the prior art, if two dies are to be packaged side by side, and if an electrical connection is desired to connect the bonding pad of a first die, which is located to one side of a second die, to a lead which is on the other side of the second die, the bonding wire has to cross over the second die. This can lead to several problems. First, the wire bond must be lengthy. Second, by crossing the wire bond over the second die, the wire bond may interfere electrically with the operation of the circuit elements on the second die. Finally, if not done carefully, the wire bond may even short to other electrical terminals (including other wire bonds) over the second die. Further, in some cases, due to the presence of the adjacent die, it may not even be possible to cross the wire bond over the adjacent die.
  • A further problem with the prior art is if one of the dies contains a vertically oriented circuit element, such as a bipolar transistor or a vertical DMOS transistor. In that event, the bottom surface of that die is a terminal, and must be connected to a voltage other than ground. Thus, the dies cannot be connected on the same die attach pad (which is typically made of a metal), due to the potential differences between the bottom surfaces of the dies.
  • One prior art solution is to use multiple die attach pads, with each die attach pad for a different die, and the multiple die attach pads are then packaged in a single package. Another prior art solution is to create a re-distribution layer (RDL) with the bonding pads of the different dies connected to the RDL, and the RDL re-routing the signals to different circuit elements. Finally, another prior art solution is to connect the dies on a printed circuit board (PCB) with the PCB packaged in a die attach pad. Clearly all of these prior art solutions are expensive.
  • In the prior art, it is also well known to use oxide filled trenches to isolate circuit elements. In addition, through substrate vias (TSV) filled with metal have also been used to route signals from the back side of a die to the front side. Finally, junction diffusion isolation has been used to isolate circuit elements on the same die from one another.
  • Therefore, one object of the present invention is to reduce the cost of multi-chip packaging, and in particular to reduce the cost for a multi-chip packaging of multiple dies, where one of the dies contains a vertical circuit element.
    • SUMMARY OF THE INVENTION
  • Accordingly, in the present invention, a circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are attached to the nonconductive adhesive on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead.
  • The present invention also relates to a semiconductor device which comprises a silicon layer of substantially single crystal, and has a bottom surface and a top surface. A doped layer forms a terminal along the bottom surface of the layer. A trench filled with doped polysilicon extends from the top surface to the terminal.
  • The present invention also relates to a semiconductor device that comprises a silicon layer of substantially single crystal, with a bottom surface and a top surface. A plurality of vertical circuit components are in the layer between the top surface and the bottom surface. A trench filled with doped polysilicon extends from the top surface to the bottom surface and isolates and separates the plurality of circuit components from one another.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top view of a multi-chip package module of the present invention.
  • FIG. 2 is a side view of the module of the present invention shown in FIG. 1.
  • FIG. 3 is a cross-sectional view of a semiconductor die with a doped polysilicon trench of the present invention to connect to a buried layer.
  • FIG. 4( a) is a cross-sectional view of a first embodiment of a die with which the polysilicon trench of the present invention may be used.
  • FIG. 4( b) is a cross-section view of the trench of the present invention connected to the substrate in the die shown in FIG. 4( a).
  • FIG. 5( a) is a cross-sectional view of a second embodiment of a die with which the polysilicon trench of the present invention may be used for isolation.
  • FIG. 5( b) is a cross-section view of the trench of the present invention connected to the buried layer in the die shown in FIG. 5( a) for isolation.
  • FIG. 6( a) is a cross-sectional view of a third embodiment of a die with which the polysilicon trench of the present invention may be used.
  • FIG. 6( b) is a cross-section view of the trench of the present invention connected to the buried layer in the die shown in FIG. 6( a).
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring to FIG. 1 there is shown a top view of the multi-chip packaged module 10 of the present invention. The module 10 comprises a die attach pad 12 having a surface 12 surrounded by a plurality of leads 14 (a-p). The leads 14 surround the surface 12. Two dies 18 a and 18 b are shown, although the present invention is not limited to two dies. Each die 18, as will be described hereinafter, comprises at least one circuit element. Each die 18 has a top surface 32 and a bottom surface 34. On the top surface 32 are a plurality of bonding pads, e.g. 16 a and 16 b for die 18 a. The dies 18 a and 18 b are attached to the surface 12 of the die attach pad along the bottom surface 34 of the die 18 with a layer of non-conductive adhesive 24 between the bottom surface 34 and the surface 12 of the die attach pad. As is well know in the art, wire bonds, such as 20 c, 20 d and 20 e, connect various bonding pads of the die 18 to the leads 14.
  • In the present invention, die 18 b further comprises a signal routing layer 30, on the top surface 32 of die 18 b. The routing layer 30 connects a bonding pad 22 a of the die 18 b to the bonding pad 22 b. Thus, routing layer 30 does not connect to any of the electrical components in the die 18 b, and is used solely to route signals. In the preferred embodiment, the bonding pad 22 a is located near a side surface which is on one side of the die 18 b, while the bonding pad 22 b is near a side surface of the die 18 b which is opposite to that of the bonding pad 22 a. Thus, the side surfaces to which the bonding pads 22 a and 22 b are near are parallel to one another, with the signal routing layer 30 routing signals from one side of the die 18 b to another side of the die 18 b. An intra-chip wire bond 20 a connects bonding pad 16 b of die 18 a to bonding pad 22 a of die 18 b. Finally a bonding wire 20 b connects the bonding pad 22 b to lead 14 a. In this manner, signals from the die 18 a at the bonding pad 16 b can be electrically connected to the lead 14 a, without “crossing” over the die 18 b.
  • In another aspect of the present invention, one of the dies, such as die 18 a can contain a vertical circuit element, such as a vertical DMOS transistor. Referring to FIG. 3 there is shown a cross-sectional view of a die 18 a with a vertical circuit element, such as a vertical DMOS transistor. As noted hereinabove, typically, in a vertical circuit component, the bottom surface 34 of the die 18 a is a doped layer 33. As shown in FIG. 3, the doped layer of the die 18 a is a N+ layer 33. In another aspect of the present invention, because the bottom surfaces 34 of the dies 18 a and 18 b are attached to the surface 12 of the die attach pad by a non-conductive adhesive 24, the bottom surfaces 34 will not short one another. However, there remains the problem of routing the signal connection to the doped layer 33 along the bottom surface 34. In the present invention, this is achieved by the use of a vertical trench 50 cut in the die 18 a but filled with doped polysilicon. Typically, the doped layer 33 is the drain of a vertical transistor, such as a bipolar transistor. In the prior art, to package a multi-chip module in which one of the dies has a vertical transistor, the connection to the drain 33 is done by connecting the die with its bottom surface 34 on a printed circuit board (PCB) substrate and then routing the signal on the PCB to the other die. With the present invention, a trench 50 filled with doped polysilicon connects to the drain 33, and then with the connection to the trench 50 can be made on the same front surface 32 of the die 18 a as the rest of the electrical connections. Further, using the intra-chip signal routing path 30 described hereinabove, the signal from the drain 33 can be routed to virtually any of the leads in the die attach pad.
  • Referring to FIG. 4( a) there is shown a cross-sectional view of a die 18 with which the trench 50 of the present invention may be used. The die 18 a comprises a single crystalline substrate 52, such as single crystalline silicon (although other complex single crystalline compounds, such as GaAS, may also be used). The substrate 52 is typically doped with P type or N type to render it conductive to act as the bottom most layer of a vertical device, such as a bipolar transistor, with the bottom surface 34 of the die 18 a being the bottom of the substrate 52. A layer 54 of silicon is epitaxially grown on the substrate 52. Because the layer 54 is epitaxially grown, it will also be single crystalline, and will match the crystalline lattice structure of the substrate 52. The top surface of the epitaxial layer 54 forms the top surface 32 of the die 18 a. A layer 60 of silicon (di)oxide or other insulator is grown or deposited on the top surface 32. A trench 50 is cut into the die 18 a, through the oxide layer 60, through the epitaxial layer 54 and into the substrate 52. The trench 50 can be cut by well known techniques such as first forming a mask with a photoresist to cut into the oxide layer 60. Thereafter using the exposed portion of the photoresist and the oxide 60 as a mask, the epitaxial layer 54 is cut anisotropically by reactive ion etch into the substrate 52. Polysilicon is then deposited into the trench 50. The polysilicon in the trench 50 is then doped with a dopant to render it conductive. The doping can be done by ion implant or by diffusion or may be doped in-situ with the deposition of the polysilicon in the trench 50. The level of doping of the polysilicon in the trench 50 can be controlled to match the doping level of the substrate 52 to which electrical contact is desired to be made. Alternatively, a thin layer of LPCVD (Low pressure Chemical Vapor Deposition) polysilicon is first deposited into the trench 50. It is then doped to either N+ or P+ to match the dopant type and concentration of the substrate layer 52. Thereafter a second layer of LPCVD of polysicliocn can then be deposited into the trench 50 filling it. This second deposition of LPCVD can be doped to a level slightly different than the first layer of LPCVD polysilicon. The resultant structure is shown in FIG. 4( b).
  • Referring to FIG. 5( a) there is shown a cross-section view of another die 18 a with which the trench 50 of the present invention may be used for isolation purpose. The die 18 a shown in FIG. 5( a) is similar to the die shown in FIG. 4( a). The die 18 a shown in FIG. 5( a) comprises a layer of single crystalline substrate 52 of a first conductivity type. A buried layer 56 is formed by selectively implanting the substrate 52 to a second conductivity type. An epitaxial layer 54 is then grown on the substrate 52. The epitaxial layer 54 is of the same conductivity as the substrate 52. Due to subsequent thermal processing, dopants of the second conductivity in the buried layer 56 will subsequently migrate into the epitaxial layer 54. Thus, the buried layer 56 is not a different layer, but is simply portions of the epitaxial layer 54 and the substrate 52 doped to form the connection to the vertical circuit element. In addition, the buried layer 56 does not extend along the entire epitaxial layer 54/substrate 52 interface. Similar to the embodiment shown in FIGS. 4( a) and 4(b) described hereinabove, trenches 50 are then cut into the oxide layer 60 through the epitaxial layer 54 and into the buried layer 56. The trenches 50 are then filled with polysilicon, doped to the same conductivity type as the buried layer 56 to make electrical contact with the buried layer 56.
  • Finally, referring to FIG. 6( a), there is shown a cross-section view of another embodiment of a die 18 a for use with the trench 50 of the present invention. The die 18 a shown in FIG. 6( a) is similar to the die 18 a shown in FIG. 5( a), and comprises a substrate 52, with an epitaxial layer 54, and a buried layer 56 therebetween. Unlike the embodiment shown in FIG. 5( a), however, in the embodiment shown in FIG. 6( a), the buried layer 56 extends across the entire interface region between the epitaxial layer 54 and the substrate 52. Referring to FIG. 6( b) there is shown a cross section view of the die 18 a with the trench 50 made through the oxide layer 60, the epitaxial layer 54 and into the buried layer 56. The trench 60 is then filled with doped polysilicon to make an electrical connection to the buried layer 56.
  • With the trench 50 of the present invention, because the trench 50 is filled with the same material (silicon) as the material through which the trench 50 is made (epitaxial layer 54, and the buried layer 56 or the substrate 52), there is no material incompatibility between the trench 50 and the layers 54/56/52. Further, a doped polysilicon trench 50 of the present invention may also be used as an isolation structure to electrically isolate a one circuit component, such as a vertical component from other electrical components in the integrated circuit die.

Claims (15)

What is claimed is:
1. A semiconductor device comprising:
a silicon layer of substantially single crystal, having a bottom surface and a top surface;
a doped layer forming a terminal near the bottom surface of said layer; and
a trench filled with doped polysilicon with said trench extending from said top surface to said terminal.
2. The device of claim 1 wherein said silicon layer comprises a vertical transistor with said terminal being a terminal to said vertical transistor.
3. The device of claim 2 wherein said trench is formed by an etch process.
4. The device of claim 3 wherein said polysilicon in said trench is doped by diffusion.
5. The device of claim 1 wherein said layer is formed of an epitaxial layer of silicon, with said layer formed on a single crystalline substrate.
6. The device of claim 5 wherein said terminal is a buried layer between said silicon layer and said substrate.
7. A semiconductor device comprising:
a silicon layer of substantially single crystal, having a bottom surface and a top surface;
a plurality of vertical circuit components in said layer between said top surface and said bottom surface; and
a trench filled with doped polysilicon with said trench extending from said top surface to said bottom surface isolating and separating said plurality of circuit components from one another.
8. The device of claim 7 wherein said trench is formed by an etch process.
9. The device of claim 8 wherein said polysilicon in said trench is doped by diffusion.
10. The device of claim 9 wherein said layer is formed of an epitaxial layer of silicon, with said layer formed on a single crystalline substrate.
11. The device of claim 10 further comprising a buried layer between said silicon layer and said substrate.
12. A semiconductor device comprising:
a silicon layer of substantially single crystal substrate, having a top surface;
an epitaxial layer of silicon on the substrate;
a buried layer between the epitaxial layer and the substrate;
a plurality of circuit components in said epitaxial layer; and
a trench filled with doped polysilicon with said trench extending from the top surface to the buried layer to isolate and separate said plurality of circuit components from one another.
13. The device of claim 12 wherein said trench is formed by an etch process.
14. The device of claim 13 wherein said polysilicon in said trench is doped by diffusion.
15. The device of claim 14 wherein said epitaxial layer is formed on a single crystalline substrate.
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