CN116090383B - Method, device, computer storage medium and terminal for realizing static time sequence analysis - Google Patents
Method, device, computer storage medium and terminal for realizing static time sequence analysis Download PDFInfo
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Abstract
Disclosed herein are a method, an apparatus, a computer storage medium and a terminal for implementing static timing analysis, including: dividing the time sequence model into more than two time sequence related models; determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis; starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads; the time sequence model is obtained by traversing the netlist file, the time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2. According to the embodiment of the invention, the time sequence model is divided into more than two time sequence related models, more than two threads are called according to the number of the time sequence related models and the system environment parameter information, so that the parallel processing of static time sequence analysis is realized, and the efficiency of the static time sequence analysis is improved.
Description
Technical Field
The present disclosure relates to, but is not limited to, field programmable gate array technology, and more particularly to a method, apparatus, computer storage medium, and terminal for implementing static timing analysis.
Background
The field programmable gate array (FPGA, field Programmable GATE ARRAY) software development tool mainly includes links such as synthesis, layout, wiring, timing analysis, and bit stream generation.
The FPGA timing analysis mainly refers to static timing analysis, and the static timing analysis of the FPGA has two basic uses: firstly, determining the circuit speed of a user design after layout and wiring; and secondly, comprehensively analyzing a time sequence model in the circuit netlist, calculating delay data of a time sequence path in the circuit, and judging whether the delay data meet requirements. The key of static time sequence analysis is to establish an effective time sequence model, calculate the time sequence path and the time sequence allowance information in the time sequence model rapidly and accurately, and then feed the calculated time sequence information back to the layout wiring process of the FPGA in time to assist the layout wiring to perform time sequence optimization, so that the circuit speed of user design is improved.
FIG. 1 is a flow chart of static timing analysis in the related art, as shown in FIG. 1, the static timing analysis is a serial process, including: step 101, traversing a netlist file, and establishing a time sequence model; 102, determining a time sequence path of a time sequence model; step 103, sequentially carrying out time sequence analysis on each time sequence path, and determining whether the time sequence analysis of all the time sequence paths is completed or not; returning to step 103 when the timing analysis of all timing paths is not completed; when the timing analysis of all timing paths is completed, step 104 is executed; step 104, ending the flow. In general, static timing analysis is an iterative process, which requires multiple iterations according to layout and wiring information, and each iteration needs to reestablish a timing model and perform timing analysis and margin calculation on a timing path. Static timing analysis requires timing analysis for each timing path until all timing path analysis is complete. In the related art, after determining the sequence of the time sequence paths according to a preset strategy, the time sequence paths are analyzed according to the determined sequence, only one time sequence path can be analyzed at a time, and the time sequence paths sequenced later can be started after the time sequence analysis of the previous time sequence path is completed. When the design logic resources of the user are more, the time sequence path is complex or the static time sequence analysis process needs to iterate according to the layout and wiring information, and the iteration calculation is frequent, the static time sequence analysis has the defects of low execution efficiency, low analysis speed and long consumed time, and the running speed of the FPGA software tool can be limited, so that the efficiency of the user design is reduced.
In summary, how to improve the execution efficiency of static timing analysis of FPGA is a problem to be solved.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a method, a device, a computer storage medium and a terminal for realizing static time sequence analysis, which can improve the execution efficiency of the static time sequence analysis.
The embodiment of the invention provides a method for realizing static time sequence analysis, which comprises the following steps:
dividing the time sequence model into more than two time sequence related models;
determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis;
Starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads;
The time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2.
In one illustrative example, the partitioning of the timing model into more than two timing related models includes:
selecting any instance, and determining all instances in the time sequence model which are related to the selected instance time sequence as a time sequence related model;
Removing all the examples contained in the determined time sequence correlation model, and judging whether the time sequence model has residual examples after removing all the examples contained in the determined time sequence correlation model;
When all the examples contained in the determined time sequence related model are removed and the time sequence model has residual examples, any one example is reselected from the residual examples of the time sequence model, and all the examples related to the reselected example time sequence in the time sequence model are determined to be a time sequence related model;
and after judging that all the examples contained in the determined time sequence correlation model are eliminated, when the time sequence model does not contain the rest examples, determining all the determined time sequence correlation models as the divided more than two time sequence correlation models.
In one illustrative example, the system environment parameter information includes:
The number of cores of the central processing unit for executing the static time sequence analysis.
In one illustrative example, the determining the number of threads for static timing analysis includes:
dividing the number of the time sequence related models by the system environment parameter information to obtain thread number related value information;
and determining the number of threads corresponding to the obtained thread number related value information according to the corresponding relation between the preset thread number related value range and the thread number.
In an exemplary embodiment, the parallel static timing analysis of the divided timing correlation model by the opened thread includes:
determining the sequence of reading the divided time sequence related models into the opened threads according to the time sequence models;
And according to the determined sequence of reading the divided time sequence related models into the opened threads, carrying out parallel static time sequence analysis.
On the other hand, the embodiment of the invention also provides a computer storage medium, wherein a computer program is stored in the computer storage medium, and the method for realizing the static time sequence analysis is realized when the computer program is executed by a processor.
In still another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory storing a computer program; wherein,
The processor is configured to execute the computer program in the memory;
the computer program, when executed by the processor, implements a method for implementing static timing analysis as described above.
In still another aspect, an embodiment of the present invention further provides an apparatus for implementing static timing analysis, including: the division model unit is set as: dividing the time sequence model into more than two time sequence related models;
Determining that the thread unit is set to: determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis;
the processing unit is configured to: starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads;
The time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2. In an exemplary embodiment, the division model unit is configured to:
selecting any instance, and determining all instances in the time sequence model which are related to the selected instance time sequence as a time sequence related model;
Removing all the examples contained in the determined time sequence correlation model, and judging whether the time sequence model has residual examples after removing all the examples contained in the determined time sequence correlation model;
When all the examples contained in the determined time sequence related model are removed and the time sequence model has residual examples, any one example is reselected from the residual examples of the time sequence model, and all the examples related to the reselected example time sequence in the time sequence model are determined to be a time sequence related model;
and after judging that all the examples contained in the determined time sequence correlation model are eliminated, when the time sequence model does not contain the rest examples, determining all the determined time sequence correlation models as the divided more than two time sequence correlation models.
In one illustrative example, the system environment parameter information includes:
The number of cores of the central processing unit for executing the static time sequence analysis.
The technical scheme of the application comprises the following steps: dividing the time sequence model into more than two time sequence related models; determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis; starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads; the time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2. According to the embodiment of the application, the time sequence model is divided into more than two time sequence related models, more than two threads are called according to the number of the time sequence related models and the system environment parameter information, so that the parallel processing of static time sequence analysis is realized, and the efficiency of the static time sequence analysis is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a flow chart of static timing analysis in the related art;
FIG. 2 is a flow chart of a method for implementing static timing analysis according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for implementing static timing analysis according to another embodiment of the present invention;
fig. 4 is a block diagram of a device for implementing static timing analysis according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be arbitrarily combined with each other.
The steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.
FIG. 2 is a flowchart of a method for implementing static timing analysis according to an embodiment of the present invention, as shown in FIG. 2, including:
Step 201, dividing a time sequence model into more than two time sequence related models;
Step 202, determining the number of threads for static time sequence analysis according to the number of divided time sequence related models and system environment parameter information for executing the static time sequence analysis;
Step 203, starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads;
The time sequence model is obtained by traversing the netlist file, the time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2. According to the embodiment of the invention, the time sequence model is divided into more than two time sequence related models, more than two threads are called according to the number of the time sequence related models and the system environment parameter information, so that the parallel processing of static time sequence analysis is realized, and the efficiency of the static time sequence analysis is improved.
In one illustrative example, the static timing analysis of an embodiment of the present invention includes: static timing analysis of Field Programmable Gate Arrays (FPGAs); the time sequence model in the embodiment of the invention can be determined by traversing the netlist file of the FPGA; specifically, the embodiment of the invention reads the time sequence device information in the netlist file, analyzes the netlist file based on the read time sequence device information, and establishes a time sequence model of the netlist file.
In one illustrative example, an embodiment of the present invention divides a timing model into two or more timing related models, comprising:
selecting any one instance, and determining all instances in the time sequence model, which are related to the selected instance time sequence, as a time sequence related model;
Removing all the examples contained in the determined time sequence correlation model, and judging whether the time sequence model has residual examples after removing all the examples contained in the determined time sequence correlation model;
After all the examples contained in the determined time sequence correlation model are removed, when the time sequence model has residual examples, any one example is reselected from the residual examples of the time sequence model, and all the examples related to the time sequence of the reselected example in the time sequence model are determined as a time sequence correlation model;
And after judging that all the examples contained in the determined time sequence correlation model are removed, determining the determined time sequence correlation model as more than two divided time sequence correlation models when the time sequence model does not contain the rest examples.
In one illustrative example, an embodiment of the present invention may determine each timing-related model based on a defined traversal of the timing-related model based on a netlist file.
In an exemplary embodiment, the system environment parameter information of the embodiment of the present invention includes:
the number of cores in the central processing unit that performs the static timing analysis.
In an exemplary embodiment, the system environment parameter information of the embodiment of the present invention includes: the number of cores of the central processing unit for executing the static time sequence analysis and the memory size for executing the static time sequence analysis; in an exemplary embodiment, the number of cores and the memory size of the central processing unit of the embodiment of the present invention are mainly used for measuring the operation capability of the static timing analysis, and the information for determining the number of threads used for the static timing analysis can be obtained through operation.
In one illustrative example, the memory size in embodiments of the present invention is in units of gigabytes (G).
In one illustrative example, an embodiment of the present invention determines the number of threads for static timing analysis, comprising:
dividing the number of the time sequence related models by the system environment parameter information to obtain thread number related value information;
And determining the number of threads corresponding to the obtained thread number related value information according to the corresponding relation between the preset thread number related value range and the thread number.
In an exemplary embodiment, the method of the present invention performs parallel static timing analysis on the divided timing correlation model through an opened thread, including:
determining the sequence of reading the divided time sequence related models into the opened threads according to the time sequence models;
And according to the determined sequence of reading the divided time sequence related models into the opened threads, performing parallel static time sequence analysis.
In an exemplary embodiment, the sequence of the time sequence analysis performed on the time sequence correlation model according to the embodiment of the present invention may be confirmed by referring to a correlation technique, for example, according to the sequence of the starting instance in the divided time sequence correlation module, determining the sequence= of the time sequence analysis performed on the time sequence correlation model.
In an exemplary embodiment, with reference to the related art, the embodiment of the present invention performs static timing analysis according to source location information, sink location information of a timing path, and location information of an instance and an instance port that pass through. In an exemplary embodiment, examples of the embodiment of the present invention include devices such as a look-up table (LUT) and a register (DFF) in a timing path, and a timing model is built according to the correlation principle and according to the connection relationship between the positions of the examples and the input/output ports according to all the examples tracked in the netlist file.
FIG. 3 is a flowchart of a method for implementing static timing analysis according to another embodiment of the present invention, as shown in FIG. 3, including:
Step 301, analyzing a netlist file by reading an instance in the netlist file, and establishing a time sequence model corresponding to the netlist file;
step 302, determining and storing a time sequence model;
step 303, dividing the time sequence model into more than two time sequence related models;
Step 304, determining the thread number for static time sequence analysis according to the number of the divided time sequence related models and the kernel number of the central processing unit for executing the static time sequence analysis;
In one illustrative example, determining the number of threads for static timing analysis includes:
Dividing the number of the divided time sequence correlation models by the kernel number of a central processing unit for executing static time sequence analysis to obtain thread number correlation value information;
And determining the number of threads corresponding to the obtained thread number related value information according to the corresponding relation between the preset thread number related value range and the thread number. In an exemplary embodiment, the correspondence between the thread number correlation value range and the thread number may be set by those skilled in the art according to the computing capability of the central processing unit performing the static timing analysis and the processing efficiency of the static timing analysis;
step 305, starting threads according to the determined thread number;
step 306, determining the sequence of reading the divided time sequence related models into the opened threads according to the time sequence models;
step 307, performing parallel static time sequence analysis according to the determined sequence of reading the divided time sequence related models into the opened threads.
The embodiment of the invention takes the data structure of the time sequence path as input, sequentially reads the time sequence related models into a thread pool, dynamically distributes all the time sequence related models into different threads through thread scheduling for parallel time sequence analysis until all the time sequence analysis is completed; wherein the data structure comprises: source location information, sink location information, and location information of passing instances and instance ports.
According to the embodiment of the invention, the time sequence model is divided into more than two time sequence related models according to the time sequence relation, the number of the time sequence related models, the running environment information and the like are used for analyzing, a thread pool is dynamically started, the time sequence paths are subjected to parallel time sequence analysis, the problems that the serial static time sequence analysis of the FPGA has more logic resources, the time sequence paths are complex or the static time sequence analysis needs to iterate according to the layout wiring result, and the analysis speed is slow when the iterative computation is frequent are solved, and the design efficiency of the FPGA is improved.
The embodiment of the invention also provides a computer storage medium, wherein a computer program is stored in the computer storage medium, and the method for realizing the static time sequence analysis is realized when the computer program is executed by a processor.
The embodiment of the invention also provides a terminal, which comprises: a memory and a processor, the memory storing a computer program; wherein,
The processor is configured to execute the computer program in the memory;
the computer program, when executed by a processor, implements a method for implementing static timing analysis as described above.
Fig. 4 is a block diagram of a device for implementing static timing analysis according to an embodiment of the present invention, as shown in fig. 4, including: dividing a model unit, determining a thread unit and a processing unit; wherein,
The division model unit is set as: dividing the time sequence model into more than two time sequence related models;
Determining that the thread unit is set to: determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis;
the processing unit is configured to: starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads;
The time sequence model is obtained by traversing the netlist file, the time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2.
According to the embodiment of the invention, the time sequence model is divided into more than two time sequence related models, more than two threads are called according to the number of the time sequence related models and the system environment parameter information, so that the parallel processing of static time sequence analysis is realized, and the efficiency of the static time sequence analysis is improved.
In an exemplary embodiment, the division model unit of the embodiment of the present invention is configured to:
selecting any one instance, and determining all instances in the time sequence model, which are related to the selected instance time sequence, as a time sequence related model;
Removing all the examples contained in the determined time sequence correlation model, and judging whether the time sequence model has residual examples after removing all the examples contained in the determined time sequence correlation model;
After all the examples contained in the determined time sequence correlation model are removed, when the time sequence model has residual examples, any one example is reselected from the residual examples of the time sequence model, and all the examples related to the time sequence of the reselected example in the time sequence model are determined as a time sequence correlation model;
And after judging that all the examples contained in the determined time sequence correlation model are removed, determining the determined time sequence correlation model as more than two divided time sequence correlation models when the time sequence model does not contain the rest examples.
In an exemplary embodiment, the system environment parameter information of the embodiment of the present invention includes:
the number of cores in the central processing unit that performs the static timing analysis.
In one illustrative example, an embodiment of the present invention determines that a thread unit is set to:
dividing the number of the time sequence related models by the system environment parameter information to obtain thread number related value information;
And determining the number of threads corresponding to the obtained thread number related value information according to the corresponding relation between the preset thread number related value range and the thread number.
In an exemplary embodiment, the processing unit of the present invention performs parallel static timing analysis on the divided timing correlation model through an opened thread, including:
determining the sequence of reading the divided time sequence related models into the opened threads according to the time sequence models;
And according to the determined sequence of reading the divided time sequence related models into the opened threads, performing parallel static time sequence analysis.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (8)
1. A method of implementing static timing analysis, comprising:
dividing the time sequence model into more than two time sequence related models;
determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis;
Starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads;
The time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static time sequence analysis is more than or equal to 2; the partitioning of the timing model into more than two timing related models includes: selecting any instance, and determining all instances in the time sequence model which are related to the selected instance time sequence as a time sequence related model; removing all the examples contained in the determined time sequence correlation model, and judging whether the time sequence model has residual examples after removing all the examples contained in the determined time sequence correlation model; when all the examples contained in the determined time sequence related model are removed and the time sequence model has residual examples, any one example is reselected from the residual examples of the time sequence model, and all the examples related to the reselected example time sequence in the time sequence model are determined to be a time sequence related model; and after judging that all the examples contained in the determined time sequence correlation model are eliminated, when the time sequence model does not contain the rest examples, determining all the determined time sequence correlation models as the divided more than two time sequence correlation models.
2. The method of claim 1, wherein the system environment parameter information comprises:
The number of cores of the central processing unit for executing the static time sequence analysis.
3. The method of any of claims 1-2, wherein the determining the number of threads for static timing analysis comprises:
dividing the number of the time sequence related models by the system environment parameter information to obtain thread number related value information;
and determining the number of threads corresponding to the obtained thread number related value information according to the corresponding relation between the preset thread number related value range and the thread number.
4. The method according to any of claims 1-2, wherein the parallel static timing analysis of the partitioned timing correlation model by an on-thread comprises:
determining the sequence of reading the divided time sequence related models into the opened threads according to the time sequence models;
And according to the determined sequence of reading the divided time sequence related models into the opened threads, carrying out parallel static time sequence analysis.
5. A computer storage medium having a computer program stored therein, which when executed by a processor, implements the method of implementing static timing analysis according to any of claims 1-4.
6. A terminal, comprising: a memory and a processor, the memory storing a computer program; wherein,
The processor is configured to execute the computer program in the memory;
The computer program, when executed by the processor, implements a method of implementing static timing analysis as claimed in any one of claims 1-4.
7. An apparatus for implementing static timing analysis, comprising: dividing a model unit, determining a thread unit and a processing unit; wherein,
The division model unit is set as: dividing the timing model into more than two timing related models, the dividing the timing model into more than two timing related models comprising: selecting any one instance, and determining all instances in the time sequence model, which are related to the selected instance time sequence, as a time sequence related model; removing all the examples contained in the determined time sequence correlation model, and judging whether the time sequence model has residual examples after removing all the examples contained in the determined time sequence correlation model; after all the examples contained in the determined time sequence correlation model are removed, when the time sequence model has residual examples, any one example is reselected from the residual examples of the time sequence model, and all the examples related to the time sequence of the reselected example in the time sequence model are determined as a time sequence correlation model; after judging that all the examples contained in the determined time sequence correlation model are removed, when the time sequence model does not contain the rest examples, determining all the determined time sequence correlation models as more than two divided time sequence correlation models;
Determining that the thread unit is set to: determining the number of threads for static time sequence analysis according to the number of the divided time sequence correlation models and the system environment parameter information for executing the static time sequence analysis;
the processing unit is configured to: starting threads according to the determined thread number, and carrying out parallel static time sequence analysis on the divided time sequence related models through the started threads;
The time sequence correlation is an example contained in the time sequence correlation model, and connection is established through an input port or an output port; the number of threads for static timing analysis is greater than or equal to 2.
8. The apparatus of claim 7, wherein the system environment parameter information comprises:
The number of cores of the central processing unit for executing the static time sequence analysis.
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| US9501609B1 (en) * | 2015-12-02 | 2016-11-22 | International Business Machines Corporation | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit |
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