DE112018000842T5 - MORE NUCLEAR-ON-THE MEMORY MICROCONTROLLER - Google Patents

Abstract

Devices, systems, methods, and computer program products are disclosed for a multi-core on-die memory controller 150. An integrated circuit device 123, 212, 700 includes an array of non-volatile memory cells 200 and a microcontroller unit 150. A microcontroller unit 150 includes a plurality of processing units 302, 402, 404. Different processing units 302, 402, 404 perform different categories of tasks in parallel for an array of non-volatile memory cells 200.

Description

TECHNICAL AREA

The present disclosure relates to non-volatile and / or volatile memory in various embodiments, and more particularly relates to an on-die memory microcontroller for non-volatile and / or volatile memory.

BACKGROUND

A storage device may include a state machine that controls certain operations of the storage device. However, once the state machine goes through the tapeout and is in production, minimal, if any, changes can be made to address bugs or design flaws, reducing development and test flexibility without significantly extending the design cycle.

KU RZDARSTELLU NG

Devices, systems, methods, and computer program products are disclosed for multi-core on-die memory control. In one embodiment, a device includes an array of non-volatile memory cells in an integrated circuit device. In a further embodiment, a device includes a microcontroller unit in an integrated circuit device. In certain embodiments, a device includes a plurality of processing units of a microcontroller unit. Different processing units, in some embodiments, perform different categories of tasks in parallel for an array of non-volatile memory cells.

In one embodiment, a system includes an integrated circuit device including multiple stages, each having one or more layers. A first stage of an integrated circuit device includes a non-volatile storage medium in certain embodiments. In a further embodiment, a second stage of an integrated circuit device is parallel to and offset from a first stage. In one embodiment, a second stage of an integrated circuit device includes a microcontroller with a plurality of processing units. Different processing units perform different types of tasks in parallel for a non-volatile storage medium in different embodiments.

Another device, in certain embodiments, includes means for storing data. In one embodiment, an apparatus includes task sorting means for means for storing data by task category. In some embodiments, an apparatus includes means for performing different categories of tasks in parallel for a means for storing data using different processing units for the means for storing data.

In one embodiment, a method includes receiving a request for a store operation. In certain embodiments, a method includes determining a variety of tasks to complete a storage operation. Different tasks of a plurality of tasks are linked to different sets of instructions in one embodiment. In some embodiments, a method includes performing different tasks of a plurality of tasks in parallel using different processing units of a microcontroller. Different processing units support different sets of instructions in one embodiment.

Another device in some embodiments includes a microcontroller for a memory array of an integrated circuit device. In one embodiment, a microcontroller is set up to select a plurality of tasks for a memory operation using a first processing unit. In a further embodiment, a microcontroller is set up to control the timing of a multiplicity of tasks for a memory operation using a second processing unit. In certain embodiments, a microcontroller is configured to set voltages for a variety of tasks for a memory operation using a third processing unit.

list of figures

• 1 ist ein schematisches Blockdiagramm, das eine Ausführungsform eines Systems für einen On-Die-Speichermikrocontroller veranschaulicht;
• 2 ist ein schematisches Blockdiagramm, das eine andere Ausführungsform eines Systems für einen On-Die-Speichermikrocontroller veranschaulicht;
• 3 ist ein schematisches Blockdiagramm, das eine Ausführungsform eines On-Die-Speichermikrocontrollers veranschaulicht;
• 4 ist ein schematisches Blockdiagramm, das eine weitere Ausführungsform eines On-Die-Speichermikrocontrollers veranschaulicht;
• 5 ist ein schematisches Blockdiagramm, das eine Ausführungsform eines Systems mit mehreren On-Die-Speichermikrocontroller-Kernen veranschaulicht;
• 6 ist ein schematisches Blockdiagramm, das eine andere Ausführungsform eines Systems mit mehreren On-Die-Speichermikrocontroller-Kernen veranschaulicht;
• 7 ist ein schematisches Blockdiagramm, das eine Ausführungsform einer integrierten Schaltungsvorrichtung mit einem On-Die-Speichermikrocontroller veranschaulicht;
• 8 ist ein schematisches Flussdiagramm, das eine Ausführungsform eines Verfahrens für einen On-Die-Speichermikrocontroller veranschaulicht; und
• 9 ist ein schematisches Flussdiagramm, das eine weitere Ausführungsform eines Verfahrens für einen On-Die-Speichermikrocontroller veranschaulicht.

A more specific description is included below with reference to specific embodiments illustrated in the accompanying drawings. Given that these drawings illustrate only certain embodiments of the disclosure and are therefore not to be considered limiting of the scope thereof, the disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

• 1 10 is a schematic block diagram illustrating an embodiment of a system for an on-die memory microcontroller;
• 2 Figure 3 is a schematic block diagram illustrating another embodiment of a system for an on-die memory microcontroller;
• 3 10 is a schematic block diagram illustrating an embodiment of an on-die memory microcontroller;
• 4 Fig. 4 is a schematic block diagram illustrating another embodiment of an on-die memory microcontroller;
• 5 FIG. 12 is a schematic block diagram illustrating an embodiment of a system with multiple on-die memory microcontroller cores;
• 6 FIG. 12 is a schematic block diagram illustrating another embodiment of a system with multiple on-die memory microcontroller cores;
• 7 10 is a schematic block diagram illustrating an embodiment of an integrated circuit device with an on-die memory microcontroller;
• 8th FIG. 12 is a schematic flow diagram illustrating one embodiment of a method for an on-die memory microcontroller; and
• 9 FIG. 12 is a schematic flow diagram illustrating another embodiment of a method for an on-die memory microcontroller.

DETAILED DESCRIPTION

Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program. Accordingly, aspects of the present disclosure may take the form of a full hardware embodiment, a full software embodiment (including firmware, resident software, microcode, or the like), or a software and hardware aspect combining embodiment, all of which are generally referred to herein as "circuitry", "Module", "device" or "system" can be called. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-volatile computer readable storage media that store computer readable and / or executable program code.

Many of the functional units described in this patent were referred to as modules in order to additionally emphasize their independence from implementation. For example, a module can be implemented as a hardware circuit that includes custom VLSI circuits or gate arrays, commercially available semiconductors such as logic chips, transistors, or other discrete components. A module can also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

Modules can also be implemented, at least in part, in software for execution by various types of processors. For example, an identified executable code module may include one or more physical or logical blocks of computer instructions that may be organized, for example, as an object, procedure, or function. Nevertheless, the executable programs of an identified module do not have to be physically arranged together, but can have different instructions stored in different locations which, when logically connected, have the module and serve the stated purpose for the module.

As a result, a module of executable codes can include a single instruction or many instructions, and can even be distributed over several different code segments, in different programs, over several storage devices or the like. Where a module or parts of a module are implemented in software, the software parts can be stored on one or more computer-readable and / or executable storage media. Any combination of one or more computer readable storage media can be used. For example, but not limited to, a computer readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and / or executable storage medium may be any concrete and / or non-volatile medium that can contain or store a program for use by or in connection with an instruction execution system, device, processor, or device.

Computer program code for performing operations for aspects of the present disclosure can be written in any combination of one or more programming languages, including an object-oriented programming language such as Python, Java, Smalltalk, C ++, C #, Objective C, or the like, conventional procedural programming languages such as the programming language "C", script Programming languages and / or other similar programming languages. The program code can be executed partially or completely on one or more computers of a user and / or on a remote computer or server via a data network or the like.

A component as used herein has a concrete, physical, non-volatile device. For example, a component can be implemented as a hardware logic circuit that includes custom VLSI circuits, gate arrays, or other integrated circuits; commercially available semiconductors such as logic chips, transistors or other discrete devices; and / or other mechanical or electrical devices. A component can also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like. A component may include one or more silicon-based integrated circuit devices (e.g., chips, dies, die levels, packets) or other discrete electrical devices in electrical communication with one or more other components via electrical circuit board (PCB) lines or the like. Each of the modules described herein may alternatively be embodied or implemented by a component in certain embodiments.

A circuit as used herein comprises a set of one or more electrical and / or electronic components that provide one or more paths for electrical power. In certain embodiments, a circuit may include an electrical return path so that the circuit is a closed loop. However, in another embodiment, a set of components that does not include an electrical return path may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit can be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for electrical current) or not. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and / or electrical components with or without integrated circuit devices, or the like. In one embodiment, a circuit may include individual VLSI circuits, gate arrays, logic circuits, or other integrated circuits; commercially available semiconductors such as logic chips, transistors or other discrete devices; and / or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device, such as a field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, netlist, or the like). A circuit may include one or more silicon-based integrated circuit devices (e.g., chips, dies, die levels, packets) or other discrete electrical devices that are electrically connected to one or more other components via electrical wiring of a circuit board (PCB) or the like are connected. Each of the modules described herein can be embodied or implemented by circuitry in certain embodiments.

Reference to "an embodiment", "embodiment", or similar usage in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the terms "in one embodiment," "in the embodiment," and similarly used language in this description, where they occur, may not necessarily all refer to the same embodiment, but may mean "one or more, but not all, embodiments" if so not expressly stated otherwise. The terms "including", "exhibiting", "possessing" and variations thereof mean "including but not limited to" unless expressly stated otherwise. An enumerating list of elements does not imply that any or all of the elements are mutually exclusive and / or mutually exclusive, unless expressly stated otherwise. The terms "a" and "the" refer to "one or more" unless expressly stated otherwise.

Aspects of the present disclosure are described below with reference to schematic flow diagrams and / or schematic block diagrams of methods, devices, systems and computer program products according to embodiments of the disclosure. It is understood that each block of the schematic flow diagrams and / or schematic block diagrams and combinations of blocks in the schematic flow diagrams and / or schematic block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a computer or other programmable computing device to generate a machine so that the Instructions executed by the processor or other programmable computing device generate means for implementing the functions and / or steps specified in the schematic flow diagrams and / or schematic block diagrams block or blocks.

It should also be noted that in some alternative implementations, the functions specified in the block may occur out of the order shown in the figures. For example, two blocks shown in sequence may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. Other steps and methods that are equivalent in function, logic or effect to one or more blocks or parts thereof of the figures shown can be conceived. Although various types of arrows and lines can be used in the flowchart and / or the block diagrams, they are to be understood that they do not limit the scope of the corresponding embodiments. For example, an arrow may indicate a maintenance or monitoring period of an unspecified duration between enumerated steps in the illustrated embodiment.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The previous summary is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, other aspects, embodiments and features will become apparent with reference to the drawings and the following detailed description. The description of elements in each figure can refer to elements of continuous figures. Like reference numerals may refer to like elements in the figures, including alternative embodiments of like elements.

1 Figure 3 is a block diagram of one embodiment of a system 100 for an on-die memory microcontroller 150 , The system 100 has one or more microcontrollers 150 for storage media 122 a non-volatile and / or volatile storage device 120 on. A microcontroller 150 may be part of a non-volatile and / or volatile memory element 123 and can be in communication with a controller 126 non-volatile and / or volatile storage media, a device driver or the like. In some embodiments, a microcontroller 150 at least partially on and / or in communication with a non-volatile and / or volatile storage system 102 a computing device 110 work that a processor 111 , volatile memory 112 and a communication interface 113 can have. The processor 111 can be one or more central processing units, one or more universal processors, one or more application-specific processors, one or more virtual processors (e.g. the computing device 110 a virtual machine operating in a host), one or more processor cores, or the like. The communication interface 113 may have one or more network interfaces that are configured to the computing device 110 and / or memory control 126 communicative with a communication network 115 , such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network, a wired network, or the like.

A microcontroller 150 As used herein, one or more circuitry or other logic hardware includes an integrated circuit device, such as a die and / or a chip 123 of storage media 122 (e.g. a storage element 123 or another integrated circuit device). For example, in one embodiment, a microcontroller 150 synthesizable logic (e.g., defined in a hardware description language such as Verilog, VHSIC hardware description language (VHDL) or the like; a gate level network list; a softcore; and / or other logical structure) based on a programmable logic device such as a field programmable gate - Array (FPGA), manufactured as an Application Specific Integrated Circuit (ASIC), is placed and / or routed thereon; and / or another integrated circuit device 123 exhibit. In a further embodiment, a microcontroller 150 Analog and / or mixed signal logic (e.g., defined and / or designed in a transistor array format, an ASIC, discrete logic components, a hardcore and / or other integrated circuit device 123 ).

A microcontroller 150 can do one or more tasks for a storage element 123 of storage media 122 , such as management functions or the like, perform and / or control. A microcontroller 150 may include one or more processing units, processing cores, or the like that process and / or execute microcode or other computer-executable code (e.g., a set of instructions) to perform tasks or operations. In this way, instead of or in addition to making a new integrated Circuit device or updating firmware one or more functions and / or tasks of a microcontroller 150 by changing and / or updating microcode or other computer-executable code of the microcontroller 150 be updated. A microcontroller 150 can have volatile or volatile and / or non-volatile or non-volatile memory or storage that the microcontroller 150 Can use microcode to store data for and / or from an array of storage media 122 save to save settings and / or configuration parameters or the like.

In certain embodiments, the storage device 120 and / or the storage elements 123 can be used in a number of applications and / or environments. In order to function properly at different temperatures and other environmental conditions, a clock rate of a microcontroller can 150 and / or a storage element 123 artificially set low to improve stability, reliability or the like in a wide range of operating conditions. For example, in various embodiments, a clock rate for a microcontroller 150 to less than about 50 MHz, less than about 40 MHz, less than about 30 MHz, less than about 20 MHz, less than about 15 MHz, about 14 MHz, about 13.5 MHz, about 13 MHz, about 12.5 MHz , about 12 MHz, less than about 12 MHz, or the like.

However, such a low clock rate can be a microcontroller 150 in certain embodiments are set lower than a clock rate at which the microcontroller 150 Data operations for the storage media 122 using a single processing unit without increasing latency of data operations (e.g., a single processing unit or processing core may not be fast enough in clock speed or frequency to extract data from the non-volatile storage medium 123 to read and / or write to it without slowing down the read and / or write operations, thereby causing the microcontroller 150 becomes a bottleneck, or the like). A microcontroller 150 may, in one embodiment, include, be associated with, and / or have access to, a plurality of processing units and / or cores that have different categories and / or parts of tasks for an array of storage media 122 run in parallel (e.g. to an effect of a slow microcontroller clock rate on the access latency for the storage media 122 to reduce and / or eliminate or the like).

A processing unit, as used herein, has a sub-block and / or a sub-component that is associated with one or more microcontrollers 150 linked and capable of executing and / or processing one or more commands and / or instructions (e.g. microcode, an instruction set or the like). A processing unit can be part of a microcontroller 150 can be from multiple microcontrollers 150 shared or the like. A processing unit can be a processing core, a soft core, a hardcore, synthesizable logic, analog and / or mixed signal logic, an execution unit, a module, a sub-component and / or another part of a microcontroller 150 with the ability to execute an instruction. In one embodiment, different processing units may have separate logical and / or physical interfaces (e.g. buses, control lines, addresses and / or address spaces or the like) to receive commands and / or instructions independently. In other embodiments, different processing units can share a logical and / or physical interface and can dynamically differentiate received commands and / or instructions by category, command type, instruction set, flag, identifier or the like.

Different processing units and / or cores of a microcontroller 150 can support different instruction sets (e.g., different microcode instructions and / or instructions) based on the categories and / or types of tasks assigned to the different processing units and / or cores. An instruction set for a processing unit, as used herein, may include one or more commands and / or instructions that are supported and / or compatible with the processing unit. In various embodiments, an instruction set may include and / or support one or more microcode instructions, assembly code instructions, machine instructions, memory instructions, device instructions, control and / or management instructions, or the like.

In one embodiment, one or more processing units can be one Execute a flow control category of tasks (for example, a flow control instruction set). One or more processing units may, in certain embodiments, execute a timing category of tasks (e.g., a timing instruction set). In another embodiment, one or more processing units can execute a data latch control category of tasks (e.g., a data latch control instruction set). In one embodiment, one or more processing units can perform a voltage control category of tasks (e.g., a voltage control instruction set). In certain embodiments, one or more processing units may execute a built-in self-test (BIST) task category (e.g., a self-test instruction set). In one embodiment, one or more processing units can perform one or more other types and / or categories of tasks, instruction sets, or the like. Two instruction sets may be different in certain embodiments in response to at least one instruction and / or command included in one instruction set not being included in another instruction set. A microcontroller 150 In one embodiment, comprises and / or supports an instruction set that has a combined sum and / or total of the different instruction sets that are supported by the processing units that operate with the microcontroller 150 linked and / or available for it.

In one embodiment, a microcontroller 150 on or towards an edge and / or circumference of a storage element 123 , adjacent to and / or next to an array of storage media 122 , be arranged (e.g. as in 2 ) Shown. In a further embodiment, a microcontroller 150 at another level, layer and / or level of an integrated circuit device 123 as an array of storage media 122 be arranged (e.g. as CMOS or another circuit under the array, in parallel with and offset from the array or the like). Forming and / or placing a microcontroller 150 at another stage of an integrated circuit device 123 as an array of storage media 122 may, in certain embodiments, space the integrated circuit device 123 save, resulting in more circuits (e.g. more or larger microcontrollers 150 and / or microcontroller cores 150 , Processing units, a larger array of storage media 122 or the like), a smaller integrated circuit device 123 or the like. In certain embodiments, e.g. B. silicon vias (TSV) between different stages of an integrated circuit device 123 electrical connections between one or more microcontrollers 150 and an array of storage media 122 provide.

In certain embodiments, an integrated circuit device 123 one or more additional microcontrollers 150 , Microcontroller cores 150 or the like. Different microcontrollers 150 and / or microcontroller cores 150 may be on the same level and / or layer to each other (e.g. a different level and / or layer than a storage array, parallel to and offset from a level of the storage array or the like), may be on several other levels and / or layers ( e.g., multiple levels and / or layers other than the storage array, parallel to and offset from a level of the storage array and from each other or the like) may be on one or more of the same levels and / or layers as a storage array or the like.

In one embodiment, to space an integrated circuit device 123 to save one or more additional microcontrollers 150 and / or microcontroller cores 150 have fewer processing units, may have processing units that are configured to perform fewer types and / or categories of tasks or the like than a first microcontroller 150 and / or microcontroller core 150 (e.g. a primary, main, control, full and / or complete microcontroller core 150 with one or more secondary, partial, smaller and / or reduced microcontroller cores 150 which have fewer processing units, or the like).

For example, a first microcontroller 150 and / or microcontroller core 150 have a built-in self-test processing unit and / or be in communication therewith, which is set up to perform self-test operations on an array of storage media 122 execute while one or more additional microcontrollers 150 and / or microcontroller core 150 may not have a built-in self-test processing unit. In a further embodiment there is a first microcontroller 150 and / or microcontroller core 150 set up to perform both programming / writing and reading operations on a memory array while one or more additional microcontrollers 150 and / or microcontroller core 150 can be set up to carry out read operations, but no programming / writing operations on the memory array (and, for example, can have a smaller space requirement and / or a smaller size than the first microcontroller 150 ).

In certain embodiments, a first set of one or more microcontrollers 150 (e.g. primary, main, control, full, and / or full microcontroller cores 150 or the like) programming / writing operations for an entire array of storage media 122 (e.g., each channel, subset and / or area of memory cells of an integrated circuit device 123 ) run while both the first set of one or more microcontrollers 150 as well as a second set of one or more microcontrollers 150 (e.g. one or more secondary, partial, smaller and / or reduced microcontroller cores 150 , which have fewer processing units, or the like) Read operations for different parts of the array of storage media 122 can perform (e.g., assigning to different channels, subsets and / or areas of memory cells of an integrated circuit device 123 ).

The storage device 120 may, in various embodiments, be in one or more different locations relative to the computing device 110 be arranged. In one embodiment, the storage device 120 one or more non-volatile and / or volatile memory elements 123 , such as semiconductor chips or packages or other integrated circuit devices, which are arranged on one or more circuit boards, memory packages and / or other mechanical and / or electrical carrier structures. For example, the storage device 120 One or more cards for a direct inline memory module (DIMM), one or more expansion cards and / or daughter cards, a memory card, a universal serial bus (USB) drive, a solid-state drive (SSD) or another hard disk device and / or can have a different storage and / or storage form factor. The storage device 120 can be in a motherboard of the computing device 110 integrated and / or mounted thereon, in a port and / or slot of the computing device 110 be installed on another computing device 110 and / or a dedicated storage device on the network 115 be installed with the computing device 110 be in communication via an external bus (e.g. an external hard drive) or the like.

The storage device 120 may, in one embodiment, on a processor memory bus 111 (e.g. on the same memory bus as the volatile memory 112 , on a different memory bus than the volatile memory 112 , instead of volatile memory 112 or the like) may be arranged. In another embodiment, the storage device 120 on a peripheral bus of the computing device 110 , such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) ) Bus, a small computer system interface (SCSI) bus, a FireWire bus, a fiber channel connection, a universal serial bus (USB), a PCIe Advanced Switching (PCIe-AS- ) Bus or the like. In another embodiment, the storage device 120 on a data network 115 , such as an Ethernet network, an Infiniband network, SCSI-RDMA over a network 115 , a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network 115 or the like.

The computing device 110 can still be a non-volatile, computer-readable storage medium 114 exhibit. The computer readable storage medium 114 may include executable instructions configured to cause the computing device 110 (e.g. processor 111 ) Performing steps of one or more of the methods disclosed herein. Alternatively or additionally, the microcontroller 150 include one or more computer readable instructions that are on the non-volatile storage medium 114 are saved.

In one embodiment, a microcontroller 150 logical hardware of a non-volatile and / or volatile memory element 123 , other programmable logic, firmware for a non-volatile and / or volatile memory element 123 , Microcode for execution by a non-volatile and / or volatile memory element 123 or the like. In another embodiment, a microcontroller 150 have at least partially executable software code (eg microcode) on a computer-readable storage medium for execution by logical hardware of a non-volatile and / or volatile memory element 123 (e.g. for execution by the microcontroller 150 itself, through the processor 111 or the like) is stored. In a further embodiment, a microcontroller 150 include a combination of both executable software code and logical hardware.

In one embodiment, the microcontroller 150 set up to receive requests and / or commands from a device driver or other executable application via buses 125 . 127 , a storage media controller 126 or the like. The microcontroller 150 can also be configured to transfer data to / from a device driver and / or storage clients 116 over the bus 125 transferred to. Accordingly, the microcontroller 150 in some embodiments, include, and / or be in communication with, and / or in communication with direct memory access (DMA) modules, modules with remote DMA, bus controllers, bridges, buffers, and so on, for the transfer of memory requests and to facilitate associated data. In another embodiment, the microcontroller 150 Storage requests and / or refresh commands as an API call from a storage client 116 , received as an IO-CTL command or the like.

In one embodiment is a microcontroller 150 on a storage element 123 integrates (e.g., on-die control and / or other logic hardware or executable code) and receives commands from a device controller 126 , a host device 110 and / or a processor 111 , In other embodiments, part of a microcontroller 150 on a device control 126 or another interposer and be part of a microcontroller 150 can on a storage element 123 be arranged or the like.

According to various embodiments, memory control 126 and / or a microcontroller 150 one or more storage devices 120 and / or storage elements 123 manage. The storage device (s) 120 may include recording, storage, and / or storage devices, such as solid state storage device (s) and / or semiconductor storage device (s), arranged and / or partitioned in a variety of addressable media storage locations. As used herein, a media location refers to any physical storage device (e.g., any amount of physical storage media on a storage device 120 ). Storage devices and / or areas may include, but are not limited to, pages, storage sections, blocks, sectors, collections, or sets of physical storage locations (e.g., logical pages, logical blocks), or the like.

A device driver, the storage media controller 126 and / or a microcontroller 150 can, in certain embodiments, the storage clients 116 a logical address space 134 present. As used herein, a logical address space refers 134 for a logical representation of storage resources. The logical address space 134 may have a plurality (e.g., a range) of logical addresses. As used herein, a logical address refers to any identifier for referencing a memory resource (e.g., data), including but not limited to: a logical block address (LBA), a cylinder / head / sector (Cylinder / Head) / Sector, CHS) address, a file name, an object identifier, a globally unique identifier (GUID), a hash code, a signature, an index entry, an area, a scope or the like.

A device driver for the storage device 120 can metadata 135 , such as a logical-to-physical address mapping structure, to manage logical addresses of the logical address space 134 media locations on the storage device or devices 120 map. A device driver can be set up to provide storage services for one or more storage clients 116 provide. The storage clients 116 can local storage clients 116 that on the computing device 110 work, and / or remote storage clients 116 that on the network 115 and / or the network interface 113 can be accessed. The storage clients 116 may include, but are not limited to: operating systems, file systems, database applications, server applications, kernel level processes, user level processes, applications, and the like.

A device driver can communicate with one or more storage devices 120 be coupled. The one or more storage devices 120 may include various types of storage devices, including but not limited to: solid state storage devices, semiconductor storage devices, SAN storage resources, volatile storage devices, non-volatile storage devices, or the like. The one or more storage devices 120 can have one or more respective storage media controls 126 and storage media 122 exhibit. A device driver can access the one or more storage devices 120 via a conventional block I / O interface 131 provide. In addition, a device driver can access improved functionality via the SCM interface 132 provide. The metadata 135 can be used to manage and / or track data operations through one of the block I / O interfaces 131 , SCM interfaces 132 , Cache interfaces 133 or other related interfaces.

The cache interface 133 may expose cache-specific features to those via a device driver for the storage device 120 can be accessed. In addition, in some embodiments, the SCM interface provides 132 that the storage clients 116 is presented, access to data transformations provided by the one or more storage devices 120 and / or the one or more storage media controls 126 be implemented.

A device driver can be used by the storage clients 116 a logical address space 134 present via one or more interfaces. As discussed above, the logical address space 134 have a plurality of logical addresses, each having respective media locations on the one or more storage devices 120 equivalent. A device driver can have metadata 135 manage the random-to-arbitrary mappings between logical addresses and media locations or the like.

A device driver may also have a storage device interface 139 used to transfer data, commands and / or requests to the one or more storage devices 120 over a bus 125 is set up, and / or in communication with it, which may include, but is not limited to: a memory bus of a processor 111 , a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a Small Computer System Interface (SCSI), FireWire, Fiber Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network 115 , Infiniband, SCSI-RDMA or the like. The storage device interface 139 can with the one or more storage devices 120 communicate by means of a command or commands for input / output control (IO-CTL), an IO-CTL command extension or IO-CTL command extensions, remote direct memory access or the like.

The communication interface 113 may have one or more network interfaces that are configured to the computing device 110 and / or memory control 126 communicative with a network 115 and / or with one or more remote, network-accessible storage clients 116 to couple. The storage clients 116 can local storage clients 116 that on the computing device 110 work, and / or remote storage clients 116 include on the over the network 115 and / or the network interface 113 can be accessed. The memory controller 126 is part of and / or in communication with one or more storage devices 120 , Even though 1 a single storage device 120 the disclosure is not limited in this regard, and could be adapted to any number of storage devices 120 , a combination of one or more volatile storage devices 120 and one or more non-volatile memory devices 120 or the like.

The storage device 120 can be one or more elements 123 of storage media 122 exhibit. In one embodiment, an element 123 of storage media 122 a volatile storage medium 122 on, such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, static RAM (SRAM), thyristor RAM (T-RAM), zero Capacitor RAM (Zero-Capacitor RAM, Z-RAM) or the like. In certain embodiments, an element has 123 of storage media 122 a non-volatile storage medium 122 such as ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, Ovonic Unified Memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g. 2D-NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), wire-based nanocrystal memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, silicon oxide nitride oxide silicon (SONOS) Memory, programmable metallization cell (PMC) memory, RAM with conductive bridging (Conductive Bridging RAM, CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g. hard disk, tape), optical Storage media or the like. The one or more elements 123 of storage media 122 have storage class memory (SCM) in certain embodiments.

While legacy technologies, such as NAND flash, can be block and / or page addressable, storage class memory is byte addressable in one embodiment. In other embodiments, storage class storage may be faster and / or have a longer lifespan (e.g., idle time) than NAND flash; may be less costly, use less power, and / or have higher memory density than DRAM; or offer one or more other advantages or improvements over other technologies. For example, the storage class storage may include one or more non-volatile storage elements 123 from ReRAM, memristor memory, programmable metallization cell memory, phase change memory, nano-RAM, wire-based nanocrystal memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM and / or variations thereof.

While the non-volatile storage medium 122 referred to herein as a "storage medium" may be the non-volatile storage medium 122 more generally, in various embodiments, include one or more non-volatile recording media capable of recording data that may be referred to as non-volatile storage media, non-volatile storage media, or the like. Furthermore, the non-volatile memory device 120 in various embodiments include a non-volatile recording device, a non-volatile storage device, a non-volatile storage device, or the like. Similarly, one can non-volatile memory element 123 in various embodiments include a non-volatile recording element, a non-volatile storage element, a non-volatile storage element or the like.

The non-volatile storage medium 122 can have one or more non-volatile memory elements 123 which may include, but are not limited to, chips, packets, levels, dies, or the like. One control 126 a non-volatile storage medium can be set up to perform data operations on the non-volatile storage medium 122 to manage, and may include one or more processors, programmable processors (e.g. FPGAs), ASICs, microcontrollers or the like. In some embodiments, control is 126 of the non-volatile storage medium to store data and / or data from the non-volatile storage medium 122 to read data to / from the non-volatile storage device 120 to transfer and so on.

The control 126 Non-volatile storage media can communicate with the non-volatile storage media 122 (e.g. with the microcontroller 150 ) via a bus 127 be coupled. The bus 127 can be an I / O bus for communicating data to / from the non-volatile memory elements 123 and / or the associated microcontrollers 150 exhibit. The bus 127 may further include a control bus for communicating addressing and other command and control information to the non-volatile memory elements 123 and / or the microcontrollers 150 exhibit. In some embodiments, the bus 127 the non-volatile memory elements 123 (e.g. the microcontrollers 150 ) communicative with the control system in parallel 126 Pair non-volatile storage media. This parallel access can allow the non-volatile storage elements 123 managed as a group, creating a logical storage element 129 is formed. The logical storage element can be subdivided into corresponding logical storage units (e.g. logical pages) and / or logical storage areas (e.g. logical blocks). The logical storage units can be formed by logically combining physical storage units from each of the non-volatile storage elements.

The control 126 of non-volatile memory and / or a microcontroller 150 can have a device driver running on the computing device 110 executed, and / or be in communication with it. A device driver can have one or more interfaces 131 . 132 and or 133 Storage services for the storage clients 116 provide. In some embodiments, a device driver provides a block device I / O interface 131 ready by the storage clients 116 Perform I / O operations at the block level. Alternatively or additionally, a device driver may have a storage class storage (SCM) interface 132 provide the other storage services to the storage clients 116 can provide. In some embodiments, the SCM interface 132 Extensions to the block device interface 131 (e.g., the storage clients 116 to the SCM interface 132 about extensions or additions to the block device interface 131 access). Alternatively or additionally, the SCM interface 132 be provided as a separate API, service and / or library. A device driver can also be set up to have a cache interface 133 for caching data using the non-volatile storage system 102 provides. A device driver can also interface 139 for non-volatile memory devices, which is set up to send data, commands and / or queries to the controller 126 non-volatile storage media and / or a microcontroller 150 over a bus 125 to be transmitted as described above.

2 illustrates an embodiment of a non-volatile storage device 210 that have one or more memory dies or chips 212 with one or more microcontrollers 150 can include. The non-volatile storage device 210 can the referring to 1 described non-volatile memory device 120 to be essentially similar. Although the one or more microcontrollers 150 of 2 to an extent of memory dies and / or chips 212 (e.g. at the same physical level as the storage array 200 in an integrated circuit device 123 ) are shown, in other embodiments, one or more microcontrollers 150 at a different physical level of memory dies and / or chips 212 than the storage array 200 (eg parallel to and offset from a level of the storage array 200 in an integrated circuit device 123 ) be arranged as in 7 shown.

The memory die 212 closes an array in some embodiments 200 (eg two-dimensional or three-dimensional) of memory cells, an on-die control 220 and read / write circuits 230A / 230B on. In one embodiment, access to the storage array is 200 implemented by the various peripheral circuits in a symmetrical manner on opposite sides of the array so that the densities of access lines and switching logic on each side are reduced by half. The read / write circuits 230A / 230B close a further reading blocks in a further embodiment 250 one that enable that one side of memory cells is read or programmed in parallel. In certain embodiments, the reading blocks 250 in communication with the one or more microcontrollers 150 ,

The storage array 200 is in different embodiments by word lines via row decoders 240A / 240B and through bit lines via column decoders 242A / 242B addressable. In some embodiments, there is a controller 244 in the same storage device 210 (e.g., a removable memory card or package) like the one or more memory dies 212 locked in. Commands and data are between the host and the controller 244 over lines 232 and between the controller and the one or more memory dies 212 over lines 234 transfer. An implementation can have multiple chips 212 lock in.

The on-die control 220 works with the read / write circuits in one embodiment 230A / 230B together to perform storage operations on the storage array 200 perform. The on-die control 220 includes a microcontroller in certain embodiments 150 , an on-chip address decoder 224 and a power control circuit 226 on. In one embodiment, the on-chip address decoder 224 and / or the power control circuit 226 Part of the microcontroller 150 be and / or controlled by it.

The microcontroller 150 provides control of memory operations at the chip level in one embodiment. The on-chip address decoder 224 provides an address interface to convert the address used by the host or memory controller to the hardware address used by the decoders 240A . 240B . 242A . 242B is used. The power control circuit 226 controls the power and voltages applied to the word lines and bit lines during memory operations. According to one embodiment, the control circuit closes 226 one or more charge pumps that can generate voltages that are greater than the supply voltage.

In one embodiment, any or any combination of the on-die control 220 , the microcontroller 150 , the power control circuit 226 , the decoding circuit 224 , the decoding circuit 242A , the decoding circuit 242B , the decoding circuit 240A , the decoding circuit 240B , the read / write circuits 230A , the read / write circuits 230B and / or the controller 244 are referred to as one or more management circuits.

3 represents an embodiment of a system 300 with an on-die memory microcontroller unit 150 The microcontroller 150 of 3 can essentially the microcontroller in certain embodiments 150 of 1 and / or the microcontroller 150 of 2 be similar to.

In the embodiment shown, the microcontroller has 150 a variety of processing units 302a-n on and / or is in communication with it. Some processing units 302a . 302b . 302n are inside the microcontroller 150 and / or are part of it, while other processing units 302c . 302d yourself outside of the microcontroller 150 located (e.g. external processing units, functional units or the like) and in communication with the microcontroller 150 are (and e.g. in communication with one or more additional microcontrollers 150 and / or microcontroller cores 150 could be). In certain embodiments, the outside of the microcontroller 150 processing units located 302c . 302d at the same level (e.g. one or more layers, levels or the like) as the microcontroller 150 within an integrated circuit device 123 (e.g. under a storage array 200 or the like) may be arranged.

The processing units 302a-n In various embodiments, one or more of a read processing unit 302 , a programming / writing processing unit 302 , a built-in self-test processing unit 302 , a flow control processing unit 302 , a timing processing unit 302 , a voltage control processing unit 302 and / or a data latch control processing unit 302 or the like. The processing units 302a-n can perform various categories of tasks such as flow control tasks, timing control tasks, data latch control tasks, voltage control tasks and / or built-in self-test tasks or the like.

In certain embodiments, the use of a microcontroller 150 (e.g., instead of and / or in addition to a finite state machine or the like) dynamic updates and / or changes to timing, voltages, logic operations, instructions, commands, microcode or the like for the microcontroller 150 even after completion and / or manufacture of the hardware of the microcontroller 150 and / or the associated integrated circuit device 123 , on-site or the like without changing the hardware. The multiple processing units 302a-n In one embodiment, working in parallel (e.g. multithreaded) can enable the microcontroller 150 operates at a lower clock speed than would otherwise be possible without also latency of memory operations (e.g. reading, programming / writing, erasing) on the memory array 200 to increase.

Every processing unit 302 in certain embodiments has a read port that the processing unit 302 may be used to refer to instructions / commands and / or data from a volatile memory module (e.g. the one below with respect to 4 volatile memory modules described 406 or the like). Communication between the processing units 302a-n can use a standard interface (e.g. the same protocol for different types of processing units 302a-n) take place, which transmits both commands and data. In one embodiment, the same interface can be used for the processing units 302a . 302b . 302n inside a microcontroller 150 and for the processing units 302c . 302d outside the microcontroller 150 be used.

4 represents an embodiment of a system 400 with an on-die memory microcontroller 150 The microcontroller 150 may be essentially one or more of the microcontroller in certain embodiments 150 of 1 , the microcontroller 150 of 2 and / or the microcontroller 150 of 3 described above may be similar. In the embodiment shown, the microcontroller has 150 a flow control processing unit 402a , a timing processing unit 402b , a data latch control processing unit 402c and a voltage control processing unit 402d on, each in communication with volatile memory 406 and with one or more external processing units 404a n that are outside the microcontroller 150 are.

A flow control processing unit 402a may, in certain embodiments, perform one or more memory operations (e.g., read operations, write / program operations, erase operations, management operations such as garbage collection operations, or the like) for a memory array 200 control and / or track. For example, a flow control processing unit 402a a set of states for different storage operations, managing one or more other processing units 402 (e.g. a time control unit 402b , a data latch control unit 402c , a voltage control unit 402d , one or more external processing units 404a-n or the like) for performing the various storage operations, sending commands / instructions thereto, determining a state of the other processing units 402 . 404 routing during various storage operations or the like. A flow control processing unit 402a In one embodiment, a data path can be used for storage operations (e.g., between device controllers 126 and a storage array 200 , between a microcontroller 150 and a storage array 200 or the like) manage. A flow control processing unit 402a may, in some embodiments, one or more internal data buses of a microcontroller 150 , an integrated circuit device 123 that the microcontroller 150 has, or manage the like.

A flow control processing unit 402a may, in one embodiment, include or otherwise include a read processing unit configured to execute and / or manage a subroutine of microcode, assembly code, and / or other computer-executable code (e.g., in parallel with one or more other processing units 402a-n . 404a-n) to get data from a storage array 200 to read and the read data of a device controller 126 , a host device 110 , a storage client 116 or the like (e.g., in response to a read request from the device controller 126 , the host device 110 , the storage client 116 or similar).

A flow control processing unit 402a In one embodiment, may include or otherwise include a write / program processing unit configured to run a subroutine of microcode, assembly code, and / or other computer-executable code (e.g., in parallel with one or more other processing units 402a-n . 404a-n) execute and / or manage data in response to a write request from a device controller 126 , a host device 110 , a storage client 116 or the like in a storage array 200 to write / program. As below regarding 6 described, in certain embodiments, a first microcontroller 150a a flow control processing unit 402a having a write / programming processing unit and a reading processing unit, while one or more other microcontrollers 150b-n have a read processing unit without a write / programming processing unit (e.g. in order to save energy, circuit size / space or the like).

In one embodiment, a flow control processing unit 402a a built-in self-test processing unit. As below regarding 6 described, point in certain embodiments, one or more first microcontrollers 150a a built-in self-test processing unit for an integrated circuit device 123 and / or a storage array 200 on while one or more other microcontrollers 150b-n have no built-in self-test processing unit (e.g. to save energy, circuit size / space or the like).

In one embodiment, in a system with multiple microcontrollers 150 one or more reduced-size microcontrollers 150 without built-in self-test processing units during a die sorting or other test, validation and / or verification process, that of a built-in self-test processing unit of a primary or full-size microcontroller 150 the same integrated circuit device 123 running, run empty. If one or more microcontrollers reduced in size 150 at least part of the volatile memory can not be used 406 with the empty microcontrollers 150 is also unused and available. In certain embodiments, a flow control processing unit 402a the available excess capacity of volatile memory 406 from one or more idle microcontrollers 150 during a test performed by a built-in self-test processing unit of the flow control processing unit 402a is used to take out of the storage array 200 save and process data read out for the test.

The flow control processing unit 402a can get test data from the storage array 200 in volatile memory 406 stream where the built-in self-test unit can process the data for errors or the like. A built-in self-test processing unit of a flow control processing unit 402a may perform one or more data transfers, data processing, timer functions, or the like to perform one or more functions of an integrated circuit device 123 and / or a storage array 120 to test (e.g. to identify one or more faulty bit lines, faulty word lines, faulty erase blocks; one or more test and / or fault reports for a test device, a host device 110 , a storage client 116 or the like to generate).

In one embodiment, a flow control processing unit 402a have one or more interrupt ports (e.g., soft or logic interrupt ports, physical or electrical hard interrupt ports, or the like) through which the flow control processing unit 402a may receive one or more signals (e.g., operating mode selection signals, feedback signals, programming and / or erase pulse counts, acknowledgment or failure signals for programming and / or erase verification, and / or other interrupts or other signals to the flow control processing unit 402a enable one or more memory operations for the microcontroller 150 manage).

In certain embodiments, a flow control processing unit 402a a status (e.g. ready, busy or the like) of the microcontroller 150 a device controller 126 , a host device 110 , a storage client 116 or the like and can provide one or more commands and / or operations for the microcontroller 150 and / or the storage array 200 receive. The flow control processing unit 402a may use the one or more interrupt ports to respond quickly (e.g., substantially immediately) to a command, rather than periodically polling a command and introducing latency and delay. A flow control processing unit 402a can be a subroutine for execution by one or more processing units 402a-d . 404a-n of a microcontroller 150 select based on signals on the one or more interrupt ports, a received command for an operation, or the like.

For example, in one embodiment, a flow control processing unit 402a (e.g. from a device controller 126 , a host device 110 , a storage client 116 or the like) a command interrupt signal (e.g., a single bit or the like), a command index (e.g., several bits indicating which predefined operation calls the command interrupt signal), a command operation code or OPCODE (e.g. multiple bits, which indicate a type of interrupt, such as a command interrupt, a suspend interrupt, a resume interrupt, a reset interrupt or the like) and / or receive one or more other interrupt signals based on which the flow control processing unit 402a a subroutine can select / determine one or more instructions for one or more processing units 402a-d . 404a-n of the microcontroller 150 having.

A flow control processing unit 402a may respond to a hard interrupt request in certain embodiments, may receive a received command index into a program counter of the microcontroller 150 Copy (e.g. into the lower bits or another predefined location of the program counter) or the like. An instruction that corresponds to the instruction index in the program counter can have an unconditional branch instruction that points to a Directs the target subroutine to perform the requested operation.

In one embodiment, a flow control processing unit 402a one or more other processing units 402a-d . 404a-n manage to avoid a write-after-read risk and / or one or more other dangers (e.g. read-after-write risks, write-after-write risks, structural risks, control risks or the like). For example, a flow control processing unit 402a use an instruction for a single interrupt wait (SIW) and / or a group interrupt wait (GIW) as wait instructions or the like to proactively detect a status outside the flow control processing unit 402a check and wait (e.g., waiting for a soft / logical interrupt signal, a hard / physical interrupt signal, another predefined condition, or the like) to execute order to avoid write-after-read -Danger to force another danger or the like.

In certain embodiments, a flow control processing unit 402a an order of execution for one or more other processing units 402a-d . 404a-n Manage using one or more interrupt waiting instructions (e.g. SIW and / or GIW). For example, a flow control management unit 402a execute a first sequence of instructions, execute a SIW and / or GIW instruction which identifies an interrupt condition (e.g. an external signal or the like), wait for the interrupt condition and execute a second sequence of instructions in response to the fulfillment of the interrupt condition.

A GIW wait instruction is essentially similar to a SIW wait instruction in one embodiment, except that it causes the flow control processing unit 402a waiting for multiple interrupt signals in a predefined group (e.g. multiple interrupt signals physically grouped in hardware or the like). In certain embodiments, a GIW wait instruction may be set up to selectively use the binary operator AND or the binary operator OR among the selected plurality of interrupt signals. For example, if a binary AND operator is selected, the GIW wait instruction waits until it receives all of the selected multiple interrupt signals. If a binary OR operator is selected, the GIW wait instruction waits until it receives one of the selected multiple interrupt signals, whereupon the flow control processing unit's GIW wait instruction 402a allowed to continue.

In certain embodiments, when multiple target interrupt signals are not physically grouped, and therefore a GIW wait instruction cannot be used for the multiple target interrupt signals, a flow control processing unit can 402a support a sequence of successive SIW instructions, which together can behave as a single GIW instruction, or the like.

In one embodiment, a flow control processing unit functions 402a as the command center of one or more other processing units 402b-d . 404a-n , A flow control processing unit 402a can send commands and / or data to other processing units 402b-d . 404a-n send and monitor their status. This one-to-all communication pattern can reduce microcode and design complexity in certain embodiments. In one embodiment, one may be from the flow control processing unit 402a statement storage space used 406 to minimize and / or to prevent the flow control processing unit 402a becomes a performance bottleneck, the flow control processing unit 402a control and track some tasks, but other tasks for one or more processing units 402b-d . 404a-n access without monitoring and / or tracking a current status.

For control by a flow control processing unit 402a To facilitate and / or simplify, in certain embodiments, one or more other processing units 402b-d . 404a-n have a substantially similar interface (e.g. a standard interface or the like). One or more different processing units 402a-d . 404a-n can have a standard interface, but can support a different set of instructions to perform different categories and / or types of tasks.

During many tasks (e.g. with complex algorithms and / or repeated execution) by the processing units 402b-d . 404a-n via the standard interface protocol of the flow control processing unit 402a can be controlled, there may be other small and / or one-time tasks for certain types of operations. In embodiments where there are many such small tasks, the flow control processing unit can 402a have an extended and / or customizable interface to support the tasks for new ones Provide tasks over time, for custom tasks, or the like.

For example, the flow control processing unit 402a one or more instruction tables in a control register array (e.g. 64 bits by 16 bits or the like) of the microcontroller 150 support. A control register array can be accessed in certain embodiments by the instructions of the flow control processing unit 402a can be accessed for loading (LOD) and / or saving (STR). At least a portion of the space of the control register array can be virtual because of the design of the flow control processing unit 402a may occupy only a subset of the space (e.g. 5 of the 64 registers or the like). The rest of the control register arrangement can be relatively independent of the flow control processing unit 402a , for use by custom tasks or the like. One or more registers in the control register array that are not for the flow control processing unit 402a reserved, in certain embodiments, can store custom command tables to extend the functionality of the microcontroller to perform small tasks, one-time tasks, new tasks over time, or the like.

In some embodiments, a one-to-all communication pattern back and forth signal / command pairs may exist between the flow control processing unit 402a and the timing processing unit 402b use which is the speed of the microcontroller 150 can control. An output from the timing processing unit 402b can be attached to one or more peripheral modules of the storage array during an entire memory access operation 200 are provided to control the timing of the memory access operation. If the flow control processing unit 402a the only main module in the microcontroller 150 remains, it can monitor the progress of the timing processing unit 402b for each step of a memory access operation on a memory array 200 using processing time and / or overhead of volatile memory 406 monitor to the flow control processing unit 402a and the timing unit 402b to synchronize as the flow control processing unit 402a Commands to the timing unit 402b sends and feedback signals from the timing processing unit 402b receives (e.g. via the interrupt interface of the flow control processing unit 402a or similar).

The parallelism of the processing units 402a-d . 404a-n and / or pipelines of a microcontroller 150 improve, to reduce a number of microcode lines, instruction / data storage space 406 to save or the like, one or more of the processing units 402a-d . 404a-n have one or more buffer and / or output stages. While the flow control processing unit 402a still a master for the microcontroller 150 can be when activated by the flow control processing unit 402a the timing processing unit 402b a proxy for the flow control processing unit 402a the other processing units in real time 402c-d . 404a-n for one or more storage operations on a storage array 200 triggers.

The timing processing unit 402b may have knowledge of the progress of the storage operation since the timing unit 402b the timing and / or the speed of the entire microcontroller 150 can control. The timing processing unit 402b may have more available space (e.g. in with the timer 402b linked volatile memory 406 ) to expand the instruction set of the timing processing unit 402b have as the flow control processing unit 402a which can be used to enable the timing processing unit 402b as a proxy for the flow control processing unit 402a acts. For example, only a small portion of space in the instruction processing table of the timing processing unit 402b filled with instruction identification code, arguments, and switches (e.g., enable / disable bits), creating space in the instruction encoding table of the timing processing unit 402b to include further arguments and switches remains.

In certain embodiments, excess capacity of the instruction processing table of the timing processing unit 402b store an array (e.g., an 8-bit array or the like), the trigger for use by the timing processing unit 402b to trigger the other processing units 402c-d . 404a-n or the like. For example, the flow control processing unit 402a the timing processing unit 402b start and / or initiate to execute a subroutine. The timing processing unit 402b can be used as a background process (e.g. in parallel with the flow control processing unit 402a) are executed to trigger one or more of the flow control processing unit 402a , the data latch control unit 402c , the voltage control processing unit 402d , one or more external processing units 404a-n or the like.

The flow control processing unit 402a can issue a build command to one or more other processing units 402b-d . 404a-n send to create a next task, provide an update, create an output in a buffer, or the like. The flow control processing unit 402a can trigger the timing processing unit in various embodiments depending on the assigned task 402b wait or not wait to send a next build command. The timing processing unit 402b can be one or more other processing units 402a . 402c . 402d . 404a-n trigger to copy a buffer value to an associated output stage or the like (e.g., to complete a task, to trigger a next step of a task, or the like).

The flow control processing unit 402a can send an initialization command (eg start command, creation command or the like) to a processing unit 402b-d . 404a-n send, and the timing processing unit 402b can trigger to initiate subsequent sections of a task to a processing unit 402c-d . 404a-n can send feedback to the flow control processing unit 402a send (e.g. via an interrupt port or another interrupt interface of the flow control processing unit 402a) or similar. A trigger signal from the timing processing unit 402b can be another processing unit 402c-d . 404a-n trigger to provide an output signal, value, or the like (e.g., the data latch control processing unit 402c to load a value into a data latch, the voltage control processing unit 402d to provide an output voltage or the like) to complete a task, as an intermediate step of a task or the like.

For example, the voltage control processing unit 402d binary and / or digital values from the microcontroller 150 into analog voltages for the memory array 200 convert (e.g. programming voltages, erase voltages, read voltages, bias voltages, word line voltages, bit line voltages, reverse voltages or the like). The data latch control processing unit 402c may, in certain embodiments, one or more data buffers for the memory array, logic circuitry for the memory array 200 (e.g., YLOG logic circuits that the sense amplifiers 250 , Read / write circuits 230 , Row decoder 240 or the like) and / or other circuitry for a memory array 200 an integrated circuit device 123 Taxes.

In one embodiment, the data latch control processing unit 402c Data from a volatile memory 406 decode into a command index (e.g., decode 32-bit and / or 64-bit SRAM data into one or more command indexes or the like). The data latch control processing unit 402c may, in certain embodiments, translate decoded instruction indexes into one or more instructions (e.g., YLOG instructions) using hard-coded combination logic and / or other rules. The data latch control processing unit 402c can buffer a predetermined number of instructions per clock cycle or set of clock cycles. For example, the data laundering control processing unit 402c Buffer four instructions per clock cycle and issue one of the four logical instructions per quarter of a clock cycle (e.g., every 20 nanoseconds for an 80 nanosecond clock cycle or the like). The data latch control processing unit 402c can have predefined command sequences (e.g. YLOG command sequences) in volatile memory 406 or save the like.

For example, in one embodiment, the data latch control processing unit 402c about 64, 128 . 256 or store more command sequences, each having one or more ordered lists of commands. A command sequence may include a single command, multiple commands, up to five commands, up to ten commands, up to thirteen commands, up to fifteen commands, up to twenty commands, more than twenty commands, or the like, in various embodiments.

A microcontroller 150 can provide flexible control of values stored in data latches, the data latch control processing unit 402c Stores data in data latches based on instruction indices decoded into instruction sequences and the flow control processing unit 402a selectively overrides data stored in one or more data latches. For example, the flow control processing unit 402a the data latch control processing unit 402c initiate to execute a subroutine (e.g., microcode or other computer-executable program code) to create an instruction sequence (e.g., one or more instructions for the memory array 200 and / or for sense amplifiers 250 , Read / write circuits 230 , Row decoder 240 or the like), the flow control processing unit 402a can store one or more data values directly in one or more data latches; the flow control processing unit 402a can mask, truncate, modify, update, and / or override a command index for the data latch.

In certain embodiments, a read command for a memory array 200 have a higher priority than a programming and / or erase command (e.g., read operations in NAND flash memory can be performed substantially faster than programming and / or erase operations or the like). The microcontroller 150 may switch from executing a program or erase instruction sequence to a read instruction sequence or the like in response to receiving an interim read request, and switch back to the program or erase instruction sequence in response to termination of the read instruction sequence. The microcontroller 150 can switch back to the programming or erase subroutine where it left off in the programming or erase command sequence.

In one embodiment, a microcontroller 150 include a set of shadow registers that provide status for the microcontroller 150 save, which shows where the suspension took effect. However, in a particular embodiment, to use less power and slot than shadow registers, the flow control processing unit can 402a a register file and pending instruction sequences for the processing units 402a-d . 404a-n push to a thread change stack and can pop the register file and pending instruction sequences from the thread change stack in response to resuming the program or delete operation after an interim read. The processing units 402a-d . 404a-n may begin the interrupted programming or reading operation from where it left off, or may rerun certain instructions in the instruction sequence to restore the correct operating state, or the like. Using a thread switch stack can have fewer registers than using shadow registers for the entire microcontroller 150 add while allowing the flow control processing unit 402a and the timing processing unit 402b remain synchronized so that other processing units 402c-d . 404a-n are able to create the correct buffer values when the timing processing unit 402b it triggers even after an interrupted programming or erasing operation is resumed.

5 represents an embodiment of a system 500 with multiple on-die memory microcontroller cores 150a-n represented by a thread management unit 502 synchronized and / or managed. In the illustrated embodiment, each of the microcontroller cores 150a-n a similar size (e.g. it can have similar processing units 302a - 302d , a similar number of processing units 302a - 302d or the like).

Any microcontroller core 150a-n may, in certain embodiments, have a different subset of storage media 122 (e.g., one or more different dies, die levels, blocks, erase blocks, or the like), each capable of performing programming, reading, and / or erasing operations on the linked subsets of storage media 122 perform. In a further embodiment, different microcontroller cores can be used 150a-n be set up to perform programming, reading and / or erasing operations on any selected subset of storage media 122 (e.g., one or more different dies, die levels, blocks, erase blocks, or the like).

6 represents another embodiment of a system 600 with multiple on-die memory microcontroller cores 150a-n and a thread management unit 502 In the illustrated embodiment, a microcontroller core has 150a a larger size than one or more additional microcontroller cores 150b-n (e.g. the microcontroller core 150a more and / or larger processing units 302a - 302d than the one or more additional microcontroller cores 150b-n with fewer and / or smaller processing units 302a-c have or the like).

Multiple microcontroller cores 150a-n full size, everyone with full skills as in 5 can represent a larger amount of energy and / or circuit area of an integrated circuit device 123 consume. In 6 closes the system 600 one or more microcontroller cores 150a full size and one or more reduced and / or partial microcontroller cores 150b-n on (e.g., to save energy, reduce circuit size, or the like). For example, in the illustrated embodiment, a first microcontroller core points for illustration purposes only 150a full-size four processing units 302a-d on while one or more partial and / or reduced size microcontroller cores 150b-n three processing units 302a-c have (e.g. less than the controller core 150a in full size).

With the one or more partial and / or reduced in size microcontroller cores 150b-n unnecessary registers, rarely used instructions, pointer stacks, register file entries or the like may have been removed to reduce the size. Partial and / or reduced in size microcontroller cores 150b-n may be able in certain embodiments However, performing all user mode operations, a predefined set of user mode operations, or the like may be smaller than a full microprocessor core 150a full size. A complete microcontroller 150a full size may be able to perform both user mode operations and built-in self test test mode operations.

For example, a full microcontroller 150a a full-size flow control processing unit 402a have a built-in self-test processing unit, while the partial and / or reduced in size microcontroller cores 150b-n Flow control processing units 402a can have without built-in self-test processing units. In a further embodiment, a complete microcontroller 150a a full-size flow control processing unit 402a have both a read processing unit and a programming / writing processing unit, while the partial and / or reduced in size microcontroller cores 150b-n Flow control processing units 402a with reading processing units, but without programming / writing processing units.

The complete microcontroller 150a Full size can be one or more operations (e.g., programming, erasing, built-in self-test operations, or the like) for each different subset of storage media 122 an integrated circuit device 123 (e.g. one or more different dies, die levels, blocks, erase blocks or the like) because the one or more partial and / or reduced-sized microcontroller cores 150b-n that may not support one or more operations. In certain embodiments, for operations each of the microcontroller cores 150a-n supports (e.g. read operations) the various microcontroller cores 150a-n different subsets of storage media 122 an integrated circuit device 123 (e.g. one or more dies, die levels, blocks, erase blocks, or the like).

For example, in one embodiment, a die of an integrated circuit device 123 have multiple die levels (e.g., four die levels), each with separate storage arrays 200 that are able to perform memory operations in parallel. The levels can be at the same level (e.g., one or more layers of semiconductors, metal, or other conductors, insulators, or the like) of an integrated circuit device 123 to each other (e.g. adjacent on the same step) or in parallel on different staggered steps or the like.

In one embodiment, each die level can have a different microcontroller core 150a-n for from each of the microcontroller cores 150a-n supported operations (e.g., read operations) may be assigned while a single microcontroller core 150a (e.g. a full microcontroller core 150a full size) one or more operations that are not performed by each of the microcontroller cores 150a-n can be carried out for each die level (e.g. programming operations, delete operations, built-in self-test operations or the like). For example, in one embodiment with four die levels, one microcontroller core 150a full-size capable of performing programming operations for each of the four die levels, and three additional reduced-size microcontroller cores 150b-n , with all four microcontroller cores 150a-n are assigned different die levels for performing read operations, up to four read operations are performed in parallel, or three read operations and one programming operation or the like.

In this way, in certain embodiments, high priority operations (e.g., read operations or the like) can be performed in parallel on multiple memory dies or other memory areas, and yet power consumption and circuit size can be minimized. Performing only a single program and / or erase operation may be optimal for power management in certain embodiments due to the peak power used for program and / or erase operations, while read operations may use less power.

The one or more smaller, smaller-sized microcontroller cores 150b-n may each have a timing processing unit in one embodiment 402b lock in. In certain embodiments, a flow control processing unit 402a for one or more smaller, smaller-sized microcontroller cores 150b-n be smaller (e.g., reduced, removed, with a smaller set of instructions, with enough logic to perform a read operation but not a programming operation, or the like) than in the larger microcontroller core 150a full size.

In a further embodiment, the one or more smaller, reduced-size microcontroller cores 150b-n may not be a flow control processing unit 402a but some of the logic and / or functionality of the flow control processing unit 402a with a timing processing unit 402b or the like can be combined. Several smaller, smaller-sized microcontroller cores 150b-n can, in one embodiment, a single data latch control processing unit 402c or share the like. In certain embodiments, both microcontroller cores 150a full-size and reduced-size microcontroller cores 150b-n use the same firmware code, but can execute different subroutines or the like. Volatile memory buffers 406 may be reduced in size, shared, eliminated, or the like, in one embodiment, to reduce the circuit size in one or more reduced-size microcontroller cores 150b-n to reduce.

In certain embodiments, it can be for any microcontroller core 150a-n be advantageous individual timing processing units 402b include so that every channel, every die level or any other subset of storage media 122 an integrated circuit device 123 can receive a continuous, individual time control. In a further embodiment, each microcontroller core can 150a-n individual flow control processing units 402a include, since a thread change between different microcontroller cores 150a-n due to the increased synchronization between the different microcontroller cores 150a-n and the frequent change can be detrimental to performance. A reduced version of a flow control processing unit 402a and / or a timing processing unit 402b (e.g., to handle read operations, but not programming operations, or the like) may have reduced instruction sets, reduced volatile memory 406 or the like.

The Thread Management Unit (TMU) 502 distributes commands to different microcontroller cores in certain embodiments 150a-n (e.g. commands for different channels, die levels and / or other subsets of storage media 122 an integrated circuit device 123 or similar). For example, the thread management unit 502 Commands from a device controller 126 received (eg read commands, write / program commands, delete commands, test commands or the like) and a microcontroller core 150a-n select (e.g. based on an address or other indicator of the command based on which microcontrollers 150a-n are available and / or busy, or the like). The thread management unit 502 can return a status of a command to the device controller 126 report (e.g., in response to a microcontroller completing a command, a status of the load during the execution of a command, or the like).

The thread management unit 502 may, in various embodiments, share resources between microcontroller cores 150a-n (e.g. external processing units 404a-n , shared volatile memory 406 or the like) can allocate energy for the microcontroller cores 150a-n manage (e.g. different microcontroller cores 150a-n wake up and / or go to sleep to manage energy, or the like), conflicts and / or collisions between microcontroller cores 150a-n manage and / or otherwise between the different microcontroller cores 150a-n coordinate.

In certain embodiments, the thread manager 502 Instructions from each flow control processing unit 402a of the different microcontroller cores 150a-n to a target timing processing unit 402b send, thereby causing communication, shared tasks, transferred tasks or the like between a flow control processing unit 402a a microcontroller core 150a-n and a timing processing unit 402b of another microcontroller core 150a-n be made possible.

For example, a flow control processing unit 402a for a larger microcontroller 150a Full-size programming operations for any die level or any other subset of storage media 122 an integrated circuit device 123 manage while timing processing units 402b the microcontroller cores 150a-n other die levels or other subsets of storage media 122 can be assigned (e.g. to simplify placement and routing of conductor tracks or the like), and the thread management unit 502 can receive commands, tasks or the like from the flow control processing unit 402a to the other timing processing units 402b for programming operations to send commands from the flow control processing unit 402a with the right channels (e.g. die levels) for the programming operations.

The thread management unit 502 may, in certain embodiments, use a mapping table and a multiplexer to carry out operations, commands and / or tasks from the flow control processing unit 402a of the microcontroller 150a full-sized to the timing processing unit 402b routing associated with the channel for the programming operation and tasks from the other flow control processing units 402a (e.g. from those in size reduced microcontrollers 150b-n) to the timing processing units 402b to manage that are linked to their respective channels.

7 10 is a schematic block diagram illustrating one embodiment of an integrated circuit device 700 with an on-die memory microcontroller 150 illustrated. In the illustrated embodiment, there is a memory array 200 (e.g., one or more die levels or the like) at one level of the integrated circuit device 700 (e.g. one or more layers of conductors, insulators, semiconductors or the like) and the microcontroller 150 and other switching logic 704 (e.g., sense amplifiers, word line switches, or the like) are at another level of the integrated circuit device 700 (e.g. under the array 200 ) and are via one or more connections 702 (e.g. insulation layers, conductive layers, through silicon vias, holes, buses or the like) in communication with the memory array 200 , In the illustrated embodiment, the memory array is located 200 at a first stage of the integrated circuit device 700 , and the microcontroller 150 is on a second stage of the integrated circuit device 700 that is parallel to and offset from the first stage. A substrate 706 has a third stage of the integrated circuit device 700 (e.g., a support structure on which one or more other layers are formed and / or deposited) and is parallel to and offset from the other layers.

8th 10 is a schematic flow diagram illustrating one embodiment of a method 800 for an on-die memory microcontroller 150 illustrated. The procedure 800 starts, and a microcontroller 150 receives 802 a request for a memory operation (e.g., a read request, a write / program request, an erase request, or the like) for a memory array 200 an integrated circuit device 123 ,

A flow control processing unit 402a and / or a thread management unit 502 has 804 Tasks for the received 802 Request for the storage operation different processing units 302a-n . 402a-d . 404a-n to. One or more processing units 302a-n . 402a-d . 404a-n to lead 806 the assigned tasks 804 to complete the save operation and the procedure 800 ends.

9 10 is a schematic flow diagram illustrating one embodiment of a method 900 for an on-die memory microcontroller 150 illustrated. The procedure 900 starts, and a microcontroller 150 receives 902 a request for a memory operation (e.g., a read request, a write / program request, an erase request, or the like) for a memory array 200 an integrated circuit device 123 ,

A flow control processing unit 402a and / or a thread management unit 502 certainly 904 Tasks for the received 902 Store operation request. The flow control processing unit 402a and / or the thread management unit 502 certainly 906 whether there are flow control tasks and the flow control processing unit 402a leads 908 the certain 906 Flow control duties. The flow control processing unit 402a and / or the thread management unit 502 certainly 910 whether there are timing tasks and a timing processing unit 402b leads 912 the certain 910 Time control tasks. The flow control processing unit 402a and / or the thread management unit 502 certainly 914 whether there are voltage control tasks and the voltage control processing unit 402d leads 916 the certain 914 Voltage control tasks. The flow control processing unit 402a and / or the thread management unit 502 certainly 918 whether there are data latch control tasks and the data latch control processing unit 402c leads 920 the certain 918 Data latch control tasks. The procedure 900 continues and the microcontroller 150 receives 902 one or more additional requirements for storage operations.

In various embodiments, means for storing data can be a storage device 120 , a storage medium 122 , a storage element 123 , a storage array 200 , a volatile storage medium 122 (e.g. RAM, DRAM, SDRAM, DDR-SDRAM, SRAM, T-RAM, Z-RAM or the like), a non-volatile storage medium 122 (e.g. ReRAM, memristor memory, programmable metallization cell memory, PCM, PCME, PRAM, PCRAM, Ovonic Unified Memory, C-RAM, NAND flash memory, 2D NAND flash memory, 3D NAND flash memory, NOR flash memory, nano- RAM or NRAM, wire-based nanocrystal memory, silicon oxide-based sub-10-nanometer process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, magnetic storage media such as a hard disk or tape drive, optical storage media, SCM or the like) or include the like. Other embodiments may include similar or equivalent means for storing data.

In various embodiments, means for sorting tasks by task category can be a microcontroller 150 , a flow control processing unit 402a , a thread management unit 502 , a data latch control processing unit 402c , an integrated circuit device 123 and / or other logical hardware or computer executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means of sorting tasks by task category.

Means for executing different categories of tasks in parallel can be a microcontroller in different embodiments 150 , a flow control processing unit 402a , a timing processing unit 402b , a data latch control processing unit 402c , a voltage control processing unit 402d , an external processing unit 404a-n , another processing unit 302a-n . 402a-d . 404a-n , an integrated circuit device 123 and / or other logical hardware or computer executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means of performing different categories of tasks in parallel.

Means for performing fewer categories of tasks using a different set of processing units may be a microcontroller in various embodiments 150 , a flow control processing unit 402a , a timing processing unit 402b , a data latch control processing unit 402c , a voltage control processing unit 402d , an external processing unit 404a-n , another processing unit 302a-n . 402a-d . 404a-n , an integrated circuit device 123 and / or other logical hardware or computer executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means of performing fewer categories of tasks using a different set of processing units.

The present disclosure can be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims (25)

Having device: an array of non-volatile memory cells in an integrated circuit device; a microcontroller unit in the integrated circuit device; and a plurality of processing units of the microcontroller unit, wherein different processing units execute different categories of tasks in parallel for the array of non-volatile memory cells. Device according to Claim 1 , further comprising one or more additional microcontroller units in the integrated circuit device, the one or more additional microcontroller units having fewer processing units than the microcontroller unit and performing fewer categories of tasks. Device according to Claim 2 , wherein the plurality of processing units of the microcontroller unit have a built-in self-test unit which is set up to carry out a multiplicity of test operations on the array of non-volatile memory cells, and the fewer processing units of the one or more additional microcontroller units have no built-in self-test unit. Device according to Claim 2 , wherein the plurality of processing units of the microcontroller unit are configured to perform programming and reading operations on the array of non-volatile memory cells, and the fewer processing units of the one or more additional microcontroller units are configured to perform reading operations and no programming operations on the array of non-volatile memory cells. Device according to Claim 4 wherein the microcontroller unit is configured to perform the programming operations on each subset of the array of non-volatile memory cells and the one or more additional microcontroller units are configured to perform read operations on different subsets of the array of non-volatile memory cells. Device according to Claim 1 , wherein the array of non-volatile memory cells is on a first level of the integrated circuit device and the microcontroller unit is on a second level of the integrated circuit device, the second level being parallel to and offset from the first level. Device according to Claim 1 , wherein a clock rate for the microcontroller unit is set lower than a clock rate with which the microcontroller can perform data operations on the array of non-volatile memory cells in series with a single processing unit without increasing a latency of the data operations, the plurality of processing units of the microcontroller unit performing data operations in parallel Execute on the array of non-volatile memory cells at the set clock rate without increasing the latency of the data operations. Device according to Claim 1 , wherein the plurality of processing units of the microcontroller unit support different sets of instructions associated with the different categories of tasks. Device according to Claim 1 wherein the plurality of processing units include one or more of a flow control processing unit, a timing processing unit, a voltage control processing unit, and a data latch control processing unit. Device according to Claim 1 , wherein the various categories of tasks include one or more of flow control tasks, timing control tasks, data latch control tasks, voltage control tasks, and built-in self-test tasks. Device according to Claim 1 , further comprising volatile memory of the integrated circuit device, wherein the plurality of processing units store data in the volatile memory to perform the various categories of tasks, wherein a built-in self-test unit of the plurality of processing units test data read from the array of non-volatile memory cells in stores a portion of the volatile memory, the portion of the volatile memory being otherwise used by other processing units of the plurality of processing units when not in a test mode of the built-in self-test unit. System, comprising: an integrated circuit device comprising a non-volatile storage medium; a microcontroller with a plurality of processing units for performing tasks for the non-volatile storage medium; and one or more additional microcontrollers, having fewer processing units than the microcontroller. System according to Claim 12 , wherein different processing units of the plurality of processing units perform different types of tasks in parallel for the non-volatile storage medium and the one or more additional microcontrollers perform fewer types of tasks than the microcontroller. System according to Claim 12 , wherein the non-volatile storage medium is arranged on a first stage of the integrated circuit device and the microcontroller and the one or more additional microcontrollers are arranged on a second stage of the integrated circuit device, the second stage being parallel to and offset from the first stage. System according to Claim 12 , wherein the plurality of processing units of the microcontroller have a built-in self-test unit, which is set up to carry out a multiplicity of test operations on the non-volatile storage medium, and the fewer processing units of the one or more additional microcontrollers have no built-in self-test unit. System according to Claim 12 , wherein the plurality of processing units of the microcontroller are set up to carry out programming operations and reading operations on the non-volatile storage medium, and the fewer processing units of the one or more additional microcontrollers are set up to carry out reading operations and no programming operations on the non-volatile storage medium. System according to Claim 16 , wherein the microcontroller unit is configured to perform the programming operations on each die level of the non-volatile storage medium, and the one or more additional microcontroller units are configured to perform reading operations on different die levels of the non-volatile storage medium. Apparatus comprising: means for storing data; Means for sorting tasks for the means for storing data by task category; and means for performing different categories of tasks in parallel for the means for storing data using different ones Processing units for the means for storing data. Device according to Claim 18 , further comprising means for performing fewer categories of tasks for the data storage means using a different set of processing units for the data storage means. Device according to Claim 18 , the means for storing data being arranged on a first stage of an integrated circuit device and the means for carrying out different categories of tasks and the different processing units being arranged on a second stage of the integrated circuit device, the second stage being parallel to and offset from the first stage is. Process, comprising: Receiving a request for a store operation; Determining a plurality of tasks to complete the storage operation, wherein different tasks of the plurality of tasks are associated with different sets of instructions; and executing the various tasks of the plurality of tasks in parallel using different processing units of a microcontroller, the different processing units supporting the different instruction sets. Procedure according to Claim 21 , further comprising performing a subsequent memory operation using an additional microcontroller with fewer processing units than the microcontroller and supporting fewer sets of instructions. Having device: a microcontroller for a memory array of an integrated circuit device, the microcontroller being set up to: select a plurality of tasks for a memory operation using a first processing unit; control the timing of the plurality of tasks for the memory operation using a second processing unit; and Set voltages for the plurality of tasks for the memory operation using a third processing unit. Device according to Claim 23 , further comprising one or more additional microcontrollers for the integrated circuit device, the one or more additional microcontroller units having fewer processing units than the microcontroller. Device according to Claim 24 , wherein the microcontroller is configured to perform programming operations, read operations and test operations, and the one or more additional microcontrollers are configured to perform read operations and not programming operations and test operations.

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