CN116069100A - Band gap reference circuit, chip and electronic equipment - Google Patents

Band gap reference circuit, chip and electronic equipment Download PDF

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Publication number
CN116069100A
CN116069100A CN202211702446.XA CN202211702446A CN116069100A CN 116069100 A CN116069100 A CN 116069100A CN 202211702446 A CN202211702446 A CN 202211702446A CN 116069100 A CN116069100 A CN 116069100A
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transistor
coupled
electrode
voltage
circuit
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吕桄甫
于翔
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Shengbang Microelectronics Suzhou Co ltd
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Shengbang Microelectronics Suzhou Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

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Abstract

Embodiments of the present disclosure provide a bandgap reference circuit, a chip, and an electronic device. The bandgap reference circuit comprises a bandgap reference core circuit, a current mirror circuit, a voltage control circuit, a current source circuit, and first and second shunt circuits. The bandgap reference core circuit generates a core current. The current mirror circuit generates a mirror current of the core current and provides the mirror current to the voltage control circuit via the first node. The voltage control circuit enables the voltage of the first node to have a negative temperature coefficient and controls the temperature change rate of the voltage of the first node according to the mirror current. The current source circuit generates a constant current. The first shunt circuit generates a first shunt according to the voltage and the constant current of the third node. The second shunt circuit generates a second shunt according to the voltage of the first node and the constant current and causes the core current to be reduced in magnitude of the second shunt. The temperature change rate of the voltage of the third node is smaller than the temperature change rate of the voltage of the first node so that the second shunt has a positive temperature coefficient.

Description

Band gap reference circuit, chip and electronic equipment
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to bandgap reference circuits, chips, and electronic devices.
Background
Bandgap reference circuits are widely used in integrated circuits as a reference source that is insensitive to temperature variations. Inside the bandgap reference circuit, a lower temperature coefficient voltage/current can be achieved by superposition of a positive temperature coefficient voltage/current and a negative temperature coefficient voltage/current. However, the existing bandgap reference circuits have voltage/current with nonlinear temperature coefficients inside. In order to achieve lower temperature coefficient voltages/currents, a higher order curvature temperature compensation is required in addition to the linear temperature coefficient term.
Disclosure of Invention
Embodiments described herein provide a bandgap reference circuit, a chip, and an electronic device.
According to a first aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: the circuit comprises a band gap reference core circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first shunt circuit and a second shunt circuit. Wherein the bandgap reference core circuit is configured to: a core current is generated and a reference voltage is generated from the core current. The current mirror circuit is configured to: an image current of the core current is generated and provided to the voltage control circuit via the first node. The voltage control circuit is configured to: so that the voltage of the first node has a negative temperature coefficient, and the temperature change rate of the voltage of the first node is controlled according to the mirror current. The current source circuit is configured to: a constant current is generated and provided to both the first shunt circuit and the second shunt circuit together via the second node. The first shunt circuit is configured to: the first shunt is generated from the voltage and the constant current of the third node. Wherein the third node is a node having a negative temperature coefficient within the bandgap reference core circuit. The second shunt circuit is configured to: the second shunt is generated from the voltage and constant current of the first node and is provided to the bandgap reference core circuit such that the core current is reduced in magnitude. Wherein the rate of change of temperature of the voltage at the third node is less than the rate of change of temperature of the voltage at the first node such that the second shunt has a positive temperature coefficient.
In some embodiments of the present disclosure, a bandgap reference core circuit includes: first to fifth transistors, first to fourth resistors, and an operational amplifier. The control electrode of the first transistor is coupled with the control electrode of the second transistor and the output end of the operational amplifier. The first electrode of the first transistor is coupled to the first voltage terminal. The second pole of the first transistor is coupled to the first input terminal of the op-amp, the first terminal of the first resistor, and the first terminal of the second resistor. The first electrode of the second transistor is coupled to the first voltage terminal. The second diode of the second transistor is coupled to the second input terminal of the op-amp, the first terminal of the third resistor, and the control electrode and the second diode of the fourth transistor. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second end of the second resistor. The first electrode of the third transistor is coupled to the second voltage terminal. The first electrode of the fourth transistor is coupled to the second voltage terminal. The second end of the first resistor is coupled to the second voltage end. The second end of the third resistor is coupled to the second voltage end. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first electrode of the fifth transistor is coupled to the first voltage terminal. The second pole of the fifth transistor is coupled to the first end of the fourth resistor and the output voltage end. The second terminal of the fourth resistor is coupled to the second voltage terminal. The third node is any one input end of the operational amplifier.
In some embodiments of the present disclosure, a current mirror circuit includes: and a sixth transistor. The control electrode of the sixth transistor is coupled to the control electrode of the first transistor. The first electrode of the sixth transistor is coupled to the first voltage terminal. The second pole of the sixth transistor is coupled to the first node.
In some embodiments of the present disclosure, the voltage control circuit includes: and a seventh transistor. The control electrode of the seventh transistor is coupled to the second electrode of the seventh transistor. The first electrode of the seventh transistor is coupled to the second voltage terminal.
In some embodiments of the present disclosure, a current source circuit includes: and an eighth transistor. The control electrode of the eighth transistor is coupled to the control electrode of the first transistor. The first electrode of the eighth transistor is coupled to the first voltage terminal. The second pole of the eighth transistor is coupled to the second node.
In some embodiments of the present disclosure, the first shunt circuit includes: and a ninth transistor. The control electrode of the ninth transistor is coupled to the third node. The first pole of the ninth transistor is coupled to the second node.
The second pole of the ninth transistor is coupled to the first node.
In some embodiments of the present disclosure, the second shunt circuit includes: a tenth transistor and an eleventh transistor. The control electrode of the tenth transistor is coupled to the first node. The first pole of the tenth transistor is coupled to the second node. The second pole of the tenth transistor is coupled to the second input terminal of the op-amp. The control electrode of the eleventh transistor is coupled to the first node. The first pole of the eleventh transistor is coupled to the second node. The second pole of the eleventh transistor is coupled to the first input terminal of the op-amp.
According to a second aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: first to eleventh transistors, first to fourth resistors, and an operational amplifier. The control electrode of the first transistor is coupled with the control electrode of the second transistor and the output end of the operational amplifier. The first electrode of the first transistor is coupled to the first voltage terminal. The second pole of the first transistor is coupled to the first input terminal of the op-amp, the first terminal of the first resistor, and the first terminal of the second resistor. The first electrode of the second transistor is coupled to the first voltage terminal. The second diode of the second transistor is coupled to the second input terminal of the op-amp, the first terminal of the third resistor, and the control electrode and the second diode of the fourth transistor. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second end of the second resistor. The first electrode of the third transistor is coupled to the second voltage terminal. The first electrode of the fourth transistor is coupled to the second voltage terminal. The second end of the first resistor is coupled to the second voltage end. The second end of the third resistor is coupled to the second voltage end. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first electrode of the fifth transistor is coupled to the first voltage terminal. The second pole of the fifth transistor is coupled to the first end of the fourth resistor and the output voltage end. The second terminal of the fourth resistor is coupled to the second voltage terminal. The control electrode of the sixth transistor is coupled to the control electrode of the first transistor. The first electrode of the sixth transistor is coupled to the first voltage terminal. The second pole of the sixth transistor is coupled to the control pole of the seventh transistor and the second pole. The first electrode of the seventh transistor is coupled to the second voltage terminal. The control electrode of the eighth transistor is coupled to the control electrode of the first transistor. The first electrode of the eighth transistor is coupled to the first voltage terminal. The second pole of the eighth transistor is coupled to the first pole of the ninth transistor, the first pole of the tenth transistor, and the first pole of the eleventh transistor. The control electrode of the ninth transistor is coupled to any one of the input terminals of the op-amp. The second pole of the ninth transistor is coupled to the second pole of the sixth transistor. The control electrode of the tenth transistor is coupled to the control electrode of the eleventh transistor and the second electrode of the sixth transistor. The second pole of the tenth transistor is coupled to the second input terminal of the op-amp. The second pole of the eleventh transistor is coupled to the first input terminal of the op-amp.
According to a third aspect of the present disclosure, a chip is provided. The chip comprises a bandgap reference circuit according to the first or second aspect of the present disclosure.
According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a chip according to the third aspect of the present disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is an exemplary circuit diagram of a bandgap reference circuit;
FIG. 2 is a waveform diagram of some signals for the bandgap reference circuit shown in FIG. 1;
FIG. 3 is a schematic block diagram of a bandgap reference circuit according to an embodiment of the disclosure;
FIG. 4 is an exemplary circuit diagram of a bandgap reference circuit in accordance with an embodiment of the present disclosure; and
fig. 5 is a waveform diagram of some signals for the bandgap reference circuit shown in fig. 4.
In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. In addition, for convenience of unified expression, in the context, the base of a bipolar transistor (BJT) is referred to as a control electrode, the emitter of the BJT is referred to as a first electrode, and the collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Fig. 1 shows an exemplary circuit diagram of a bandgap reference circuit 100. In the example of fig. 1, the transistor M2, the transistor Q3, the transistor Q4, the transistor M5, the resistor R1, the resistor R2, the resistor R3, the resistor R4, and the op Amp constitute a bandgap reference core circuit. The transistor M6, the transistor Q7, the resistor R5, and the resistor R6 constitute a compensation circuit. The transistors M1, M2, and M5 are PMOS transistors. The transistor Q3, the transistor Q4, and the transistor Q7 are NPN bipolar transistors.
The current flowing through the transistor M5 (i.e., the current flowing through the transistor M1 or M2) is the core current Icore. The core current Icore flows through the resistor R4, thereby generating the reference voltage Vref at the first end of the resistor R4. Transistor M6 generates a mirrored current of the current flowing through transistor M1. The currents flowing through the resistor R5 and the resistor R6 can be made equal by setting the resistance values of the resistor R5 and the resistor R6 equal, which is represented by I in FIG. 1 NL And (3) representing. The transistors Q3, Q4 and Q7 are NPN bipolar transistors whose base emitter voltages have negative temperature coefficients. Since the two input terminals of the op Amp are virtually short, the voltages at the two input terminals are equal. Thus, the voltage across resistor R2 has a negative temperature coefficient. The current I flowing through the resistor R2 can be made by setting the parameters of the transistor Q3 and the transistor Q4 PATA Has a positive temperature coefficient. Current I flowing through resistor R2 PATA Equal to the current flowing through transistor Q3 and transistor Q4, respectively. Since the base emitter voltage of transistor Q4 has a negative temperature coefficient, the current flowing through resistor R3 has a negative temperature coefficient. Current I flowing through transistor Q4 PATA Contrary to the temperature coefficient of the current flowing through the resistor R3, so that the temperature coefficient of the current flowing through the transistor M1 or the transistor M2 is compared with the current I PATA Is smaller, and therefore, the current I flowing through the transistor Q7 CT The temperature coefficient of (c) is smaller.
According to the characteristics of the bipolar transistor, the smaller the temperature coefficient of the current flowing through the bipolar transistor, the larger the temperature change rate of the base emitter voltage of the bipolar transistor. Therefore, the temperature change rate of the base emitter voltage of the transistor Q7 is greater than that of the transistor Q4Temperature rate of change of base emitter voltage. That is, as the temperature increases, the base voltage of transistor Q7 drops faster than the base voltage of transistor Q4. Thus, the current I NL Has a positive temperature coefficient. Current I NL The flow direction of (2) is shown in figure 1. Referring to FIG. 2, it can be seen that in the case of a core current Icore having a negative temperature coefficient, the current I NL The purpose of curvature compensation can be achieved. The compensated core current Icorr is less variable with temperature T than the core current Icore before compensation and is therefore more stable.
However, the core current Icore of the bandgap reference circuit 100 may have a positive temperature coefficient due to differences in component materials and processes, etc. The bandgap reference circuit 100 shown in FIG. 1 can compensate only the core current Icore (reference voltage corresponding to negative temperature coefficient) that is negative temperature coefficient before compensation, if the core current Icore (reference voltage corresponding to positive temperature coefficient) is to be compensated, I needs to be calculated NL Become negative temperature coefficient or cause current I in FIG. 1 NL Is reversed. And cannot be achieved by changing the resistance values of the resistor R5 and the resistor R6, the structure shown in fig. 1 cannot compensate for the reference voltage of the positive temperature coefficient.
Embodiments of the present disclosure propose a bandgap reference circuit capable of compensating for a positive temperature coefficient reference voltage. Fig. 3 shows a schematic block diagram of a bandgap reference circuit 300 according to an embodiment of the disclosure. The bandgap reference circuit 300 includes: a bandgap reference core circuit 310, a current mirror circuit 320, a voltage control circuit 330, a current source circuit 340, a first shunt circuit 350, and a second shunt circuit 360.
The bandgap reference core circuit 310 is coupled to the current mirror circuit 320, the first shunt circuit 350 and the second shunt circuit 360. The bandgap reference core circuit 310 is configured to: the core current Icore is generated, and the reference voltage Vref is generated according to the core current Icore.
The current mirror circuit 320 is coupled to the bandgap reference core circuit 310. The current mirror circuit 320 is coupled to the voltage control circuit 330 and the second shunt circuit 360 via the first node N1. The current mirror circuit 320 is configured to: generating a mirror current I of a core current Icore CT And provides the mirror current I to the voltage control circuit 330 via the first node N1 CT 。
The voltage control circuit 330 is coupled to the current mirror circuit 320 and the second shunt circuit 360 via the first node N1. The voltage control circuit 330 is configured to: so that the voltage of the first node N1 has a negative temperature coefficient and is based on the mirror current I CT To control the temperature change rate of the voltage of the first node N1. In some embodiments of the present disclosure, the mirror current I CT Is close to 0. Mirror current I CT The lower the temperature coefficient of the voltage of the first node N1, the higher the temperature change rate.
The current source circuit 340 is coupled to the first shunt circuit 350 and the second shunt circuit 360 via the second node N2. The current source circuit 340 is configured to: generating a constant current I SUM And provides a constant current I to both the first shunt circuit 350 and the second shunt circuit 360 via the second node N2 SUM . Constant current I SUM The sum of the currents flowing through both the first shunt circuit 350 and the second shunt circuit 360 is defined.
The first shunt circuit 350 is configured to: according to the voltage and constant current I of the third node N3 SUM To generate a first split stream I NT1 . Wherein the third node N3 is a node having a negative temperature coefficient within the bandgap reference core circuit 310.
The second shunt circuit 360 is configured to: according to the voltage and constant current I of the first node N1 SUM To generate a second split stream I NT2 And provides a second shunt I to the bandgap reference core circuit 310 NT2 So that the core current Icore is reduced by the second shunt I NT2 Is of a size of (a) and (b). Wherein the temperature change rate of the voltage of the third node N3 is smaller than that of the first node N1, so that the second current is divided into NT2 Has a positive temperature coefficient.
Since the temperature change rate of the voltage of the third node N3 is smaller than that of the first node N1, the first shunt I NT1 Is less than the second partial flow I NT2 Is a temperature change rate of (a). At the first stageSplit stream I NT1 With a second split I NT2 Is defined as constant current I SUM In the case of (1) due to the first split stream I NT1 With a second split I NT2 Is changed in proportion to the size of the first split stream I as the temperature increases NT1 Descending and second split stream I NT2 Rising. Thus the second split stream I NT2 Has a positive temperature coefficient. By subtracting the second shunt I from the core current Icore NT2 The magnitude of (a) can be such that the core current Icore having a positive temperature coefficient (the reference voltage Vref corresponding to the positive temperature coefficient) has a compensation of the negative temperature coefficient term, thereby making the output of the bandgap reference circuit 300 more stable.
In some embodiments of the present disclosure, bandgap reference circuit 300 may also include a start-up circuit (not shown in fig. 3). The start-up circuit is coupled to the bandgap reference core circuit 310 for providing a start-up current to the bandgap reference core circuit 310 during a start-up phase. The start-up circuit may stop providing the start-up current after the bandgap reference circuit 300 enters a steady state of operation. Since the start-up circuit is a circuit normally provided in the bandgap reference circuit, further description is omitted in this disclosure.
Fig. 4 shows an exemplary circuit diagram of a bandgap reference circuit 400 according to an embodiment of the disclosure. The bandgap reference core circuit 410 includes: the first to fifth transistors M1 to M5, the first to fourth resistors R1 to R4, and the op Amp. The control electrode of the first transistor M1 is coupled to the control electrode of the second transistor M2 and the output terminal of the op Amp. The first pole of the first transistor M1 is coupled to the first voltage terminal V1. The second pole of the first transistor M1 is coupled to the first input terminal of the op Amp, the first terminal of the first resistor R1 and the first terminal of the second resistor R2. The first pole of the second transistor M2 is coupled to the first voltage terminal V1. The second diode of the second transistor M2 is coupled to the second input terminal of the op Amp, the first terminal of the third resistor R3, and the control pole and the second diode of the fourth transistor M4. The control electrode of the third transistor M3 is coupled to the second electrode of the third transistor M3 and the second end of the second resistor R2. The first pole of the third transistor M3 is coupled to the second voltage terminal V2. The first pole of the fourth transistor M4 is coupled to the second voltage terminal V2. The second terminal of the first resistor R1 is coupled to the second voltage terminal V2. The second terminal of the third resistor R3 is coupled to the second voltage terminal V2. The control electrode of the fifth transistor M5 is coupled to the control electrode of the first transistor M1. The first pole of the fifth transistor M5 is coupled to the first voltage terminal V1. The second pole of the fifth transistor M5 is coupled to the first terminal of the fourth resistor R4 and the output voltage terminal Vref. The second terminal of the fourth resistor R4 is coupled to the second voltage terminal V2. In some embodiments of the present disclosure, the third node N3 is any one of the inputs of the op Amp. In the example of fig. 4, the third node N3 is the inverting input of the op Amp. Those skilled in the art will appreciate that the third node N3 may also be the non-inverting input of the op-Amp.
The current mirror circuit 420 includes: and a sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the control electrode of the first transistor M1. The first pole of the sixth transistor M6 is coupled to the first voltage terminal V1. The second pole of the sixth transistor M6 is coupled to the first node N1.
The voltage control circuit 430 includes: and a seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the second electrode of the seventh transistor M7. The first pole of the seventh transistor M7 is coupled to the second voltage terminal V2.
The current source circuit 440 includes: eighth transistor M8. The gate of the eighth transistor M8 is coupled to the gate of the first transistor M1. The first pole of the eighth transistor M8 is coupled to the first voltage terminal V1. The second pole of the eighth transistor M8 is coupled to the second node N2. In the example of fig. 4, the current flowing through the eighth transistor M8 may be made smaller than the current flowing through the first transistor M1 by setting the ratio of the width-to-length ratio of the eighth transistor M8 to the width-to-length ratio of the first transistor M1. In an alternative embodiment illustrated in fig. 4, the control electrode of the eighth transistor M8 may also be coupled to the bias voltage terminal. The current flowing through the eighth transistor M8 may be made smaller than the current flowing through the first transistor M1 by setting the magnitude of the bias voltage from the bias voltage terminal. The current flowing through the eighth transistor M8 may be specifically set according to the magnitude of the current to be compensated. In some embodiments of the present disclosure, the current flowing through the eighth transistor M8 is less than one percent of the current flowing through the first transistor M1.
The first shunt INT1 circuit 450 includes: and a ninth transistor M9. The control electrode of the ninth transistor M9 is coupled to the third node N3. The first pole of the ninth transistor M9 is coupled to the second node N2. The second pole of the ninth transistor M9 is coupled to the first node N1.
The second tap INT2 circuit 460 includes: a tenth transistor M10 and an eleventh transistor M11. The control electrode of the tenth transistor M10 is coupled to the first node N1. The first pole of the tenth transistor M10 is coupled to the second node N2. A second diode of the tenth transistor M10 is coupled to the second input terminal of the op Amp. The gate of the eleventh transistor M11 is coupled to the first node N1. The first pole of the eleventh transistor M11 is coupled to the second node N2. The second pole of the eleventh transistor M11 is coupled to the first input terminal of the op Amp.
In the example of fig. 4, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8 to the eleventh transistor M11 are PMOS transistors. The third transistor Q3, the fourth transistor Q4, and the seventh transistor Q7 are NPN bipolar transistors. The first input of the op Amp is the non-inverting input of the op Amp. The second input of the op Amp is an inverting input of the op Amp. The resistance value of the first resistor R1 is equal to the resistance value of the third resistor R3. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 4 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 4.
In the example of fig. 4, the third transistor Q3, the fourth transistor Q4, and the seventh transistor Q7 are NPN bipolar transistors whose base emitter voltages have negative temperature coefficients. Since the two input terminals of the op-amp are virtually short, the voltages at the two input terminals are equal. Thus, the voltage across the second resistor R2 has a negative temperature coefficient. The current I flowing through the second resistor R2 can be made by setting the parameters of the third transistor Q3 and the fourth transistor Q4 PATA Has a positive temperature coefficient. Current I flowing through the second resistor R2 PATA Equal to the current flowing through the third transistor Q3 and the fourth transistor Q4, respectively. Due to the firstThe base emitter voltage of the four transistor Q4 has a negative temperature coefficient, and thus the current flowing through the third resistor R3 has a negative temperature coefficient. Current I flowing through the fourth transistor Q4 PATA Contrary to the temperature coefficient of the current flowing through the third resistor R3, so that the temperature coefficient of the current flowing through the first transistor M1 or the second transistor M2 is compared with the current I PATA The temperature coefficient of (a) is smaller, and thus, the current I flowing through the seventh transistor Q7 CT The temperature coefficient of (c) is smaller.
According to the characteristics of the bipolar transistor, the smaller the temperature coefficient of the current flowing through the bipolar transistor, the larger the temperature change rate of the base emitter voltage of the bipolar transistor. Therefore, the temperature change rate of the base emitter voltage (the voltage of the first node N1) of the seventh transistor Q7 is greater than the temperature change rate of the base emitter voltage (the voltage of the third node N3) of the fourth transistor Q4. Referring to FIG. 5, as the temperature T increases, the voltage V at the first node N1 N1 Drop to a voltage V lower than the voltage V of the third node N3 N3 Faster. Since the first node N1 is coupled to the gates of the tenth and eleventh transistors M10 and M11 and the third node N3 is coupled to the gate of the ninth transistor M9, a current I flows through the tenth and eleventh transistors M10 and M11 NT2 The rising change rate of (a) is greater than the current I flowing through the ninth transistor M9 NT1 Is a rate of change of the rise of (c). Due to current I NT2 And current I NT1 The sum is a constant current, current I NT2 And current I NT1 The change in the ratio of (2) results in a current I NT2 Rise and current I NT1 And (3) lowering. This results in a current I NT2 Has a positive temperature coefficient. From the voltage-current relationship of MOS transistor (temperature coefficient of current is the square of temperature coefficient of voltage), the current I is known NT2 Has a nonlinear positive temperature coefficient.
At passing current I NT2 Before compensation, the core current Icore of the bandgap reference circuit is equal to the current I flowing through the fourth transistor Q4 PATA And the sum of the currents flowing through the third resistor R3. After compensation, the core current Icore of the bandgap reference circuit is equal to the current I flowing through the fourth transistor Q4 PATA And flows through a third resistor R3The sum of the currents of (2) minus the current I NT2 . This corresponds to the core current Icore being reduced by the current I NT2 . That is, the change amount of the core current Icore is I shown in fig. 5 NT2 '. Referring to fig. 5, it can be seen that the compensated current Icorr (icorr=icore+i NT2 ') is more stable than the core current Icore before compensation.
The embodiment of the disclosure also provides a chip. The chip includes a bandgap reference circuit according to embodiments of the present disclosure. The chip is, for example, a power management type chip.
The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is for example a smart terminal device such as a tablet computer, a smart phone or the like.
In summary, the bandgap reference circuit according to the embodiments of the present disclosure can perform temperature compensation of high-order curvature on a reference voltage having a positive temperature coefficient, so that the reference voltage output by the bandgap reference circuit is more stable.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A bandgap reference circuit comprising: a band gap reference core circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first shunt circuit, and a second shunt circuit,
wherein the bandgap reference core circuit is configured to: generating a core current and generating a reference voltage according to the core current;
the current mirror circuit is configured to: generating a mirror current of a core current and providing the mirror current to the voltage control circuit via a first node;
the voltage control circuit is configured to: so that the voltage of the first node has a negative temperature coefficient, and controlling the temperature change rate of the voltage of the first node according to the mirror current;
the current source circuit is configured to: generating a constant current and providing the constant current to both the first shunt circuit and the second shunt circuit via a second node;
the first shunt circuit is configured to: generating a first shunt according to a voltage of a third node and the constant current, wherein the third node is a node with a negative temperature coefficient in the bandgap reference core circuit;
the second shunt circuit is configured to: generating a second shunt from the voltage of the first node and the constant current and providing the second shunt to the bandgap reference core circuit such that the core current is reduced in magnitude by the second shunt;
wherein the rate of change of temperature of the voltage of the third node is less than the rate of change of temperature of the voltage of the first node, such that the second shunt has a positive temperature coefficient.
2. The bandgap reference circuit of claim 1, wherein the bandgap reference core circuit comprises: first to fifth transistors, first to fourth resistors, and an operational amplifier,
the control electrode of the first transistor is coupled with the control electrode of the second transistor and the output end of the operational amplifier, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the first input end of the operational amplifier, the first end of the first resistor and the first end of the second resistor;
the first pole of the second transistor is coupled with the first voltage end, and the second pole of the second transistor is coupled with the second input end of the operational amplifier, the first end of the third resistor, the control pole of the fourth transistor and the second pole;
a control electrode of a third transistor is coupled to a second electrode of the third transistor and a second end of the second resistor, and a first electrode of the third transistor is coupled to a second voltage end;
a first pole of the fourth transistor is coupled to the second voltage terminal;
a second end of the first resistor is coupled to the second voltage end;
a second end of the third resistor is coupled to the second voltage end;
a control electrode of the fifth transistor is coupled to the control electrode of the first transistor, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal;
a second end of the fourth resistor is coupled to the second voltage end;
the third node is any one input end of the operational amplifier.
3. The bandgap reference circuit of claim 2, wherein the current mirror circuit comprises: a sixth transistor is provided, which is connected to the first transistor,
the control electrode of the sixth transistor is coupled to the control electrode of the first transistor, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the first node.
4. A bandgap reference circuit as claimed in any one of claims 1 to 3, wherein the voltage control circuit comprises: a seventh one of the transistors is provided with a third transistor,
the control electrode of the seventh transistor is coupled to the second electrode of the seventh transistor, and the first electrode of the seventh transistor is coupled to the second voltage terminal.
5. A bandgap reference circuit as claimed in any one of claims 2 to 3, wherein the current source circuit comprises: an eighth transistor is provided for the purpose of providing a second voltage,
the control electrode of the eighth transistor is coupled to the control electrode of the first transistor, the first electrode of the eighth transistor is coupled to the first voltage terminal, and the second electrode of the eighth transistor is coupled to the second node.
6. A bandgap reference circuit as claimed in any one of claims 1 to 3, wherein the first shunt circuit comprises: a ninth transistor is provided, which is connected to the first transistor,
the control electrode of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the first node.
7. A bandgap reference circuit as claimed in any one of claims 2 to 3, wherein the second shunt circuit comprises: a tenth transistor and an eleventh transistor,
the control electrode of the tenth transistor is coupled to the first node, the first electrode of the tenth transistor is coupled to the second node, and the second electrode of the tenth transistor is coupled to the second input end of the operational amplifier;
the control electrode of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the first input terminal of the op-amp.
8. A bandgap reference circuit comprising: first to eleventh transistors, first to fourth resistors, and an operational amplifier,
the control electrode of the first transistor is coupled with the control electrode of the second transistor and the output end of the operational amplifier, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the first input end of the operational amplifier, the first end of the first resistor and the first end of the second resistor;
the first pole of the second transistor is coupled with the first voltage end, and the second pole of the second transistor is coupled with the second input end of the operational amplifier, the first end of the third resistor, the control pole of the fourth transistor and the second pole;
a control electrode of a third transistor is coupled to a second electrode of the third transistor and a second end of the second resistor, and a first electrode of the third transistor is coupled to a second voltage end;
a first pole of the fourth transistor is coupled to the second voltage terminal;
a second end of the first resistor is coupled to the second voltage end;
a second end of the third resistor is coupled to the second voltage end;
a control electrode of a fifth transistor is coupled to the control electrode of the first transistor, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal;
a second end of the fourth resistor is coupled to the second voltage end;
a control electrode of a sixth transistor is coupled to the control electrode of the first transistor, a first electrode of the sixth transistor is coupled to the first voltage terminal, and a second electrode of the sixth transistor is coupled to the control electrode and the second electrode of the seventh transistor;
a first pole of the seventh transistor is coupled to the second voltage terminal;
a control electrode of an eighth transistor is coupled to the control electrode of the first transistor, a first electrode of the eighth transistor is coupled to the first voltage terminal, and a second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor, the first electrode of the tenth transistor, and the first electrode of the eleventh transistor;
a control electrode of the ninth transistor is coupled to any one input end of the operational amplifier, and a second electrode of the ninth transistor is coupled to the second electrode of the sixth transistor;
a control electrode of the tenth transistor is coupled to the control electrode of the eleventh transistor and the second electrode of the sixth transistor, and a second electrode of the tenth transistor is coupled to the second input terminal of the op-amp;
a second pole of the eleventh transistor is coupled to the first input of the op-amp.
9. A chip, comprising: a bandgap reference circuit as claimed in any of claims 1 to 8.
10. An electronic device, comprising: the chip of claim 9.
CN202211702446.XA 2022-12-28 2022-12-28 Band gap reference circuit, chip and electronic equipment Pending CN116069100A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211702446.XA CN116069100A (en) 2022-12-28 2022-12-28 Band gap reference circuit, chip and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211702446.XA CN116069100A (en) 2022-12-28 2022-12-28 Band gap reference circuit, chip and electronic equipment

Publications (1)

Publication Number Publication Date
CN116069100A true CN116069100A (en) 2023-05-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211702446.XA Pending CN116069100A (en) 2022-12-28 2022-12-28 Band gap reference circuit, chip and electronic equipment

Country Status (1)

Country Link
CN (1) CN116069100A (en)

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