CN116069100A - Band gap reference circuit, chip and electronic equipment - Google Patents

Abstract

Embodiments of the present disclosure provide a bandgap reference circuit, a chip, and an electronic device. The bandgap reference circuit comprises a bandgap reference core circuit, a current mirror circuit, a voltage control circuit, a current source circuit, and first and second shunt circuits. The bandgap reference core circuit generates a core current. The current mirror circuit generates a mirror current of the core current and provides the mirror current to the voltage control circuit via the first node. The voltage control circuit enables the voltage of the first node to have a negative temperature coefficient and controls the temperature change rate of the voltage of the first node according to the mirror current. The current source circuit generates a constant current. The first shunt circuit generates a first shunt according to the voltage and the constant current of the third node. The second shunt circuit generates a second shunt according to the voltage of the first node and the constant current and causes the core current to be reduced in magnitude of the second shunt. The temperature change rate of the voltage of the third node is smaller than the temperature change rate of the voltage of the first node so that the second shunt has a positive temperature coefficient.

Description

Band gap reference circuit, chip and electronic equipment

technical field

Embodiments of the present disclosure relate to the technical field of integrated circuits, in particular, to bandgap reference circuits, chips and electronic devices.

Background technique

Bandgap reference circuits are widely used in integrated circuits as reference sources that are insensitive to temperature changes. Inside the bandgap reference circuit, a voltage/current with a lower temperature coefficient can be realized by superimposing the voltage/current with a positive temperature coefficient and the voltage/current with a negative temperature coefficient. However, there is a voltage/current with a nonlinear temperature coefficient inside the existing bandgap reference circuit. In order to achieve a voltage/current with a lower temperature coefficient, in addition to compensating for the linear temperature coefficient term, temperature compensation for high-order curvature is also required.

Contents of the invention

Embodiments described herein provide a bandgap reference circuit, chip and electronic device.

According to a first aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: a bandgap reference core circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first shunt circuit, and a second shunt circuit. Wherein, the bandgap reference core circuit is configured to: generate a core current, and generate a reference voltage according to the core current. The current mirror circuit is configured to: generate a mirror current of the core current, and provide the mirror current to the voltage control circuit via the first node. The voltage control circuit is configured to make the voltage of the first node have a negative temperature coefficient, and to control the temperature change rate of the voltage of the first node according to the mirror current. The current source circuit is configured to generate a constant current and provide the constant current to both the first shunt circuit and the second shunt circuit in common via the second node. The first shunt circuit is configured to generate a first shunt according to the voltage of the third node and the constant current. Wherein, the third node is a node with a negative temperature coefficient in the bandgap reference core circuit. The second shunt circuit is configured to: generate a second shunt according to the voltage of the first node and the constant current, and provide the second shunt to the bandgap reference core circuit so that the core current is reduced by the magnitude of the second shunt. Wherein, the temperature change rate of the voltage at the third node is smaller than the temperature change rate of the voltage at the first node, so that the second shunt has a positive temperature coefficient.

In some embodiments of the present disclosure, the bandgap reference core circuit includes: first to fifth transistors, first to fourth resistors, and an operational amplifier. Wherein, the control electrode of the first transistor is coupled to the control electrode of the second transistor and the output terminal of the operational amplifier. The first pole of the first transistor is coupled to the first voltage end. The second pole of the first transistor is coupled to the first input terminal of the operational amplifier, the first terminal of the first resistor and the first terminal of the second resistor. The first pole of the second transistor is coupled to the first voltage end. The second pole of the second transistor is coupled to the second input terminal of the operational amplifier, the first terminal of the third resistor, and the control pole and the second pole of the fourth transistor. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second terminal of the second resistor. The first pole of the third transistor is coupled to the second voltage end. The first pole of the fourth transistor is coupled to the second voltage end. The second end of the first resistor is coupled to the second voltage end. The second end of the third resistor is coupled to the second voltage end. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first pole of the fifth transistor is coupled to the first voltage end. The second pole of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal. The second end of the fourth resistor is coupled to the second voltage end. Wherein, the third node is any input terminal of the operational amplifier.

In some embodiments of the present disclosure, the current mirror circuit includes: a sixth transistor. Wherein, the control electrode of the sixth transistor is coupled to the control electrode of the first transistor. The first pole of the sixth transistor is coupled to the first voltage terminal. The second pole of the sixth transistor is coupled to the first node.

In some embodiments of the present disclosure, the voltage control circuit includes: a seventh transistor. Wherein, the control electrode of the seventh transistor is coupled to the second electrode of the seventh transistor. The first pole of the seventh transistor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the current source circuit includes: an eighth transistor. Wherein, the control electrode of the eighth transistor is coupled to the control electrode of the first transistor. The first pole of the eighth transistor is coupled to the first voltage terminal. The second pole of the eighth transistor is coupled to the second node.

In some embodiments of the present disclosure, the first shunt circuit includes: a ninth transistor. Wherein, the control electrode of the ninth transistor is coupled to the third node. The first pole of the ninth transistor is coupled to the second node.

The second pole of the ninth transistor is coupled to the first node.

In some embodiments of the present disclosure, the second shunt circuit includes: a tenth transistor and an eleventh transistor. Wherein, the control electrode of the tenth transistor is coupled to the first node. The first pole of the tenth transistor is coupled to the second node. The second pole of the tenth transistor is coupled to the second input end of the operational amplifier. The control electrode of the eleventh transistor is coupled to the first node. The first pole of the eleventh transistor is coupled to the second node. The second pole of the eleventh transistor is coupled to the first input terminal of the operational amplifier.

According to a second aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: first to eleventh transistors, first to fourth resistors, and an operational amplifier. Wherein, the control electrode of the first transistor is coupled to the control electrode of the second transistor and the output terminal of the operational amplifier. The first pole of the first transistor is coupled to the first voltage end. The second pole of the first transistor is coupled to the first input terminal of the operational amplifier, the first terminal of the first resistor and the first terminal of the second resistor. The first pole of the second transistor is coupled to the first voltage terminal. The second pole of the second transistor is coupled to the second input terminal of the operational amplifier, the first terminal of the third resistor, and the control pole and the second pole of the fourth transistor. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second terminal of the second resistor. The first pole of the third transistor is coupled to the second voltage terminal. The first pole of the fourth transistor is coupled to the second voltage terminal. The second end of the first resistor is coupled to the second voltage end. The second end of the third resistor is coupled to the second voltage end. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first pole of the fifth transistor is coupled to the first voltage end. The second pole of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal. The second end of the fourth resistor is coupled to the second voltage end. The control electrode of the sixth transistor is coupled to the control electrode of the first transistor. The first pole of the sixth transistor is coupled to the first voltage end. The second pole of the sixth transistor is coupled to the control pole and the second pole of the seventh transistor. The first pole of the seventh transistor is coupled to the second voltage end. The control electrode of the eighth transistor is coupled to the control electrode of the first transistor. The first pole of the eighth transistor is coupled to the first voltage end. The second pole of the eighth transistor is coupled to the first pole of the ninth transistor, the first pole of the tenth transistor and the first pole of the eleventh transistor. The control electrode of the ninth transistor is coupled to any input terminal of the operational amplifier. The second pole of the ninth transistor is coupled to the second pole of the sixth transistor. The control electrode of the tenth transistor is coupled to the control electrode of the eleventh transistor and the second electrode of the sixth transistor. The second pole of the tenth transistor is coupled to the second input end of the operational amplifier. The second pole of the eleventh transistor is coupled to the first input end of the operational amplifier.

According to a third aspect of the present disclosure, a chip is provided. The chip includes the bandgap reference circuit according to the first aspect or the second aspect of the present disclosure.

According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device includes the chip according to the third aspect of the present disclosure.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be known that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure. in:

Fig. 1 is an exemplary circuit diagram of a bandgap reference circuit;

FIG. 2 is a waveform diagram of some signals used in the bandgap reference circuit shown in FIG. 1;

3 is a schematic block diagram of a bandgap reference circuit according to an embodiment of the present disclosure;

4 is an exemplary circuit diagram of a bandgap reference circuit according to an embodiment of the present disclosure; and

FIG. 5 is a waveform diagram of some signals used in the bandgap reference circuit shown in FIG. 4 .

In the drawings, symbols with the same last two digits correspond to the same elements. It should be noted that elements in the drawings are schematic and not drawn to scale.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts also fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and related technologies, and will not be interpreted in an idealized or overly formal manner, Unless otherwise expressly defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

In all the embodiments of the present disclosure, since the source and the drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current direction between the source and the drain of the N-type transistor and the P-type transistor is opposite , therefore, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is called the control pole, and the remaining two ends of the MOS transistor are respectively called the first pole and the second pole. In addition, for the convenience of unified expression, in the context, the base of the bipolar transistor (BJT) is called the control electrode, the emitter of the BJT is called the first electrode, and the collector of the BJT is called the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one element (or a part of a element) from another element (or another part of a element).

FIG. 1 shows an exemplary circuit diagram of a bandgap reference circuit 100 . In the example of FIG. 1 , transistor M1 , transistor M2 , transistor Q3 , transistor Q4 , transistor M5 , resistor R1 , resistor R2 , resistor R3 , resistor R4 , and operational amplifier Amp constitute the bandgap reference core circuit. Transistor M6, transistor Q7, resistor R5 and resistor R6 form a compensation circuit. Wherein, the transistor M1, the transistor M2 and the transistor M5 are PMOS transistors. Transistor Q3, transistor Q4 and transistor Q7 are NPN bipolar transistors.

The current flowing through the transistor M5 (ie, the current flowing through the transistor M1 or M2 ) is the core current Icore. The core current Icore flows through the resistor R4, thereby generating the reference voltage Vref at the first end of the resistor R4. Transistor M6 generates a current mirror of the current flowing through transistor M1. The currents flowing through the resistors R5 and R6 can be made equal by setting the resistance values of the resistors R5 and R6 equal, indicated by _INL in FIG. 1 . Transistor Q3, transistor Q4, and transistor Q7 are NPN bipolar transistors whose base-emitter voltages have negative temperature coefficients. Since the two input terminals of the operational amplifier Amp are virtual short, the voltages at the two input terminals are equal. Therefore, the voltage across resistor R2 has a negative temperature coefficient. By setting the parameters of the transistor Q3 and the transistor Q4, the current I _PATA flowing through the resistor R2 can have a positive temperature coefficient. The current I _PATA flowing through resistor R2 is equal to the current flowing through transistor Q3 and transistor Q4 respectively. Since the base-emitter voltage of transistor Q4 has a negative temperature coefficient, the current flowing through resistor R3 has a negative temperature coefficient. The temperature coefficient of the current I _PATA flowing through transistor Q4 is opposite to that of the current flowing through resistor R3, so that the temperature coefficient of the current flowing through transistor M1 or transistor M2 is smaller than the temperature coefficient of current I _PATA , so that the current flowing The temperature coefficient of current I _CT through transistor Q7 is smaller.

According to the characteristics of the bipolar transistor, the smaller the temperature coefficient of the current flowing through the bipolar transistor is, the larger the temperature change rate of the base-emitter voltage of the bipolar transistor is. Therefore, the temperature change rate of the base-emitter voltage of transistor Q7 is greater than the temperature change rate of the base-emitter voltage of transistor Q4. That is, as the temperature increases, the base voltage of transistor Q7 drops faster than the base voltage of transistor Q4. Therefore, current _INL has a positive temperature coefficient. The flow direction of the current _INL is shown in FIG. 1 . Referring to FIG. 2 , it can be seen that in the case that the core current Icore has a negative temperature coefficient, the current I _NL can achieve the purpose of curvature compensation. Compared with the core current Icore before compensation, the core current Icorr after compensation changes less with the temperature T, so it is more stable.

However, the core current Icore of the bandgap reference circuit 100 may have a positive temperature coefficient due to differences in materials and processes of components. The bandgap reference circuit 100 shown in FIG. 1 can only compensate the core current Icore (corresponding to the reference voltage of the negative temperature coefficient) that is negative temperature coefficient before compensation. If the core current Icore (corresponding to the The reference voltage) to compensate, it is necessary to change _INL to a negative temperature coefficient or to reverse the flow of current _INL in Figure 1. However, it cannot be realized by changing the resistance values of the resistors R5 and R6, so the structure shown in FIG. 1 cannot compensate the reference voltage with a positive temperature coefficient.

Embodiments of the present disclosure propose a bandgap reference circuit capable of compensating a reference voltage with a positive temperature coefficient. FIG. 3 shows a schematic block diagram of a bandgap reference circuit 300 according to an embodiment of the disclosure. The bandgap reference circuit 300 includes: a bandgap reference core circuit 310 , a current mirror circuit 320 , a voltage control circuit 330 , a current source circuit 340 , a first shunt circuit 350 , and a second shunt circuit 360 .

The bandgap reference core circuit 310 is coupled to the current mirror circuit 320 , the first shunt circuit 350 and the second shunt circuit 360 . The bandgap reference core circuit 310 is configured to: generate a core current Icore, and generate a reference voltage Vref according to the core current Icore.

The current mirror circuit 320 is coupled to the bandgap reference core circuit 310 . The current mirror circuit 320 is coupled to the voltage control circuit 330 and the second shunt circuit 360 via the first node N1. The current mirror circuit 320 is configured to: generate a mirror current I _CT of the core current Icore, and provide the mirror current I _CT to the voltage control circuit 330 via the first node N1.

The voltage control circuit 330 is coupled to the current mirror circuit 320 and the second shunt circuit 360 via the first node N1. The voltage control circuit 330 is configured to make the voltage of the first node N1 have a negative temperature coefficient and control the temperature change rate of the voltage of the first node N1 according to the mirror current I _CT . In some embodiments of the present disclosure, the temperature coefficient of the mirror current I _CT is close to zero. The lower the temperature coefficient of the mirror current I _CT is, the higher the temperature change rate of the voltage of the first node N1 is.

The current source circuit 340 is coupled to the first shunt circuit 350 and the second shunt circuit 360 via the second node N2. The current source circuit 340 is configured to: generate a constant current I _SUM , and provide the constant current I _SUM to both the first shunt circuit 350 and the second shunt circuit 360 via the second node N2 . The constant current I _SUM defines the sum of currents flowing through both the first shunt circuit 350 and the second shunt circuit 360 .

The first shunt circuit 350 is configured to generate the first shunt _INT1 according to the voltage of the third node N3 and the constant current I _SUM . Wherein, the third node N3 is a node with a negative temperature coefficient in the bandgap reference core circuit 310 .

The second shunt circuit 360 is configured to: generate a second shunt _INT2 according to the voltage of the first node N1 and the constant current I _SUM , and provide the second shunt _INT2 to the bandgap reference core circuit 310 so that the core current Icore is reduced small size of the second shunt in _nt2 . Wherein, the temperature change rate of the voltage of the third node N3 is smaller than the temperature change rate of the voltage of the first node N1, so that the second shunt _INT2 has a positive temperature coefficient.

Since the temperature change rate of the voltage of the third node N3 is smaller than the temperature change rate of the voltage of the first node N1, the temperature change rate of the first branch _INT1 is smaller than the temperature change rate of the second branch _INT2 . In the case that the sum of the first shunt _INT1 and the second shunt _INT2 is limited to a constant current I _SUM , due to the change of the size ratio of the first shunt _INT1 and the second shunt _INT2 , as the temperature rises, the second shunt One shunt _INT1 falls and the second shunt _INT2 rises. Thus the second substream _INT2 has a positive temperature coefficient. By subtracting the size of the second shunt _INT2 from the core current Icore, the core current Icore (corresponding to the reference voltage Vref with a positive temperature coefficient) with a positive temperature coefficient can be compensated with a negative temperature coefficient term, so that the bandgap reference circuit The output of the 300 is more stable.

In some embodiments of the present disclosure, the bandgap reference circuit 300 may further include a startup circuit (not shown in FIG. 3 ). The start-up circuit is coupled to the bandgap reference core circuit 310 for providing a start-up current to the bandgap reference core circuit 310 during the start-up phase. The start-up circuit can stop providing the start-up current after the bandgap reference circuit 300 enters a stable working state. Since the start-up circuit is often provided in the bandgap reference circuit, it will not be further described in this disclosure.

FIG. 4 shows an exemplary circuit diagram of a bandgap reference circuit 400 according to an embodiment of the disclosure. The bandgap reference core circuit 410 includes: a first transistor M1 to a fifth transistor M5 , a first resistor R1 to a fourth resistor R4 , and an operational amplifier Amp. Wherein, the control electrode of the first transistor M1 is coupled to the control electrode of the second transistor M2 and the output terminal of the operational amplifier Amp. A first pole of the first transistor M1 is coupled to the first voltage terminal V1. The second pole of the first transistor M1 is coupled to the first input terminal of the operational amplifier Amp, the first terminal of the first resistor R1 and the first terminal of the second resistor R2. A first pole of the second transistor M2 is coupled to the first voltage terminal V1. The second terminal of the second transistor M2 is coupled to the second input terminal of the operational amplifier Amp, the first terminal of the third resistor R3 and the control terminal and the second terminal of the fourth transistor M4. The control electrode of the third transistor M3 is coupled to the second electrode of the third transistor M3 and the second terminal of the second resistor R2. A first electrode of the third transistor M3 is coupled to the second voltage terminal V2. A first pole of the fourth transistor M4 is coupled to the second voltage terminal V2. A second terminal of the first resistor R1 is coupled to the second voltage terminal V2. A second terminal of the third resistor R3 is coupled to the second voltage terminal V2. The control electrode of the fifth transistor M5 is coupled to the control electrode of the first transistor M1. A first pole of the fifth transistor M5 is coupled to the first voltage terminal V1. The second pole of the fifth transistor M5 is coupled to the first terminal of the fourth resistor R4 and the output voltage terminal Vref. A second terminal of the fourth resistor R4 is coupled to the second voltage terminal V2. In some embodiments of the present disclosure, the third node N3 is any input terminal of the operational amplifier Amp. In the example of FIG. 4 , the third node N3 is the inverting input terminal of the operational amplifier Amp. However, those skilled in the art should understand that the third node N3 may also be the non-inverting input terminal of the operational amplifier Amp.

The current mirror circuit 420 includes: a sixth transistor M6. Wherein, the control electrode of the sixth transistor M6 is coupled to the control electrode of the first transistor M1. A first pole of the sixth transistor M6 is coupled to the first voltage terminal V1. The second pole of the sixth transistor M6 is coupled to the first node N1.

The voltage control circuit 430 includes: a seventh transistor M7. Wherein, the control electrode of the seventh transistor M7 is coupled to the second electrode of the seventh transistor M7. A first electrode of the seventh transistor M7 is coupled to the second voltage terminal V2.

The current source circuit 440 includes: an eighth transistor M8. Wherein, the control electrode of the eighth transistor M8 is coupled to the control electrode of the first transistor M1. A first pole of the eighth transistor M8 is coupled to the first voltage terminal V1. The second pole of the eighth transistor M8 is coupled to the second node N2. In the example of FIG. 4 , the current flowing through the eighth transistor M8 is smaller than the current flowing through the first transistor M1 by setting the ratio of the aspect ratio of the eighth transistor M8 to the aspect ratio of the first transistor M1 . In an alternative embodiment illustrated in FIG. 4 , the control electrode of the eighth transistor M8 may also be coupled to the bias voltage terminal. The current flowing through the eighth transistor M8 can be made smaller than the current flowing through the first transistor M1 by setting the magnitude of the bias voltage from the bias voltage terminal. The current flowing through the eighth transistor M8 can be specifically set according to the magnitude of the current to be compensated. In some embodiments of the present disclosure, the current flowing through the eighth transistor M8 is less than one percent of the current flowing through the first transistor M1 .

The first shunt INT1 circuit 450 includes: a ninth transistor M9. Wherein, the control electrode of the ninth transistor M9 is coupled to the third node N3. A first pole of the ninth transistor M9 is coupled to the second node N2. The second pole of the ninth transistor M9 is coupled to the first node N1.

The second shunt INT2 circuit 460 includes: a tenth transistor M10 and an eleventh transistor M11. Wherein, the control electrode of the tenth transistor M10 is coupled to the first node N1. A first pole of the tenth transistor M10 is coupled to the second node N2. The second pole of the tenth transistor M10 is coupled to the second input end of the operational amplifier Amp. The control electrode of the eleventh transistor M11 is coupled to the first node N1. A first pole of the eleventh transistor M11 is coupled to the second node N2. The second pole of the eleventh transistor M11 is coupled to the first input end of the operational amplifier Amp.

In the example of FIG. 4, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8 to the eleventh transistor M11 are PMOS transistors. The third transistor Q3, the fourth transistor Q4 and the seventh transistor Q7 are NPN bipolar transistors. The first input terminal of the operational amplifier Amp is the non-inverting input terminal of the operational amplifier Amp. The second input terminal of the operational amplifier Amp is the inverting input terminal of the operational amplifier Amp. The resistance value of the first resistor R1 is equal to the resistance value of the third resistor R3. Those skilled in the art should understand that modifications to the circuit shown in FIG. 4 based on the above inventive concepts should also fall within the protection scope of the present disclosure. In this variant, the aforementioned transistors and voltage terminals may also have a different arrangement than the example shown in FIG. 4 .

In the example of FIG. 4 , the third transistor Q3 , the fourth transistor Q4 and the seventh transistor Q7 are NPN bipolar transistors, and their base-emitter voltages have negative temperature coefficients. Since the two inputs of the op amp are virtual shorted, the voltages at the two inputs are equal. Therefore, the voltage across the second resistor R2 has a negative temperature coefficient. By setting the parameters of the third transistor Q3 and the fourth transistor Q4, the current I _PATA flowing through the second resistor R2 can have a positive temperature coefficient. The current I _PATA flowing through the second resistor R2 is equal to the current flowing through the third transistor Q3 and the fourth transistor Q4 respectively. Since the base-emitter voltage of the fourth transistor Q4 has a negative temperature coefficient, the current flowing through the third resistor R3 has a negative temperature coefficient. The temperature coefficient of the current I _PATA flowing through the fourth transistor Q4 is opposite to that of the current flowing through the third resistor R3, so that the temperature coefficient of the current flowing through the first transistor M1 or the second transistor M2 is compared to that of the current I _PATA The temperature coefficient is smaller, and therefore, the temperature coefficient of the current I _CT flowing through the seventh transistor Q7 is smaller.

According to the characteristics of the bipolar transistor, the smaller the temperature coefficient of the current flowing through the bipolar transistor is, the larger the temperature change rate of the base-emitter voltage of the bipolar transistor is. Therefore, the temperature change rate of the base-emitter voltage (the voltage of the first node N1 ) of the seventh transistor Q7 is larger than the temperature change rate of the base-emitter voltage (the voltage of the third node N3 ) of the fourth transistor Q4 . Referring to FIG. 5 , it can be seen that as the temperature T increases, the voltage V _N1 of the first node N1 drops faster than the voltage V _N3 of the third node N3 . Since the first node N1 is coupled to the gates of the tenth transistor M10 and the eleventh transistor M11, and the third node N3 is coupled to the gates of the ninth transistor M9, therefore, the power flowing through the tenth transistor M10 and the eleventh transistor M11 The rising and changing rate of the current _INT2 is greater than the rising and changing rate of the current _INT1 flowing through the ninth transistor M9. Since the sum of current _INT2 and current _INT1 is a constant current, a change in the ratio of current _INT2 to current _INT1 causes current _INT2 to increase and current _INT1 to decrease. This makes the current _INT2 have a positive temperature coefficient. According to the voltage-current relationship of the MOS transistor (the temperature coefficient of the current is the square of the temperature coefficient of the voltage), it can be seen that the current I _NT2 has a non-linear positive temperature coefficient.

Before being compensated by the current _INT2 , the core current Icore of the bandgap reference circuit is equal to the sum of the current I _PATA flowing through the fourth transistor Q4 and the current flowing through the third resistor R3. After compensation, the core current Icore of the bandgap reference circuit is equal to the sum of the current I _PATA flowing through the fourth transistor Q4 and the current flowing through the third resistor R3 minus the current _INT2 . This is equivalent to the core current Icore being reduced by the current I _NT2 . That is, the change amount of the core current Icore is _INT2 ' shown in FIG. 5 . Referring to FIG. 5 , it can be seen that the current Icorr after compensation (Icorr=Icore+ _INT2 ′) is more stable than the core current Icore before compensation.

The embodiment of the present disclosure also provides a chip. The chip includes a bandgap reference circuit according to an embodiment of the present disclosure. The chip is, for example, a power management chip.

The embodiment of the present disclosure also provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, an intelligent terminal device, such as a tablet computer, a smart phone, and the like.

In summary, the bandgap reference circuit according to the embodiments of the present disclosure can perform high-order curvature temperature compensation on the reference voltage with a positive temperature coefficient, so that the reference voltage output by the bandgap reference circuit is more stable.

Unless the context clearly dictates otherwise, as used herein and in the appended claims, the singular includes the plural and vice versa. Thus, when referring to the singular, the plural of the corresponding term will generally be included. Similarly, the words "comprise" and "include" are to be interpreted as being inclusive and not exclusive. Likewise, the terms "include" and "or" should be construed as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, said "example" is exemplary and explanatory only, and should not be considered to be exclusive or inclusive .

Further aspects and ranges of adaptations will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the application.

Several embodiments of the present disclosure have been described in detail above, but obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A bandgap reference circuit comprising: a band gap reference core circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first shunt circuit, and a second shunt circuit,

wherein the bandgap reference core circuit is configured to: generating a core current and generating a reference voltage according to the core current;

the current mirror circuit is configured to: generating a mirror current of a core current and providing the mirror current to the voltage control circuit via a first node;

the voltage control circuit is configured to: so that the voltage of the first node has a negative temperature coefficient, and controlling the temperature change rate of the voltage of the first node according to the mirror current;

the current source circuit is configured to: generating a constant current and providing the constant current to both the first shunt circuit and the second shunt circuit via a second node;

the first shunt circuit is configured to: generating a first shunt according to a voltage of a third node and the constant current, wherein the third node is a node with a negative temperature coefficient in the bandgap reference core circuit;

the second shunt circuit is configured to: generating a second shunt from the voltage of the first node and the constant current and providing the second shunt to the bandgap reference core circuit such that the core current is reduced in magnitude by the second shunt;

wherein the rate of change of temperature of the voltage of the third node is less than the rate of change of temperature of the voltage of the first node, such that the second shunt has a positive temperature coefficient.

2. The bandgap reference circuit of claim 1, wherein the bandgap reference core circuit comprises: first to fifth transistors, first to fourth resistors, and an operational amplifier,

the control electrode of the first transistor is coupled with the control electrode of the second transistor and the output end of the operational amplifier, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the first input end of the operational amplifier, the first end of the first resistor and the first end of the second resistor;

the first pole of the second transistor is coupled with the first voltage end, and the second pole of the second transistor is coupled with the second input end of the operational amplifier, the first end of the third resistor, the control pole of the fourth transistor and the second pole;

a control electrode of a third transistor is coupled to a second electrode of the third transistor and a second end of the second resistor, and a first electrode of the third transistor is coupled to a second voltage end;

a first pole of the fourth transistor is coupled to the second voltage terminal;

a second end of the first resistor is coupled to the second voltage end;

a second end of the third resistor is coupled to the second voltage end;

a control electrode of the fifth transistor is coupled to the control electrode of the first transistor, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal;

a second end of the fourth resistor is coupled to the second voltage end;

the third node is any one input end of the operational amplifier.

3. The bandgap reference circuit of claim 2, wherein the current mirror circuit comprises: a sixth transistor is provided, which is connected to the first transistor,

the control electrode of the sixth transistor is coupled to the control electrode of the first transistor, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the first node.

4. A bandgap reference circuit as claimed in any one of claims 1 to 3, wherein the voltage control circuit comprises: a seventh one of the transistors is provided with a third transistor,

the control electrode of the seventh transistor is coupled to the second electrode of the seventh transistor, and the first electrode of the seventh transistor is coupled to the second voltage terminal.

5. A bandgap reference circuit as claimed in any one of claims 2 to 3, wherein the current source circuit comprises: an eighth transistor is provided for the purpose of providing a second voltage,

the control electrode of the eighth transistor is coupled to the control electrode of the first transistor, the first electrode of the eighth transistor is coupled to the first voltage terminal, and the second electrode of the eighth transistor is coupled to the second node.

6. A bandgap reference circuit as claimed in any one of claims 1 to 3, wherein the first shunt circuit comprises: a ninth transistor is provided, which is connected to the first transistor,

the control electrode of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the first node.

7. A bandgap reference circuit as claimed in any one of claims 2 to 3, wherein the second shunt circuit comprises: a tenth transistor and an eleventh transistor,

the control electrode of the tenth transistor is coupled to the first node, the first electrode of the tenth transistor is coupled to the second node, and the second electrode of the tenth transistor is coupled to the second input end of the operational amplifier;

the control electrode of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the first input terminal of the op-amp.

8. A bandgap reference circuit comprising: first to eleventh transistors, first to fourth resistors, and an operational amplifier,

the control electrode of the first transistor is coupled with the control electrode of the second transistor and the output end of the operational amplifier, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the first input end of the operational amplifier, the first end of the first resistor and the first end of the second resistor;

the first pole of the second transistor is coupled with the first voltage end, and the second pole of the second transistor is coupled with the second input end of the operational amplifier, the first end of the third resistor, the control pole of the fourth transistor and the second pole;

a control electrode of a third transistor is coupled to a second electrode of the third transistor and a second end of the second resistor, and a first electrode of the third transistor is coupled to a second voltage end;

a first pole of the fourth transistor is coupled to the second voltage terminal;

a second end of the first resistor is coupled to the second voltage end;

a second end of the third resistor is coupled to the second voltage end;

a control electrode of a fifth transistor is coupled to the control electrode of the first transistor, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal;

a second end of the fourth resistor is coupled to the second voltage end;

a control electrode of a sixth transistor is coupled to the control electrode of the first transistor, a first electrode of the sixth transistor is coupled to the first voltage terminal, and a second electrode of the sixth transistor is coupled to the control electrode and the second electrode of the seventh transistor;

a first pole of the seventh transistor is coupled to the second voltage terminal;

a control electrode of an eighth transistor is coupled to the control electrode of the first transistor, a first electrode of the eighth transistor is coupled to the first voltage terminal, and a second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor, the first electrode of the tenth transistor, and the first electrode of the eleventh transistor;

a control electrode of the ninth transistor is coupled to any one input end of the operational amplifier, and a second electrode of the ninth transistor is coupled to the second electrode of the sixth transistor;

a control electrode of the tenth transistor is coupled to the control electrode of the eleventh transistor and the second electrode of the sixth transistor, and a second electrode of the tenth transistor is coupled to the second input terminal of the op-amp;

a second pole of the eleventh transistor is coupled to the first input of the op-amp.

9. A chip, comprising: a bandgap reference circuit as claimed in any of claims 1 to 8.

10. An electronic device, comprising: the chip of claim 9.

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