CN116057692A - 具有热隔离结构的半导体装置 - Google Patents

具有热隔离结构的半导体装置 Download PDF

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Publication number
CN116057692A
CN116057692A CN202180052419.XA CN202180052419A CN116057692A CN 116057692 A CN116057692 A CN 116057692A CN 202180052419 A CN202180052419 A CN 202180052419A CN 116057692 A CN116057692 A CN 116057692A
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Prior art keywords
thermal buffer
die assembly
substrate
semiconductor
active circuit
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CN202180052419.XA
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S·U·阿里芬
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本文中描述包含用于热管理的结构的半导体装置以及相关联系统及方法。在一些实施例中，半导体装置包含第一裸片组合件，所述第一裸片组合件包含半导体衬底及在所述半导体衬底的第一表面处的多个有源电路元件。所述装置还包含第二裸片组合件，所述第二裸片组合件包含载体衬底及在所述载体衬底的第一表面上或上方的重布结构。所述装置进一步包含在所述第一与所述第二裸片组合件之间的热缓冲器结构，所述热缓冲器结构耦合到所述半导体衬底的第二表面及所述载体衬底的第二表面。所述装置还包含多个互连件，所述多个互连件至少延伸穿过所述半导体衬底、所述载体衬底及所述热缓冲器结构以将所述有源电路元件电耦合到所述重布结构。

Description

具有热隔离结构的半导体装置
相关申请的交叉参考
本申请主张在2020年7月28日申请的第16/941,437号美国专利申请的权益，所述美国专利申请以其全文引用方式并入本文中。
技术领域
本技术大体上涉及半导体装置，且更特定来说涉及用于管理半导体装置中的热的技术。
背景技术
封装式半导体裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于衬底上且包封于保护罩中的半导体裸片。半导体裸片可包含功能特征(例如存储器单元、处理器电路及成像器装置)，以及电连接到功能特征的接合垫。接合垫可电连接到保护罩外部的端子以允许将半导体裸片连接到更高层级电路系统。
存储器装置广泛用于存储与各种电子装置(例如计算机、无线通信装置、相机、数字显示器及类似物)有关的信息。存储器装置常常提供为计算机或其它电子装置中的内部半导体集成电路及/或外部可移除装置。市场压力不断驱使半导体制造商发展出具有更快数据速率的高速存储器装置。然而，更快数据速率通常涉及通过装置内金属互连件的更高电流，此产生焦耳加热且提高装置内的温度。较高温度可不利地影响装置性能及可靠性，且还可增加制造期间的良率损失。
附图说明
参考以下图式可更好地理解本技术的许多方面。图式中的组件不一定按比例。代替地，将重点放在清楚地说明本技术的原理。
图1是半导体装置的侧视横截面视图。
图2A是根据本技术的实施例配置的具有热缓冲器结构的半导体装置的示意性侧视横截面视图。
图2B是根据本技术的实施例的在制造过程期间的图2A的装置的第一裸片组合件的示意性侧视横截面视图。
图2C是根据本技术的实施例的在制造过程期间的图2A的装置的第二裸片组合件的示意性侧视横截面视图。
图3A是根据本技术的实施例配置的具有热缓冲器结构的半导体装置的示意性侧视横截面视图。
图3B是根据本技术的实施例的在制造过程期间的图3A的装置的第一裸片组合件的示意性侧视横截面视图。
图3C是根据本技术的实施例的在制造过程期间的图3A的装置的第二裸片组合件的示意性侧视横截面视图。
图4A是根据本技术的实施例配置的具有热缓冲器结构的半导体装置的示意性侧视横截面视图。
图4B是根据本技术的实施例的在制造过程的阶段之后的图4A的装置的裸片组合件的示意性侧视横截面视图。
图4C是根据本技术的实施例的在制造过程的后续阶段之后的图4A的装置的示意性侧视横截面视图。
图5是根据本技术的实施例配置的半导体封装的示意性侧视横截面视图。
图6是根据本技术的实施例配置的半导体封装的示意性侧视横截面视图。
图7是根据本技术的实施例配置的半导体封装的示意性侧视横截面视图。
图8是根据本技术的实施例配置的半导体封装的示意性侧视横截面视图。
图9是根据本技术的实施例配置的半导体封装的示意性侧视横截面视图。
图10是包含根据本技术的实施例配置的半导体装置或封装的系统的示意图。
具体实施方式
下文描述半导体装置以及相关联系统及方法的数种实施例的具体细节。在一些实施例中，例如，根据本技术配置的半导体装置包含半导体衬底，所述半导体衬底包含第一(例如，前)表面及与第一表面相对的第二(例如，后)表面，以及在半导体衬底的第一表面处的多个有源电路元件(例如，晶体管)。装置还可包含重布结构，所述重布结构包含用于将信号路由到有源电路元件及从有源电路元件路由信号的多个导电组件(例如，金属层、迹线、通路等)。重布结构可通过耦合到半导体衬底的第二表面的热缓冲器结构与有源电路元件及半导体衬底分开。例如，重布结构可定位于附接到热缓冲器结构的载体衬底上或上方，或可定位于热缓冲器结构本身上或上方。为了允许跨装置的信号传输，有源电路元件可通过延伸穿过半导体衬底、热缓冲器结构及载体衬底(如果存在)的多个互连件(例如，通路、支柱、微凸块等)电耦合到重布结构。热缓冲器结构将重布结构与有源电路元件物理分开并热隔离，此可减少或防止将在重布结构中产生的热(例如，通过焦耳加热)传输到有源电路元件。因此，本技术可改进半导体装置的性能及可靠性，且还可降低装置制造及测试期间的良率损失。
在一些实施例中，本技术提供经改进存储器装置，其中使用热缓冲器结构来减少或防止温度敏感组件(例如，CMOS电路系统)的加热。根据本技术的实施例配置的存储器装置可包含易失性存储器装置(例如，静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(SDRAM)等)以及非易失性存储器(例如，快闪存储器(例如，NAND，NOR)、相变存储器(PCM)、铁电随机存取存储器(FeRAM)、电阻式随机存取存储器(RRAM)及磁性随机存取存储器(MRAM)等)。例如，本技术可包含其中CMOS电路及存储器阵列通过热缓冲器结构与重布结构分开，或其中CMOS电路系统通过热缓冲器结构与存储器阵列及重布结构两者分开的存储器装置(例如，NAND、DRAM、NOR等)。CMOS电路系统可包含例如高速及/或高功率装置，例如驱动器、感测放大器、数据锁存器、输入/输出装置及类似物。CMOS电路系统可排除例如存取晶体管、阵列电荷存储元件及类似物的存储器阵列装置。然而，在其它实施例中，本技术可在其它类型的存储器装置中或在其它类型的半导体装置(例如，逻辑装置、控制器装置等)中实施。
相关领域的技术人员将认识到，可在晶片级或裸片级执行本文中描述的方法的适合阶段。因此，取决于其所用于的上下文，术语“衬底”可指晶片级衬底或经单粒化裸片级衬底。此外，除非上下文另有指示，否则本文中公开的结构可使用常规半导体制造技术形成。可例如使用化学气相沉积、物理气相沉积、原子层沉积、镀覆、无电式镀覆、旋涂及/或其它适合技术来沉积材料。类似地，可例如使用等离子体蚀刻、湿式蚀刻、化学机械平坦化或其它适合技术来移除材料。
本文中公开许多具体细节以提供对本技术的实施例的透彻且可行的描述。然而，所属领域的技术人员将理解，本技术可具有额外实施例，且可在不具有下文关于图2A到10描述的实施例的数种细节的情况下实践本技术。例如，已省略所述领域中所众所周知的半导体装置及/或封装的一些细节，以免使本技术不清楚。一般来说，应理解，除本文中公开的特定实施例之外的各种其它装置及系统也可在本技术的范围内。
如本文中使用，鉴于图中展示的定向，术语“垂直”、“横向”、“上”、“下”、“上面”及“下面”可指半导体装置中的特征的相对方向或位置。例如，“上”或“最上”可指定位成比另一特征更靠近页面的顶部的特征。然而，这些术语应被广泛地解释为包含具有其它定向(例如倒转或倾斜定向)的半导体装置，其中顶部/底部、在……上方/在……下方、在……上面/在……下面、向上/向下及左/右可取决于定向而互换。
图1是半导体装置100的示意性侧视横截面视图。装置100包含具有第一表面104a及第二表面104b的半导体衬底102。多个有源电路元件106(例如，晶体管及/或其它前段制程(FEOL)元件)形成于第一表面104a上及/或中。装置100还包含例如存储器阵列的中间结构108(例如，中段(MOL)结构)、重布结构110(例如，后段制程(BEOL)结构)以及热及/或电绝缘材料112。在装置100的操作期间，例如，归因于重布结构110及/或中间结构108内的金属互连件的焦耳加热，在这些组件中产生热。在一些实施例中，重布结构110具有比中间结构108厚的金属互连件，且因此产生大多数的热。因为重布结构110及中间结构108紧密靠近有源电路元件106，所以在重布结构110及/或中间结构108中产生的热经由传导直接传输到有源电路元件106(例如，如由图1中的垂直箭头指示)。此提高有源电路元件106的操作温度，此可不利地影响性能。例如，在其中装置100是存储器裸片的实施例中，来自重布结构110及/或中间结构108的过高温度降低装置可靠性(例如，数据保持丢失)及/或性能(例如，降低的数据速率)，以及装置制造及测试期间的良率损失。
图2A是根据本技术的实施例配置的具有热缓冲器结构202的半导体装置200的示意性侧视横截面视图。装置200包含通过热缓冲器结构202彼此连接的第一裸片组合件204a及第二裸片组合件204b。如下文更详细地描述，热缓冲器结构202可将第一裸片组合件204a与第二裸片组合件204b热隔离。在一些实施例中，第一裸片组合件204a包含对高温敏感的一或多个第一组件(例如，CMOS电路系统及/或其它FEOL元件)，而第二裸片组合件204b包含在操作期间产生热的一或多个第二组件(例如，重布结构及/或其它BEOL元件)，或反之亦然。例如，第一组件可具有温度阈值(性能在所述温度阈值下受损)或(“第一组件阈值温度”)，且第二组件可具有高于所述阈值温度的操作温度(“第二组件操作温度”)。热缓冲器结构202可经配置以减少或抑制从第二裸片组合件204b到第一裸片组合件204a的热传递(或反之亦然)，以减轻温度敏感第一组件的加热。例如，从第二裸片组合件204b传递到第一裸片组合件204a的热量可不超过在第二裸片组合件204a中产生的总热量的90％、80％、70％、60％、50％、40％、30％、20％、10％或5％。
在一些实施例中，第二裸片组合件204b包含预期在装置的操作期间产生大量热的装置200的所有组件(例如，重布结构及/或其它BEOL元件)，而第一裸片组合件204a包含预期基本上受高操作温度损害的所有组件(例如，CMOS电路系统及/或其它FEOL元件)。因此，第一裸片组合件204a可缺少预期在操作期间显著提高装置200的温度的任何组件，而第二裸片组合件204b可缺少受高操作温度的不利影响的任何组件。在一些实施例中，在操作期间由装置200产生的总热量的至少50％、60％、70％、80％、90％、95％或99％来源于第二裸片组合件204b，而在操作期间由装置200产生的总热量的少于50％、40％、30％、20％、10％、5％或1％来源于第一裸片组合件204a。
第一裸片组合件204a的第一组件可包含装置200的有源半导体组件。如图2A中展示，第一裸片组合件204a包含半导体衬底206，半导体衬底206具有第一表面208a(例如，前或有源表面)及与第一表面208a相对的第二表面208b(例如，后表面)。第一裸片组合件204a的第一组件可为形成于第一表面208a上的有源电路元件210。例如，有源电路元件210可包含晶体管及/或其它FEOL元件(例如，CMOS电路系统)。在一些实施例中，有源电路元件210不包含任何MOL元件(例如，存储器阵列装置)或BEOL元件(例如，重布结构)。半导体衬底206可为用于半导体制造及处理的任何适合衬底，例如硅衬底、砷化镓衬底、有机层压衬底等。半导体衬底206的厚度可视需要变化，例如，在从5μm到700μm的范围内。
在一些实施例中，第一裸片组合件204a还包含耦合到有源电路元件210的中间结构212。中间结构212可包含多个MOL组件。例如，在其中装置200是存储器装置的实施例中，中间结构212可包含存储器组件，例如包含多个存储器单元或电路(例如，NAND、NOR、DRAM等)、字线、位线等的存储器阵列。中间结构212可能不包含任何FEOL元件(例如，CMOS电路系统)或BEOL元件(例如，重布结构)。然而，在其它实施例中，中间结构212是任选的且可省略。
第一裸片组合件204a可进一步包含路由结构214，路由结构214经配置以将信号从有源电路元件210及/或中间结构212(如果存在)路由到装置200的其它内部组件。路由结构214可耦合到中间结构212，或如果省略中间结构212，那么可直接耦合到有源电路元件210。路由结构214可包含导电组件，例如触点、线、迹线、布线、通路、互连件等。在一些实施例中，路由结构214是或包含单个金属层(例如，M1层)。替代地，在其中路由结构214包含多个金属层的实施例中，层的数目可相对较小(例如，不超过五层、四层、三层或两层)。然而，在其它实施例中，路由结构214是任选的且可完全省略。
第一绝缘材料216(例如，电绝缘材料)可耦合到路由结构214以保护路由结构214、中间结构212及有源电路元件210免受损坏(例如，在制造、封装及/或使用装置200期间)。第一绝缘材料216可为钝化材料，例如电介质材料、聚酰亚胺材料及/或用于覆盖半导体装置的表面的其它材料。
第一裸片组合件204a进一步包含从路由结构214延伸到半导体衬底206的第二表面208b的第一组通路或互连件218(“第一通路218”)。第一通路218可包含穿硅通路(TSV)及/或任何其它适合类型的导电互连件。如图2A中展示，第一通路218可延伸穿过半导体衬底206、有源电路元件210及中间结构212的整个厚度。第一通路218可用于在第一裸片组合件204a与第二裸片组合件204b之间传输信号，如下文进一步论述。
第二裸片组合件204b的第二组件可包含用于在第一裸片组合件204a与外部装置(例如，另一半导体装置及/或封装衬底；图2A中未展示)之间路由信号的金属化结构。第二裸片组合件204b可缺少任何FEOL元件或MOL元件。在所说明实施例中，第二裸片组合件204b包含载体衬底220(例如，硅、玻璃或陶瓷衬底或中介层)，载体衬底220具有第一表面222a(例如，前表面)及与第一表面222a相对的第二表面222b(例如，后表面)。在一些实施例中，载体衬底220不包含形成于第一表面222a或第二表面22b中的任何晶体管及/或其它有源电路元件。载体衬底220可具有任何适合厚度，例如在从5μm到700μm的范围内的厚度。在所说明实施例中，载体衬底220比半导体衬底206薄。例如，载体衬底220的厚度可为半导体衬底206的厚度的90％、80％、70％、60％、50％、40％、30％、20％或10％。然而，在其它实施例中，载体衬底220的厚度可大于或等于半导体衬底206的厚度。
重布结构224形成于载体衬底220的第一表面222a上及/或耦合到第一表面222a。重布结构224可为或包含重布层(RDL)(例如，其在晶片探针测试之后形成)或直列式重布层(iRDL)(例如，其在晶片探针测试之前形成)。在一些实施例中，重布结构242是包含用于路由信号的导电组件(例如触点、线、迹线、布线、通路、互连件等)的BEOL结构。重布结构224还可包含用于将装置200电耦合到外部装置(未展示)(例如另一半导体装置或封装衬底)的接合垫(未展示)，如下文进一步论述。
在一些实施例中，重布结构224包含多个金属层(例如，M2到M4层)。重布结构224可包含比第一裸片组合件204a的路由结构214多的金属层。例如，路由结构214可包含单个金属层，而重布结构224可包含多个金属层(例如，两层、三层、四层、五层或更多层)。重布结构224可比路由结构214厚(例如，重布结构224的厚度可为路由结构214的厚度的至少110％、120％、150％、200％、300％、400％或500％)。在一些实施例中，在装置200的操作期间，重布结构224产生比第一裸片组合件204a的路由结构214及/或中间结构212更多的热(例如，归因于焦耳加热)。例如，在操作期间由重布结构224产生的总热量可为由路由结构214及/或中间结构212产生的总热量的至少110％、120％、150％、200％、300％、400％或500％。
第二绝缘材料226(例如，电绝缘材料)可耦合到重布结构224。第二绝缘材料226可为钝化材料，例如电介质材料、聚酰亚胺材料及/或用于覆盖半导体装置的表面的其它材料。在一些实施例中，第二绝缘材料226包含形成于其中的孔隙(未展示)，以暴露重布结构224的接合垫用于耦合到外部电连接器(例如，线接合、微凸块、焊料凸块、支柱等)，如下文更详细地论述。
第二裸片组合件204b进一步包含从重布结构224延伸穿过载体衬底220的整个厚度而到第二表面222b的第二组通路或互连件228(“第二通路228”)。第二通路228可包含TSV及/或其它类型的导电互连件。第二通路228可用于在第二裸片组合件204b与第一裸片组合件204a之间路由信号，如下文进一步描述。
第一及第二裸片组合件204a到b通过热缓冲器结构202彼此连接。在所说明实施例中，热缓冲器结构202耦合到半导体衬底206的第二表面208b及载体衬底220的第二表面222b，使得第一及第二裸片组合件204a到b以“背靠背”配置布置，其中热缓冲器结构202在其之间。为了减少或防止第一与第二裸片组合件204a到b之间的热传递，热缓冲器结构202可具有小于半导体衬底206及/或载体衬底220的热导率的热导率。例如，热缓冲器结构202的热导率可不大于半导体衬底206及/或载体衬底220的热导率的90％、80％、70％、60％、50％、40％、30％、20％、10％、5％、1％、0.25％或0.1％。在一些实施例中，热缓冲器结构202的热导率小于或等于50W/mK、40W/mK、30W/mK、20W/mK、10W/mK、5W/mK、1W/mK、0.5W/mK或0.1W/mK。半导体衬底206及/或载体衬底220的热导率可大于或等于50W/mK、75W/mK、100W/mK、125W/mK或150W/mK。因此，在第一与第二裸片组合件204a到b之间的热缓冲器结构202的存在可将发热组件(例如，重布结构224)与温度敏感组件(例如，有源电路元件210)物理分开且热隔离。例如，在一些实施例中，装置200是存储器装置(例如，NAND、DRAM、NOR等)，有源电路元件210包含CMOS电路系统，且中间结构212包含存储器阵列。在此类实施例中，可通过将重布结构224与CMOS电路系统及存储器阵列分开而改进存储器装置的性能及可靠性。
热缓冲器结构202可界定分离区且具有许多不同配置。在一些实施例中，例如，热缓冲器结构202包含热绝缘材料230，例如热绝缘膜、薄片、基质、树脂、模制化合物、膏等。例如，热绝缘材料230可为非导电膜(NCF)、裸片附接膜(DAF)或底部填充材料。底部填充材料可为毛细管底部填充材料、非导电环氧树脂膏(例如，由日本新泻(Niigata)的纳美仕(Namics)公司制造的XS8448-171)、电介质底部填充材料(例如，如由德国杜塞尔多夫(Düsseldorf)的汉高(Henkel)制造的FP4585)及/或具有低热导率的其它适合材料。然而，在其它实施例中，可省略热绝缘材料230，且热缓冲器结构202可代替地包含在半导体衬底206与载体衬底220之间的气隙。热缓冲器结构202可具有任何适合厚度，例如在从1μm到50μm的范围内的厚度。
装置200可包含延伸穿过热缓冲器结构202的整个厚度以在第一与第二裸片组合件204a到b之间传输信号的多个互连件结构232。互连件结构232可将第一裸片组合件204a的第一通路218电耦合到第二裸片组合件204b的第二通路228。在一些实施例中，互连件结构232还将半导体衬底206机械地耦合到载体衬底220(例如，结合热绝缘材料230)。互连件结构232可包含凸块、微凸块、支柱、柱、椿等。每一互连件结构232可由任何适当导电材料形成，例如铜、镍、金、硅、钨、焊料(例如，基于SnAg的焊料)、导电环氧树脂、其组合等，且可通过电镀、无电式镀覆或另一适合工艺形成。任选地，互连件结构232还可包含形成于互连件结构232的端部上方的势垒材料(例如，镍、基于镍的金属间化合物及/或金)。势垒材料可促进接合及/或防止或至少抑制铜或用于形成互连件结构232的其它金属的电迁移。
例如，在所说明实施例中，每一互连件结构232包含在第一通路218的位置处耦合到半导体衬底206的第二表面208b的第一支柱元件234a(例如，第一铜支柱)、在第二通路228的位置处耦合到载体衬底220的第二表面222b的第二支柱元件234b(例如，第二铜支柱)，及电气地且机械地连接第一及第二支柱元件234a到b的焊料凸块236或其它导电连接器。然而，在其它实施例中，可使用其它类型的互连件结构及材料。
在装置200的操作期间，来自有源电路元件210的信号可通过中间结构212传输到路由结构214，路由结构214将信号路由到第一通路218。随后，信号可循序传输通过第一通路218、互连件结构232及第二通路228以到达重布结构224。重布结构224可将信号路由到外部装置(例如，另一半导体裸片或封装衬底；图2A中未展示)。相反地，来自外部装置的信号可传输到重布结构224，重布结构224将信号路由到第二通路228。接着，信号可循序传输通过第二通路228、互连件结构232及第一通路218而到路由结构214。路由结构214可将信号路由到中间结构212及有源电路元件210。
图2B是根据本技术的实施例的在制造过程期间的第一裸片组合件204a的示意性侧视横截面视图。制造过程可为晶片级或裸片级过程，且可涉及使用所属领域的技术人员已知的半导体制造技术循序地形成第一裸片组合件204a的个别层。例如，可在半导体衬底206的第一表面208a中及/或上形成有源电路元件210，且接着在有源电路元件上方形成中间结构212。一般来说，使用FEOL处理技术形成有源电路元件210及/或中间结构。接着，可形成穿过半导体衬底206、有源电路元件210及中间结构212的第一通路218。在一些实施例中，接着可在中间结构212上形成路由结构214且将其电连接到第一通路218。在其它实施例中，可在形成通路218之前在中间结构212上形成路由结构214。接着，将第一绝缘材料216施覆到路由结构214。
图2C是根据本技术的实施例的在制造过程期间的第二裸片组合件204b的示意性侧视横截面视图。第二裸片组合件204b的制造过程还可在晶片级或裸片级执行，且可涉及使用所属领域的技术人员已知的半导体制造技术循序地形成第二裸片组合件204b的个别层。例如，在一些实施例中，在载体衬底220中形成第二通路228，且接着在载体衬底220的第一表面222a上形成重布结构224且将其电耦合到第二通路228。在其它实施例中，在载体衬底220的第一表面222a上形成重布结构224，且接着形成穿过载体衬底220的第二通路228。重布结构224可使用BEOL处理技术形成。随后，可将第二绝缘材料226施覆到重布结构224。
再次参考图2A，为了组装装置200，经由热缓冲器结构202将第一及第二裸片组合件204a到b彼此机械且电耦合。在一些实施例中，在已将第一及第二支柱元件234a到b连接在一起之后，在第一与第二裸片组合件204a到b之间原位形成热缓冲器结构202，使得在形成热缓冲器结构202的过程期间将第一及第二裸片组合件204a到b彼此耦合且耦合到热缓冲器结构202。然而，在其它实施例中，热缓冲器结构202可为预成形组件，其在第一及第二支柱元件234a到b已连接在一起之前耦合到第一及第二裸片组合件204a到b中的至少一者。
热缓冲器结构202可以许多不同方式形成，例如使用所属领域的技术人员已知的裸片附接方法(例如，直接芯片附接、微凸块等)。在一些实施例中，例如，将第一支柱元件234a耦合到第一裸片组合件204a(例如，在半导体衬底206的第二表面208b处耦合到第一通路218)，且将第二支柱元件234b耦合到第二裸片组合件204b(例如，在载体衬底220的第二表面220b处耦合到第二通路228)。随后可经由焊料凸块236将第一及第二支柱元件234a到b彼此电气且机械耦合，以例如使用热压接合(TCB)或质量回流操作形成互连件结构232。为了形成热缓冲器结构202，可在TCB/质量回流操作之前及/或期间(例如，在其中热绝缘材料230是例如NCF或DAF的固体材料的实施例中)，或在TCB/质量回流操作之后(例如，在其中热绝缘材料230是例如毛细管底部填充材料的可流动材料的实施例中)，将热绝缘材料230定位于第一与第二裸片组合件204a到b之间。因此，可经由互连件结构232及热绝缘材料230将第一及第二裸片组合件204a到b彼此电气且机械连结。
图3A是根据本技术的实施例配置的包含热缓冲器结构202的半导体装置300的示意性侧视横截面视图。装置300可大体上类似于关于图2A到2C描述的装置200。因此，相同数字用于识别类似或相同组件，且对图3A的装置300的论述将限于不同于装置200的那些特征。
装置300包含通过热缓冲器结构202彼此连接的第一裸片组合件304a及第二裸片组合件304b。装置300的第一裸片组合件304a包含半导体衬底206、形成于半导体衬底206的第一表面208a中及/或上的多个有源电路元件210、耦合到有源电路元件210的路由结构214，及耦合到路由结构214的第一绝缘材料216。在所说明实施例中，第一裸片组合件304a不包含在有源电路元件210与路由结构214之间的任何中间结构(例如，MOL结构)，使得路由结构214直接连接到有源电路元件210。第一裸片组合件304a可进一步包含从第二表面208b延伸穿过半导体衬底206及有源电路元件210而到路由结构214的第一通路218。在其它实施例中，可省略路由结构214，使得第一通路218直接电耦合到有源电路元件210，且终接在半导体衬底206的第一表面208a处或附近。
装置300的第二裸片组合件304b包含载体衬底220、耦合到载体衬底220的第一表面222a的中间结构212、耦合到中间结构212的重布结构224，及第二绝缘材料226。第二裸片组合件304b还可包含第二通路228，第二通路228延伸穿过载体衬底220及中间结构212的整个厚度，使得其电耦合到重布结构224。第二通路228可通过延伸穿过热缓冲器结构302的互连件结构232连接到第一裸片组合件304a的第一通路218。
图3A中说明的装置300的配置可通过将有源电路元件210与中间结构212及重布结构224两者热隔离而进一步减少传输到有源电路元件210的热量。例如，在一些实施例中，装置300是存储器装置(例如，NAND、DRAM、NOR等)，有源电路元件210包含CMOS电路系统，且中间结构212包含存储器阵列。在此类实施例中，存储器阵列与CMOS电路系统之间的分开可进一步改进存储器装置的性能及可靠性。
图3B是根据本技术的实施例的在制造过程期间的第一裸片组合件304a的示意性侧视横截面视图。用于制造第一裸片组合件304a的过程可类似于关于图2B描述的过程，不同之处在于路由结构214直接形成于有源电路元件210上而非在中间结构上。
图3C是根据本技术的实施例的在制造过程期间的第二裸片组合件304b的示意性侧视横截面视图。用于制造第二裸片组合件304b的过程可类似于关于图2C描述的过程，不同之处在于中间结构212形成于载体衬底220的第一表面222a上，且重布结构224可形成于中间结构212上。
图4A是根据本技术的实施例配置的包含热缓冲器结构402的半导体装置400的示意性侧视横截面视图。与图2A到3C的装置200、300相比，装置400不包含单独载体衬底或第二裸片组合件。代替地，热缓冲器结构402用于热隔离且作为用于制造重布结构224的衬底两者，如下文详细论述。图4A中展示的装置400的配置可有利地减小整体装置大小，且还可简化制造过程。
装置400包含裸片组合件404，裸片组合件404可与图2A到2B的第一裸片组合件204a及/或图3A到3B的第一裸片组合件304a相同或大体上类似。例如，裸片组合件404可包含具有第一表面208a及第二表面208b的半导体衬底206、形成于第一表面208a中及/或上的多个有源电路元件210、耦合到有源电路元件210的中间结构212、耦合到中间结构212的路由结构214，及耦合到路由结构214的第一绝缘材料216。在其它实施例中，中间结构212及/或路由结构214是任选的且可省略。
热缓冲器结构402包含第一表面406a(例如，前或有源表面)及第二表面406b(例如，后表面)。热缓冲器结构402的第二表面406b可直接耦合到半导体衬底206的第二表面208a。重布结构224可耦合到热缓冲器结构402的第一表面406a，且第二绝缘材料可耦合到重布结构224。在所说明实施例中，重布结构224直接耦合到热缓冲器结构402。然而，在其它实施例中，装置400可包含在重布结构224与热缓冲器结构402之间的一或多个额外结构(例如，如先前关于图3A到3C所描绘的例如存储器阵列的中间结构)。
热缓冲器结构402可将裸片组合件404的温度敏感组件(例如，有源电路元件210)与热缓冲器结构402的第一表面406a上的发热组件(例如，重布结构224)物理分开且热隔离。例如，为了减少或防止通过热缓冲器结构402的热传递，热缓冲器结构402可具有小于半导体衬底206的热导率的热导率。在一些实施例中，热缓冲器结构402的热导率不大于半导体衬底206的热导率的90％、80％、70％、60％、50％、40％、30％、20％、10％或5％。热缓冲器结构402可由热绝缘材料制成，所述热绝缘材料还适于用作衬底，重布结构224可形成于或以其它方式附接在所述衬底上。例如，热缓冲器结构402可由具有低热导率的模制材料(例如环氧树脂模制化合物或树脂)制成。热缓冲器结构402可具有任何适合厚度，例如在从10μm到50μm的范围内的厚度。
装置400可包含将路由结构214电耦合到重布结构224以在裸片组合件404与热缓冲器结构402的第一表面406a上的组件之间传输信号的一组通路或互连件418(例如，TSV)。如图4A中展示，通路418可延伸穿过热缓冲器结构402、半导体衬底206、有源电路元件210及中间结构212的整个厚度。在装置400的操作期间，来自有源电路元件210的信号可循序传输通过中间结构212、路由结构214及通路418而到重布结构224。随后，重布结构224可将信号路由到外部装置(未展示)。相反地，来自外部装置的信号可通过重布结构224路由到通路418，并随后传输通过路由结构214及中间结构212而到有源电路元件210。
图4B是根据本技术的实施例的在制造过程的阶段之后的裸片组合件404的示意性侧视横截面视图。用于制造裸片组合件404的过程可与关于图2B及3B描述的过程相同或大体上类似。例如，过程可涉及在半导体衬底206的第一表面208a上循序地形成有源电路元件210、中间结构212、路由结构214及第一绝缘材料216。接着，可形成穿过衬底206、有源电路元件210及中间结构214的通路418。
图4C是根据本技术的实施例的在制造过程的后续阶段之后的装置400的示意性侧视横截面视图。在已制造裸片组合件404之后，热缓冲器结构402可耦合到半导体衬底206的第二表面208a及/或形成于第二表面208a上(例如，通过模制、接合、沉积等)，且通路418可延伸穿过热缓冲器结构402。在其它实施例中，热缓冲器结构402可在通路418的任何部分经形成穿过衬底206、有源电路元件210、中间结构214或热缓冲器结构402之前形成于衬底206的第二表面208b上。接着，通路418可经形成穿过衬底206、有源电路元件210、中间结构214及热缓冲器结构402以电耦合到路由结构214。随后，额外装置组件(例如，重布结构424及第二绝缘材料426(图4A))可循序地形成于热缓冲器结构402的第一表面406a上。
图5到9说明根据本技术的实施例配置的各种半导体封装。尽管图5到9的半导体封装被描绘为并有与图2A的装置200相同或类似的半导体装置，但在其它实施例中，图5到9的半导体封装可包含在本文关于图2A到4C描述的其它半导体装置中的任何者。
图5是根据本技术的实施例配置的半导体封装500的示意性侧视横截面视图。封装500包含安装于封装衬底502上的半导体装置(例如，图2A到2C的装置200)。封装衬底502可为或包含中介层、印刷电路板、电介质间隔件、另一半导体裸片(例如，逻辑裸片)或另一适合衬底。任选地，封装衬底502可包含半导体组件(例如，掺杂硅晶片或砷化镓晶片)、非导电组件(例如，各种陶瓷衬底，例如氧化铝(Al2O3)等)、氮化铝及/或导电部分(例如，互连电路系统、TSV等)。
在所说明实施例中，装置200经安装到封装衬底502，使得第一裸片组合件204a邻近或靠近封装衬底502，第二裸片组合件204b与封装衬底502间隔开，且重布结构224定向成向上且远离封装衬底502(本文中还称为“BEOL向上”配置)。可使用所属领域的技术人员已知的任何适合裸片到衬底附接工艺来将装置200机械地耦合到封装衬底502。为了允许装置200与封装衬底502之间的信号传输，可通过将重布结构224电耦合到封装衬底502的一或多个线接合504来将装置200电耦合到封装衬底502。封装衬底502可进一步包含电连接器506(例如，焊料球、导电凸块、导电支柱、导电环氧树脂及/或其它适合导电元件)阵列，所述阵列电耦合到封装衬底502且经配置以将封装500电耦合到外部装置或电路系统(未展示)。
封装500可包含模制材料508，例如树脂、环氧树脂、聚硅氧基材料、聚酰亚胺或适于囊封装置200及/或封装衬底502的至少一部分以保护这些组件免受污染及/或物理损坏的任何其它材料。封装500还可包含例如外部散热器、外壳(例如，导热外壳)、电磁干扰(EMI)屏蔽组件等的其它组件。
图6是根据本技术的实施例配置的半导体封装600的示意性侧视横截面视图。封装600大体上类似于图5的封装500，不同之处在于装置200经安装到封装衬底502使得第一裸片组合件204a与封装衬底502间隔开，第二裸片组合件204b靠近封装衬底502，且重布结构224定向成向下且朝向封装衬底502(本文中还称为“BEOL向下”配置)。装置200可通过多个互连件结构602(例如，铜支柱或其它导电凸块、微凸块、支柱、柱、椿等)电耦合到封装衬底502，以在装置200与封装衬底502之间传输信号。互连件结构602可通过底部填充材料604(例如，毛细管底部填充材料)包围。
图7是根据本技术的实施例配置的半导体封装700的示意性侧视横截面视图。封装700包含由封装衬底704支撑的第一半导体装置702a及第二半导体装置702b。第一及第二装置702a到b垂直布置成堆叠，其中第一装置702a安装于封装衬底704上(例如，使用裸片到衬底附接技术)，且第二装置702b安装于第一装置702a上(例如，经由DAF706或其它裸片到裸片附接技术)。尽管图7说明两个经堆叠装置，但在其它实施例中，封装700可包含任何数目个经堆叠装置(例如，三个、四个、五个、六个、七个、八个、九个、十个或更多个装置)。另外，尽管第一及第二装置702a到b两者被展示为具有类似于图2A到2C的装置200的配置，但在其它实施例中，装置702a到b中的任何者可具有不同配置(例如，类似于图3A到4C的装置300、400的配置)。
在所说明实施例中，第一及第二装置702a到b两者沿相同方向(BEOL向上)定向，其中其相应重布结构724a、724b面向上且远离封装衬底704。信号可经由将第一装置702的重布结构724a电耦合到封装衬底704的第一组线接合707在第一装置702与封装衬底704之间传输。类似地，信号可经由将第二装置702b的重布结构724b电耦合到第一装置702a的重布结构724a的第二组线接合708在第一与第二装置702a到b之间传输。任选地，封装700可包含将第二装置702b的重布结构724b直接连接到封装衬底704的一或多个线接合(未展示)。因此，信号可经由线接合707、708以及第一及第二装置702a到b的相应重布结构724a到b及内部互连件718a到b在第一装置702a、第二装置702b及/或封装衬底704之间路由。
封装700还可包含额外半导体封装组件，例如电连接器710阵列及囊封第一及第二装置702a到b的模制材料712。封装衬底704、电连接器710及模制材料712可与上文关于图5论述的对应组件相同或大体上类似。
图8是根据本技术的实施例配置的半导体封装800的示意性侧视横截面视图。封装800大体上类似于图7的封装700，不同之处在于第一装置702a在与第二装置702b不同的方向上定向。在所说明实施例中，例如，第一装置702a的重布结构724a面向下(BEOL向下)且朝向封装衬底704，而第二装置702b的重布结构724b面向上且远离封装衬底704(BEOL向上)。
第一装置702a可经由多个互连件结构802及底部填充材料804(例如，如先前关于图6所论述)电气地且机械地耦合到封装衬底704，以允许第一装置702a与封装衬底704之间的信号路由。互连件结构802及底部填充材料804可使用任何适合过程形成，例如TCB/质量回流操作。第二装置702b的重布结构724b可经由一组线接合808电连接到第一装置702a的重布结构724a，以在第一与第二装置702a到b之间传输信号。任选地，封装800可包含将第二装置702b的重布结构724b直接电耦合到封装衬底704的一或多个线接合(未展示)。因此，信号可经由互连件结构802、线接合808以及第一及第二装置702a到b的相应重布结构724a到b及内部互连件718a到b在第一装置702a、第二装置702b及/或封装衬底704之间路由。
图9是根据本技术的实施例配置的半导体封装900的示意性侧视横截面视图。封装900大体上类似于图8的封装800，不同之处在于第一及第二装置702a到b两者经定向使得其相应重布结构724a到b面向下且朝向封装衬底704(BEOL向下)。类似于图8的封装800，第一装置702a经由重布结构724a与封装衬底704之间的多个互连件结构802及底部填充材料804电气地且机械地耦合到封装衬底704。
第二装置702b的重布结构724b可经由多个互连件结构902及底部填充材料904电气地且机械地耦合到第一装置702a(例如，耦合到路由结构714a)。互连件结构902及底部填充材料904可使用任何适合过程形成，例如TCB/质量回流操作。因此，信号可经由互连件结构802、902、路由结构714a以及第一及第二装置702a、702b的相应重布结构724a到b及内部互连件718a、718b在第一装置702a、第二装置702b及/或封装衬底704之间路由。在一些实施例中，第一装置702a包含比第二装置702b多的内部互连件718a，以例如适应第二装置702b与封装衬底704之间的信号路由。
具有上文关于图2A到9描述的特征的半导体装置及/或封装中的任一者可并入到无数更大及/或更复杂系统中的任何者中，所述系统的代表性实例是在图10中示意性地展示的系统1000。系统1000可包含处理器1002、存储器1004(例如，SRAM、DRAM、快闪及/或其它存储器装置)、输入/输出装置1006，及/或其它子系统或组件1008。上文关于图2A到9描述的半导体裸片及/或封装可包含于图10中展示的元件中的任何者中。所得系统1000可经配置以执行各种各样的合适计算、处理、存储、感测、成像及/或其它功能中的任何者。因此，系统1000的代表实例包含(不限于)计算机及/或其它数据处理器，例如桌面计算机、膝上型计算机、因特网器具、手持式装置(例如，掌上计算机、可穿戴计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器或可编程消费型电子器件、网络计算机及微型计算机。系统1000的额外代表性实例包含灯、相机、车辆等。关于这些及其它实例，系统1000可容置于单个单元中或例如通过通信网络分布在多个经互连单元上。因此，系统1000的组件可包含本地及/或远程存储器存储装置及各种各样的合适计算机可读媒体中的任何者。
从前文将了解，本文中已为说明的目的描述本技术的特定实施例，但可在不脱离本公开的情况下作出各种修改。因此，本发明除了如由随附权利要求书所限制之外不受限制。此外，在特定实施例的上下文中描述的新颖技术的特定方面还可在其它实施例中组合或消除。此外，尽管与新颖技术的特定实施例相关联的优点已在所述实施例的上下文中描述，但其它实施例还可展现此类优点，且并非所有实施例必然需要展现此类优点以落入本技术的范围内。因此，本公开及相关联技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (22)

1.一种半导体装置，其包括：
第一裸片组合件，其包含-
半导体衬底，其包含第一表面及与所述第一表面相对的第二表面，及
多个有源电路元件，其在所述半导体衬底的所述第一表面处；
第二裸片组合件，其包含-
载体衬底，其包含第一表面及与所述第一表面相对的第二表面，及
重布结构，其在所述载体衬底的所述第一表面上或上方；
热缓冲器结构，其在所述第一与所述第二裸片组合件之间，其中所述热缓冲器结构耦合到所述半导体衬底的所述第二表面及所述载体衬底的所述第二表面；及
多个互连件，其至少延伸穿过所述半导体衬底、所述载体衬底及所述热缓冲器结构，其中所述互连件将所述有源电路元件电耦合到所述重布结构。
2.根据权利要求1所述的半导体装置，其中所述热缓冲器结构的导热性低于所述半导体衬底。
3.根据权利要求1所述的半导体装置，其中所述热缓冲器结构包括底部填充材料、非导电膜或裸片附接膜。
4.根据权利要求1所述的半导体装置，其中所述重布结构经配置以在所述有源电路元件与外部装置之间路由信号。
5.根据权利要求1所述的半导体装置，其中所述重布结构直接耦合到所述载体衬底。
6.根据权利要求1所述的半导体装置，其中所述第二裸片组合件进一步包括在所述重布结构与所述载体衬底之间的至少一个中间结构。
7.根据权利要求6所述的半导体装置，其中所述至少一个中间结构包括存储器阵列。
8.根据权利要求1所述的半导体装置，其中：
所述第一裸片组合件进一步包括邻近或靠近所述有源电路元件的路由结构；及
所述互连件经由所述路由结构将所述重布结构电耦合到所述有源电路元件。
9.根据权利要求8所述的半导体装置，其中所述路由结构比所述重布结构薄。
10.根据权利要求8所述的半导体装置，其中所述第一裸片组合件进一步包括在所述有源电路元件与所述路由结构之间的至少一个中间结构。
11.根据权利要求10所述的半导体装置，其中所述至少一个中间结构包括存储器阵列。
12.根据权利要求1所述的半导体装置，其中所述互连件包含：(a)延伸穿过所述半导体衬底的多个第一通路；(b)延伸穿过所述载体衬底的多个第二通路；及(c)延伸穿过所述热缓冲器结构的多个互连件结构。
13.一种制造半导体装置的方法，所述方法包括：
形成第一裸片组合件，所述第一裸片组合件包含-
半导体衬底，其包含第一表面及与所述第一表面相对的第二表面，及
多个有源电路元件，其在所述半导体衬底的所述第一表面处；
形成第二裸片组合件，所述第二裸片组合件包含-
载体衬底，其包含第一表面及与所述第一表面相对的第二表面，及
重布结构，其在所述载体衬底的所述第一表面上或上方；
将热缓冲器结构定位于所述第一与所述第二裸片组合件之间，其中所述热缓冲器结构耦合到所述半导体衬底的所述第二表面及所述载体衬底的所述第二表面；
经由至少延伸穿过所述半导体衬底、所述载体衬底及所述热缓冲器结构的多个互连件将所述有源电路元件电耦合到重布结构。
14.根据权利要求13所述的方法，其中所述热缓冲器结构经配置以减少从所述重布结构到所述有源电路元件的热传输。
15.根据权利要求13所述的方法，其中：
形成所述第一裸片组合件包含：形成穿过所述半导体衬底的第一组通路；
形成所述第二裸片组合件包含：形成穿过所述载体结构的第二组通路；及
将所述有源电路元件电耦合到所述重布结构包含：使用延伸穿过所述热缓冲器结构的多个互连件结构来将所述第一组通路连接到所述第二组通路。
16.根据权利要求13所述的方法，其中形成所述第二裸片组合件包含：
在所述载体衬底上形成中间结构；及
在所述中间结构上形成所述重布结构。
17.根据权利要求13所述的方法，其中形成所述第一裸片组合件包含：在所述有源电路元件上形成中间结构。
18.根据权利要求13所述的方法，其进一步包括将所述重布结构电耦合到封装衬底或另一半导体装置。
19.一种半导体装置，其包括：
半导体衬底，其包含第一表面及与所述第一表面相对的第二表面；
多个有源电路元件，其在所述半导体衬底的所述第一表面处；
热缓冲器结构，其包含第一表面及与所述第一表面相对的第二表面，所述热缓冲器结构的所述第二表面耦合到所述半导体衬底的所述第二表面，其中所述热缓冲器结构包括模制材料：
重布结构，其在所述热缓冲器结构的所述第一表面上或上方；及
多个互连件，其至少延伸穿过所述半导体衬底及所述热缓冲器结构，其中所述互连件将所述有源电路元件电耦合到所述重布结构。
20.根据权利要求19所述的装置，其中所述重布结构直接耦合到所述热缓冲器结构的所述第一表面。
21.根据权利要求19所述的装置，其进一步包括在所述重布结构与所述热缓冲器结构之间的至少一个中间结构。
22.根据权利要求19所述的装置，其中所述热缓冲器结构的导热性低于所述半导体衬底。
CN202180052419.XA 2020-07-28 2021-07-19 具有热隔离结构的半导体装置 Pending CN116057692A (zh)

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