CN116055259A - Continuous time linear equalizer circuit - Google Patents
Continuous time linear equalizer circuit Download PDFInfo
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- CN116055259A CN116055259A CN202211690748.XA CN202211690748A CN116055259A CN 116055259 A CN116055259 A CN 116055259A CN 202211690748 A CN202211690748 A CN 202211690748A CN 116055259 A CN116055259 A CN 116055259A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
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Abstract
The invention provides a continuous time linear equalizer circuit, comprising: a source degeneration differential pair; an active inductor circuit, a first end of the active inductor is electrically connected with a first output end of the source degeneration differential pair; the second end of the active inductor is electrically connected with the second output end of the source degeneration differential pair; the third end and the fourth end of the active inductor are electrically connected with a voltage source; and the first end of the negative capacitor circuit is electrically connected with the first output end of the source degeneration differential pair, the second end of the negative capacitor is electrically connected with the second output end of the source degeneration differential pair, and the third end and the fourth end of the negative capacitor are grounded. The continuous time linear equalizer circuit provided by the invention can effectively improve the peak frequency and the equalization intensity of the continuous time linear equalizer.
Description
Technical Field
The invention relates to the technical field of equalizer, in particular to a continuous time linear equalizer circuit.
Background
The invention proposes a continuous-time linear equalizer (Continuous Time Linear equalizer, CTLE) that expands bandwidth based on active inductance and negative capacitance techniques. CTLE is an equalizer widely used in high-speed serial interface circuits, providing maximum equalization at the nyquist frequency of the signal, and acting with low-pass channels to form a higher bandwidth system for distortion-free transmission of the signal. As the data rate increases, the nyquist frequency of the signal also increases, so bandwidth needs to be extended for conventional CTLEs. The most common bandwidth expansion technique is inductive peaking, and passive inductance can expand bandwidth but has a large passive inductance area, so that the chip area is greatly increased. How to make CTLE of high-speed serial interface circuit have lower power consumption, smaller area and higher speed is a problem to be solved.
Disclosure of Invention
The continuous time linear equalizer circuit provided by the invention can effectively improve the peak frequency and the equalization intensity of the continuous time linear equalizer.
The invention provides a continuous time linear equalizer circuit, comprising:
a source degeneration differential pair;
an active inductor circuit, a first end of the active inductor is electrically connected with a first output end of the source degeneration differential pair; the second end of the active inductor is electrically connected with the second output end of the source degeneration differential pair; the third end and the fourth end of the active inductor are electrically connected with a voltage source;
and the first end of the negative capacitor circuit is electrically connected with the first output end of the source degeneration differential pair, the second end of the negative capacitor is electrically connected with the second output end of the source degeneration differential pair, and the third end and the fourth end of the negative capacitor are grounded.
Optionally, the source degeneration differential pair includes:
the first end of the first MOS tube is electrically connected with the first output end, the second end of the first MOS tube is grounded, and the grid electrode of the first MOS tube is electrically connected with a first input signal source;
the first end of the first MOS tube is electrically connected with the second output end, the second end of the first MOS tube is grounded, and the grid electrode of the first MOS tube is electrically connected with a second input signal source;
the first end of the first resistor is electrically connected with the second end of the first MOS tube, and the second end of the first resistor is electrically connected with the second end of the second MOS tube;
a first capacitor, wherein a first end of the first capacitor is electrically connected with a first end of the first resistor, and a second end of the first capacitor is electrically connected with a second end of the first resistor;
the first end of the second capacitor is electrically connected with the first end of the first MOS tube, and the second end of the second capacitor is grounded;
and the first end of the third capacitor is electrically connected with the first end of the second MOS tube, and the second end of the third capacitor is grounded.
Optionally, the second capacitor and the third capacitor have the same characteristics, and the first MOS transistor and the second MOS transistor have the same characteristics.
Optionally, the first end of the first MOS transistor is a drain, and the second end of the first MOS transistor is a source; the first end of the second MOS tube is a drain electrode, and the second end of the second MOS tube is a source electrode.
Optionally, the negative capacitance circuit includes:
the first end of the third MOS tube is electrically connected with the first output end of the source degeneration differential pair, the second end of the third MOS tube is grounded, and the grid electrode of the third MOS tube is electrically connected with the second output end of the source degeneration differential pair;
the first end of the fourth MOS tube is electrically connected with the second output end of the source degeneration differential pair, the second end of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is electrically connected with the first output end of the source degeneration differential pair;
and the first end of the fourth capacitor is electrically connected with the second end of the third MOS tube, and the second end of the fourth capacitor is electrically connected with the second end of the fourth MOS tube.
Optionally, the third MOS transistor and the fourth MOS transistor have the same characteristics.
Optionally, the first end of the third MOS transistor is a drain, and the second end of the third MOS transistor is a source; the first end of the fourth MOS tube is a drain electrode, and the second end of the fourth MOS tube is a source electrode.
Optionally, the active inductance circuit includes:
the first end of the fifth MOS tube is electrically connected with a power supply, the second end of the fifth MOS tube is electrically connected with the first output end of the source degeneration differential pair, and the second end of the fifth MOS tube is electrically connected with the grid electrode of the fifth MOS tube through a second resistor;
the first end of the sixth MOS tube is electrically connected with a power supply, the second end of the sixth MOS tube is electrically connected with the second output end of the source degeneration differential pair, and the second end of the sixth MOS tube is electrically connected with the grid electrode of the sixth MOS tube through a third resistor;
a fifth capacitor, wherein a first end of the fifth capacitor is electrically connected with the gate of the fifth MOS tube, and a second end of the fifth capacitor is electrically connected with the second end of the sixth MOS tube;
and the first end of the sixth capacitor is electrically connected with the grid electrode of the sixth MOS tube, and the second end of the sixth capacitor is electrically connected with the second end of the fifth MOS tube.
Optionally, the fifth MOS transistor and the sixth MOS transistor have the same characteristic, the fifth capacitor and the sixth capacitor have the same characteristic, and the second resistor and the third resistor have the same characteristic.
Optionally, the first end of the fifth MOS transistor is a source, and the second end of the fifth MOS transistor is a drain; the first end of the sixth MOS tube is a source electrode, and the second end of the sixth MOS tube is a drain electrode.
In the technical scheme provided by the invention, the impedance is increased along with the increase of the frequency by adopting the active inductance circuit, the load impedance is endowed with the characteristic of inductance, and the negative capacitance circuit is adopted to generate a capacitive negative impedance at the output node, so that the effect of capacitance at the output node can be counteracted, and the base point frequency at the output node is increased.
Drawings
FIG. 1 is a schematic diagram of a continuous-time linear equalizer circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a negative capacitance circuit of a continuous-time linear equalizer circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a negative capacitance circuit equivalent of a continuous-time linear equalizer circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a continuous-time linear equalizer circuit with a negative capacitance circuit according to an embodiment of the present invention;
FIG. 5 is an equivalent schematic diagram of a continuous-time linear equalizer circuit with negative capacitance according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the active inductance of a continuous-time linear equalizer circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a continuous-time linear equalizer circuit according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the present invention provides a continuous time linear equalizer circuit, as shown in fig. 1, including:
a source degeneration differential pair;
an active inductor circuit, wherein a first end of the active inductor is electrically connected with a first output end Voutn of the source degeneration differential pair; the second end of the active inductor is electrically connected with the second output end Voutp of the source degeneration differential pair; the third end and the fourth end of the active inductor are electrically connected with a voltage source;
and the first end of the negative capacitor circuit is electrically connected with the first output end Voutn of the source degeneration differential pair, the second end of the negative capacitor is electrically connected with the second output end Voutp of the source degeneration differential pair, and the third end and the fourth end of the negative capacitor are grounded.
In the technical scheme provided by the embodiment of the invention, the impedance is increased along with the increase of the frequency by adopting the active inductance circuit, the load impedance is endowed with the characteristic of inductance, and the negative capacitance circuit is adopted to generate a capacitive negative impedance at the output node, so that the effect of capacitance at the output node can be counteracted, and the base point frequency at the output node is increased.
As an alternative embodiment, the source degeneration differential pair includes:
the first MOS tube M1, the first end of the first MOS tube M1 is electrically connected with the first output end Voutn, the second end of the first MOS tube M1 is grounded, and the grid electrode of the first MOS tube M1 is electrically connected with the first input signal source Vinp;
the first end of the first MOS tube M1 is electrically connected with the second output end Voutp, the second end of the first MOS tube M1 is grounded, and the grid electrode of the first MOS tube M1 is electrically connected with a second input signal source Vinn;
the first end of the first resistor RS is electrically connected with the second end of the first MOS tube M1, and the second end of the first resistor RS is electrically connected with the second end of the second MOS tube M2;
a first capacitor Cs, a first end of which is electrically connected to the first end of the first resistor RS, and a second end of which is electrically connected to the second end of the first resistor RS;
the first end of the second capacitor Cp is electrically connected with the first end of the first MOS tube M1, and the second end of the second capacitor Cp is grounded;
and a first end of the third capacitor Cp is electrically connected to the first end of the second MOS transistor M2, and a second end of the third capacitor Cp is grounded.
As an alternative embodiment, the second capacitor Cp and the third capacitor Cp have the same characteristics, and the first MOS transistor M1 and the second MOS transistor M2 have the same characteristics.
As an optional implementation manner, the first end of the first MOS transistor M1 is a drain, and the second end of the first MOS transistor M1 is a source; the first end of the second MOS tube M2 is a drain electrode, and the second end of the second MOS tube M2 is a source electrode.
As an alternative embodiment, as shown in fig. 2, the negative capacitance circuit includes:
the first end of the third MOS tube M3 is electrically connected with the first output end Voutn of the source degeneration differential pair, the second end of the third MOS tube M3 is grounded, and the grid electrode of the third MOS tube M3 is electrically connected with the second output end Voutp of the source degeneration differential pair;
the first end of the fourth MOS tube M4 is electrically connected with the second output end Voutp of the source degeneration differential pair, the second end of the fourth MOS tube M4 is grounded, and the grid electrode of the fourth MOS tube M4 is electrically connected with the first output end Voutn of the source degeneration differential pair;
and the first end of the fourth capacitor C is electrically connected with the second end of the third MOS tube M3, and the second end of the fourth capacitor C is electrically connected with the second end of the fourth MOS tube M4.
As an alternative embodiment, the third MOS transistor M3 and the fourth MOS transistor M4 have the same characteristics.
As an optional implementation manner, the first end of the third MOS transistor M3 is a drain, and the second end of the third MOS transistor M3 is a source; the first end of the fourth MOS tube M4 is a drain electrode, and the second end of the fourth MOS tube M4 is a source electrode.
In some embodiments, the cross-coupling connection is such that the output currents of transistors M3 and M4 are of opposite polarity to the differential voltage, so that the output impedance is negative. Assuming that the output resistances ro of M3 and M4 are infinity, the node equations are listed according to the small signal equivalent circuit diagram shown in fig. 2 as shown in fig. 3:
V X ＝-V Y
V outn ＝-V outp
g m3 (V outn -V X )+(V outn -V X )sC gs ＝(V X -V Y )sC
wherein V is X And V Y Source voltages of the transistor M3 and the transistor M4, V outn And V outp Output voltages g of the drain terminals of the transistor M3 and the transistor M4 respectively m3 Is the transconductance of transistor M3, C gs Is the gate-source capacitance of transistor M3 and transistor M4, and C is the capacitance across the source of transistor M3 and the source of transistor M4.
The current flowing from Voutp is:
i＝g m3 (V outn -V X )+(V outp -V Y )sC gs
the single-ended equivalent impedance is:
due to C gs C and the operating frequency f of the circuit is generally much smaller than the characteristic frequency of the device
The equivalent impedance is further expressed as:
after the negative capacitance circuit is added to the output end of the CTLE, the capacitance at the output node is reduced, so that the negative capacitance technology can increase the high-frequency peak frequency and gain and expand the bandwidth.
As shown in fig. 4, a CTLE schematic diagram based on negative capacitance technology is shown, in which a negative capacitance circuit is added to an output node, an equivalent circuit is shown in fig. 5, and according to the equivalent circuit, a column node equation of a half-side small-signal equivalent circuit after adding a negative capacitance is shown:
wherein V is out For the output voltage, C is the capacitance across the source of transistor M3 and the source of transistor M4, C P R is parasitic capacitance of output node D G is the load resistance m3 Is the transconductance, g, of transistor M3 m1 Is the transconductance of transistor M1, V in For input voltage, V S1 For the source voltage of transistor M1, C S And R is S A source degeneration capacitor and a source degeneration resistor connected across the source of transistor M and the source of transistor M2, respectively.
The transfer function of CTLE after addition of negative capacitance is:
the two zero points are respectively:
the main pole is:
the damping coefficient is:
the natural frequency is:
as an alternative embodiment, as shown in fig. 6, the active inductance circuit includes:
a fifth MOS tube M5, wherein the first end of the fifth MOS tube M5 is electrically connected with a power source, the second end of the fifth MOS tube M5 is electrically connected with the first output end Voutn of the source degeneration differential pair, and the second end of the fifth MOS tube M5 is electrically connected with the grid electrode of the fifth MOS tube M5 through a second resistor R G Electrically connecting;
a sixth MOS tube M6, wherein the first end of the sixth MOS tube M6 is electrically connected with the power source, the second end of the sixth MOS tube M6 is electrically connected with the second output end Voutp of the source degeneration differential pair, and the second end of the sixth MOS tube M6 is electrically connected with the grid electrode of the sixth MOS tube M6 through a third resistor R G Electrically connecting;
fifth capacitor C G The fifth capacitor C G Is electrically connected with the gate of the fifth MOS transistor M5, and the fifth capacitor C G Is electrically connected with the second end of the sixth MOS tube M6;
sixth capacitor C G The sixth capacitor C G Is electrically connected with the grid electrode of the sixth MOS tube M6, and the sixth capacitor C G Is electrically connected to the second end of the fifth MOS transistor M5.
As an alternative embodiment, the fifth MOS transistor M5 and the sixth MOS transistor M6 have the same characteristics, and the fifth capacitor C G And the sixth capacitance C G Having the same characteristics, the second resistor R G And the third resistor R G Have the same characteristics.
As an optional implementation manner, the first end of the fifth MOS transistor M5 is a source, and the second end of the fifth MOS transistor M5 is a drain; the first end of the sixth MOS transistor M6 is a source, and the second end of the sixth MOS transistor M6 is a drain.
In some embodiments, the active inductance improves the high frequency impedance by utilizing the amplifying characteristics of the transistor, and the cross-coupling connection is such that the gate of the transistor and the output node are connected through a capacitor, and the capacitor CG is regarded as a short circuit at high frequency, and a positive feedback channel is provided, so that the transistors M5 and M6 can act as an amplifier. The equivalent circuit is the same as the traditional active inductance at low frequency, the low-frequency impedance is unchanged, and the positive feedback improves the highThe load impedance at frequency, the boost factor G is higher. Z of active inductance load,diff The method comprises the following steps:
wherein r is 0 G is the output resistance of transistor M5 m Is the transconductance of transistor M5, R G C is the resistance applied between the gate and source of transistor M5 G Is the capacitance applied between the gate of transistor M6 and the source of transistor M5.
The pole zero is easily known as:
to ensure the stability of the system, the pole ω p Must be a left half-plane pole, so:
g m r 0 R G <4r 0 +R G
active inductance boost factor G Proposed The method comprises the following steps:
lifting factor G of active inductance Proposed And the boost factor G of the traditional active inductance conventional The ratio is:
in order to ensure that the active inductance has a larger peaking value and to stabilize the system, the following conditions need to be met:
as shown in fig. 7, by simulating the circuit provided by the embodiments of the present invention, the CTLE transfer function based on the active inductance and the negative capacitance technology can be used for R in the CTLE transfer function based on the negative capacitance technology D Impedance Z replaced by novel active inductance load,diff The obtained product is not described in detail. FIG. 7 is a simulation result of CTLE amplitude-frequency response, wherein the gray curve is an amplitude-frequency response curve of the traditional CTLE, the peak frequency is 15.8GHz, and the equilibrium strength is 3.36dB; the black curve is the amplitude-frequency response curve of CTLE based on active inductance and negative capacitance technology, the peak frequency is 27.5GHz, and the equilibrium intensity is 8.52dB. As can be seen from the figure, the CTLE based on the active inductance and negative capacitance technology can effectively improve the peak frequency and the equilibrium strength of the CTLE.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A continuous-time linear equalizer circuit, comprising:
a source degeneration differential pair;
an active inductor circuit, a first end of the active inductor is electrically connected with a first output end of the source degeneration differential pair; the second end of the active inductor is electrically connected with the second output end of the source degeneration differential pair; the third end and the fourth end of the active inductor are electrically connected with a voltage source;
and the first end of the negative capacitor circuit is electrically connected with the first output end of the source degeneration differential pair, the second end of the negative capacitor is electrically connected with the second output end of the source degeneration differential pair, and the third end and the fourth end of the negative capacitor are grounded.
2. The circuit of claim 1, wherein the source degeneration differential pair comprises:
the first end of the first MOS tube is electrically connected with the first output end, the second end of the first MOS tube is grounded, and the grid electrode of the first MOS tube is electrically connected with a first input signal source;
the first end of the first MOS tube is electrically connected with the second output end, the second end of the first MOS tube is grounded, and the grid electrode of the first MOS tube is electrically connected with a second input signal source;
the first end of the first resistor is electrically connected with the second end of the first MOS tube, and the second end of the first resistor is electrically connected with the second end of the second MOS tube;
a first capacitor, wherein a first end of the first capacitor is electrically connected with a first end of the first resistor, and a second end of the first capacitor is electrically connected with a second end of the first resistor;
the first end of the second capacitor is electrically connected with the first end of the first MOS tube, and the second end of the second capacitor is grounded;
and the first end of the third capacitor is electrically connected with the first end of the second MOS tube, and the second end of the third capacitor is grounded.
3. The circuit of claim 2, wherein the second capacitor and the third capacitor have the same characteristics, and the first MOS transistor and the second MOS transistor have the same characteristics.
4. The circuit of claim 2, wherein a first end of the first MOS transistor is a drain and a second end of the first MOS transistor is a source; the first end of the second MOS tube is a drain electrode, and the second end of the second MOS tube is a source electrode.
5. The circuit of claim 1, wherein the negative capacitance circuit comprises:
the first end of the third MOS tube is electrically connected with the first output end of the source degeneration differential pair, the second end of the third MOS tube is grounded, and the grid electrode of the third MOS tube is electrically connected with the second output end of the source degeneration differential pair;
the first end of the fourth MOS tube is electrically connected with the second output end of the source degeneration differential pair, the second end of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is electrically connected with the first output end of the source degeneration differential pair;
and the first end of the fourth capacitor is electrically connected with the second end of the third MOS tube, and the second end of the fourth capacitor is electrically connected with the second end of the fourth MOS tube.
6. The circuit of claim 5, wherein the third MOS transistor and the fourth MOS transistor have the same characteristics.
7. The circuit of claim 5, wherein a first end of the third MOS transistor is a drain and a second end of the third MOS transistor is a source; the first end of the fourth MOS tube is a drain electrode, and the second end of the fourth MOS tube is a source electrode.
8. The circuit of claim 1, wherein the active inductor circuit comprises:
the first end of the fifth MOS tube is electrically connected with a power supply, the second end of the fifth MOS tube is electrically connected with the first output end of the source degeneration differential pair, and the second end of the fifth MOS tube is electrically connected with the grid electrode of the fifth MOS tube through a second resistor;
the first end of the sixth MOS tube is electrically connected with a power supply, the second end of the sixth MOS tube is electrically connected with the second output end of the source degeneration differential pair, and the second end of the sixth MOS tube is electrically connected with the grid electrode of the sixth MOS tube through a third resistor;
a fifth capacitor, wherein a first end of the fifth capacitor is electrically connected with the gate of the fifth MOS tube, and a second end of the fifth capacitor is electrically connected with the second end of the sixth MOS tube;
and the first end of the sixth capacitor is electrically connected with the grid electrode of the sixth MOS tube, and the second end of the sixth capacitor is electrically connected with the second end of the fifth MOS tube.
9. The circuit of claim 8, wherein the fifth MOS transistor and the sixth MOS transistor have the same characteristics, the fifth capacitor and the sixth capacitor have the same characteristics, and the second resistor and the third resistor have the same characteristics.
10. The circuit of claim 1, wherein a first end of the fifth MOS transistor is a source and a second end of the fifth MOS transistor is a drain; the first end of the sixth MOS tube is a source electrode, and the second end of the sixth MOS tube is a drain electrode.
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| CN202211690748.XA CN116055259A (en) | 2022-12-27 | 2022-12-27 | Continuous time linear equalizer circuit |
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| CN202211690748.XA CN116055259A (en) | 2022-12-27 | 2022-12-27 | Continuous time linear equalizer circuit |
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