CN116054752A - Signal amplifying circuit for two-way Ethernet power supply system - Google Patents

Signal amplifying circuit for two-way Ethernet power supply system Download PDF

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CN116054752A
CN116054752A CN202310065801.5A CN202310065801A CN116054752A CN 116054752 A CN116054752 A CN 116054752A CN 202310065801 A CN202310065801 A CN 202310065801A CN 116054752 A CN116054752 A CN 116054752A
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mos tube
electrically connected
electrode
unit
operational amplifier
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CN116054752B (en
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汪德文
徐春
吉巍
陈杰
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Wuxi Zhongxiang Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection

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  • Amplifiers (AREA)

Abstract

The invention relates to the technical field of signal amplification of power over Ethernet, and discloses a signal amplification circuit used in a two-way power over Ethernet system, which comprises a conversion unit, a current mirror unit and an amplification unit; when the invention is actually used, two voltage differences input from the outside are converted into corresponding currents through the conversion unit, then the currents are converted into voltages through the amplification unit pair, and according to ohm's law, when the two voltage differences are converted into the currents, the two voltage differences need to be divided by a resistance value, so when the two voltage differences change greatly, the corresponding current change is small, and the problem that the output voltage finally output by the invention has signal distortion can not be avoided; in addition, the amplifying unit amplifies the input current into voltage, so that the conversion unit does not need to be provided with excessive resistors, and the chip area and the thermal noise can be reduced.

Description

Signal amplifying circuit for two-way Ethernet power supply system
Technical Field
The invention relates to the technical field of power over Ethernet signal amplification, in particular to a signal amplifying circuit used in a two-way power over Ethernet system.
Background
PoE (Power over Ethernet) refers to a technology for transmitting power through a network cable, and performs data transmission and power supply for IP terminal devices (such as IP phones, APs, IP cameras, etc.) simultaneously through the existing ethernet, i.e. through the network cable. To address the suitability problem between different vendors of powered and powered devices, the IEEE standards Committee issued the IEEE 802.3af standard, the IEEE 802.3at standard, and the IEEE 802.3bt standard sequentially. Where the IEEE 802.3af standard specifies that PSE devices need to provide up to 15.4W of dc power on each port, the IEEE 802.3at standard provides up to 25.5W of power based on compliance with the 802.3af standard.
For special occasions requiring high power, a two-way power over ethernet system is often required to supply power, so that higher power supply can be provided. However, due to the impedance difference between the two power supply systems, a certain current difference exists between the two power supply systems, so that the stability of the power supply systems is affected. In order to avoid the occurrence of the situations, an equalizing circuit is added in the existing two-way power supply system to detect the power supply power of the two-way power supply system, and the transmission power of the two-way power supply system is timely adjusted, so that the power supply system meets the use requirement.
The equalizing circuit is often provided with an amplifying circuit, and the voltage difference output by the two-way power supply system is differentially amplified by the amplifying circuit. The current circuit installation working principle for realizing differential amplification can be divided into a three-operational amplifier, a switched capacitor amplifier, a current feedback amplifier and an amplifier with a Rong Ouge chopper. The most widely used three-operational amplifier is shown in fig. 1, and comprises a two-stage amplifying circuit, wherein the operational amplifier A1, the operational amplifier A2, the resistor R5, the resistor R6 and the resistor RG form a one-stage amplifying circuit, and the input voltage is buffered through the operational amplifier A1 and the operational amplifier A2, so that the input impedance is improved; the operational amplifier A3, the resistor R1, the resistor R2, the resistor R3, and the resistor R4 constitute a two-stage differential amplification circuit for amplifying a differential voltage, which can suppress a common mode voltage at the same time.
For the three-operational amplifier shown in fig. 1, the principle of virtual short input end of the ideal operational amplifier can be obtained
U i1 ＝U A ，U i2 ＝U B ；
Can be obtained by the principle of virtual break of the input end of an ideal operational amplifier
Figure BDA0004062252460000021
When R5 and R6 are equal, it is possible to obtain
Figure BDA0004062252460000022
If let r1=r3, let r2=r4, it is possible to obtain according to the nature of the differential amplifying circuit
Figure BDA0004062252460000023
/>
The three operational amplifier differential amplifying circuits obtain gain a v The method comprises the following steps:
Figure BDA0004062252460000024
from gain A v The calculation formula of the three operational amplifier differential amplifying circuit can be obtained, the three operational amplifier differential amplifying circuit mainly uses resistors to form voltage feedback and obtain constant gain, in addition, the gain can be controlled by changing the size of the resistor RG, the three operational amplifier differential amplifying circuit is realized without changing other performance parameters, and the three operational amplifier differential amplifying circuit is very simple and convenient, and the common mode rejection ratio can reach 80dB.
The circuit shown in fig. 1 has the following problems in practical use: first, VDD has been required to be less than 1.5V for some sub-micron scale processes. Due to the amplification of the first-stage amplifying circuit, the input voltage may be amplified to be close to VDD at the high-gain nodes a and B, and the excessively high voltage of the nodes may cause the excessively high voltage of the input terminal of the operational amplifier A3, thereby causing signal distortion of the output terminal and also affecting the signal-to-noise ratio. Second, since the circuit requires regulation of gain and establishment of voltage feedback through resistors, and the common mode rejection ratio of the secondary amplification circuit depends on resistor matching, the resistors must be sufficiently accurate to reduce the common mode gain, which is typically achieved by increasing the area of the resistors. The introduction of resistors, however, on the one hand, occupies a large chip area and, in addition, causes relatively high thermal noise, and requires circuitry to provide a large dynamic range.
Disclosure of Invention
In view of the shortcomings of the background art, the invention provides a signal amplifying circuit used in a two-way power over ethernet system, and aims to solve the technical problems that the amplifying circuit used in the two-way power over ethernet system occupies a larger chip area and brings thermal noise when a high common mode rejection ratio is obtained by adopting an accurate resistor.
In order to solve the technical problems, the invention provides the following technical scheme: a signal amplifying circuit for a two-way power over Ethernet system includes
A conversion unit including a first voltage input terminal and a second voltage input terminal for converting a difference between a voltage input from the first voltage input terminal and a voltage input from the second voltage input terminal into a first current;
the current mirror unit is electrically connected with the conversion unit and is used for mirroring the first current and outputting a second current;
and the amplifying unit is electrically connected with the mirror image unit and is used for converting the second current into output voltage.
In a certain embodiment, the conversion unit includes an operational amplifier A1, an operational amplifier A2, a MOS transistor Mn1, a MOS transistor Mp3, and a resistor R1; the current mirror unit comprises a MOS tube Mp1 and a MOS tube Mp2;
the negative input end of the operational amplifier A1 is the first voltage input end, and the positive input end of the operational amplifier A1 is electrically connected with one end of the resistor R1, the drain electrode of the MOS tube MP3, the grid electrode of the MOS tube MP3 and the grid electrode of the MOS tube MP4 respectively; the source electrode of the MOS tube MP3 is respectively and electrically connected with the drain electrode of the MOS tube MP1, the grid electrode of the MOS tube MP2 and the output end of the operational amplifier A1; the source electrode of the MOS tube MP1 is electrically connected with the source electrode of the MOS tube MP2; the drain electrode of the MOS tube MP2 is electrically connected with the source electrode of the MOS tube MP4, the drain electrode of the MOS tube MP4 is electrically connected with the amplifying unit, and the second current is output;
the negative input end of the operational amplifier A2 is the second voltage input end, the positive input end of the operational amplifier A2 is respectively and electrically connected with the other end of the resistor R1 and the drain electrode of the MOS tube Mn1, the output end of the operational amplifier A2 is electrically connected with the grid electrode of the MOS tube Mn1, and the source electrode of the MOS tube Mn1 is grounded; the current flowing through the resistor R1 is the first current.
Further, the operational amplifier A1 and/or the operational amplifier A2 includes a differential input unit, a folded cascode unit, a common source amplifying unit, a first feedback unit, and a second feedback unit;
the differential input unit comprises a first input end and a second input end, and is used for converting differential mode voltage input to the first input end and the second input end into differential mode current;
the folding common-source common-gate amplifying unit is electrically connected with the differential input unit and used for converting the differential mode current into single-ended output voltage, and a first output end of the folding common-source common-gate amplifying unit outputs the single-ended output voltage;
the common source amplifying unit is electrically connected with the first output end of the folding common source common gate amplifying unit and is used for amplifying the single-ended output voltage and outputting an amplified voltage;
the first feedback unit is electrically connected with the common-source amplifying unit and is used for feeding back the amplified voltage to the folding common-source common-gate amplifying unit, and the folding common-source common-gate amplifying unit negatively feeds back and adjusts the single-ended output voltage based on the amplified voltage;
the second feedback unit is electrically connected with the second output end of the folding common-source common-gate amplifying unit, feedback voltage is input to the differential input unit, and the differential input unit negatively feeds back and adjusts the magnitude of the differential mode current based on the feedback voltage.
Specifically, the folded cascode amplifying unit comprises a MOS transistor M4, a MOS transistor M6, a MOS transistor M8, a MOS transistor M10, a MOS transistor M5, a MOS transistor M7, a MOS transistor M9 and a MOS transistor M11;
the source electrode of the MOS tube M4 is electrically connected with the source electrode of the MOS tube M5; the grid electrode of the MOS tube M4 is electrically connected with the grid electrode of the MOS tube M5, the drain electrode of the MOS tube M6 and the drain electrode of the MOS tube M8 respectively; the drain electrode of the MOS tube M4 is electrically connected with the source electrode of the MOS tube M6; the drain electrode of the MOS tube M5 is electrically connected with the source electrode of the MOS tube M7; the grid electrode of the MOS tube M6 is electrically connected with the grid electrode of the MOS tube M7; the drain electrode of the MOS tube M7 is electrically connected with the drain electrode of the MOS tube M9; the grid electrode of the MOS tube M8 is electrically connected with the grid electrode of the MOS tube M9; the source electrode of the MOS tube M8 is electrically connected with the drain electrode of the MOS tube M10; the source electrode of the MOS tube M9 is electrically connected with the drain electrode of the MOS tube M10; the source electrode of the MOS tube M8 and the source electrode of the MOS tube M9 are electrically connected with the differential input unit; the grid electrode of the MOS tube M10 is electrically connected with the grid electrode of the MOS tube M11, and the source electrode of the MOS tube M10 and the source electrode of the MOS tube M11 are grounded;
the common source amplifying unit comprises an MOS tube M12 and an MOS tube M13, wherein the source electrode of the MOS tube M12 is electrically connected with the source electrode of the MOS tube M4, the grid electrode of the MOS tube M12 is electrically connected with the drain electrode of the MOS tube M7, the drain electrode of the MOS tube M12 is electrically connected with the drain electrode of the MOS tube M13, and the amplifying voltage is output; the grid electrode of the MOS tube M13 is electrically connected with the grid electrode of the MOS tube M10 and receives the single-ended output voltage; the source electrode of the MOS tube M13 is grounded.
The first feedback unit comprises a resistor R4 and a capacitor C2, one end of the capacitor C2 is electrically connected with the drain electrode of the M12, the other end of the capacitor C2 is electrically connected with one end of the resistor R4, and the other end of the resistor R4 is electrically connected with the grid electrode of the MOS tube M13.
The second feedback unit comprises a resistor R5 and a capacitor C3; the differential input unit comprises a MOS tube M1, a MOS tube M2 and a MOS tube M3;
one end of the resistor R5 is electrically connected with the grid electrode of the MOS tube M4, and the other end of the resistor R5 is respectively electrically connected with one end of the capacitor C3 and the grid electrode of the MOS tube M1; the source electrode of the MOS tube M1 is electrically connected with the other end of the capacitor C3 and the source electrode of the MOS tube M4 respectively; the drain electrode of the MOS tube M1 is electrically connected with the source electrode of the MOS tube M2 and the source electrode of the MOS tube M3 respectively;
the drain electrode of the MOS tube M2 is electrically connected with the source electrode of the MOS tube M8, the drain electrode of the MOS tube M3 is electrically connected with the source electrode of the MOS tube M8, and the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3 are used for outputting the differential mode current.
In an embodiment, the amplifying unit includes an operational amplifier A3 and a feedback unit, the output terminal of the operational amplifier A3 is electrically connected to the negative input terminal of the operational amplifier A3 through the feedback unit, the negative input terminal of the operational amplifier A3 is configured to input the second current, and the positive input terminal of the operational amplifier A3 is configured to input the reference voltage.
Furthermore, the feedback unit comprises a feedback resistor and a compensation capacitor, the feedback resistor is connected in parallel with the compensation capacitor, one end of the feedback resistor is electrically connected with the output end of the operational amplifier A3, and the other end of the feedback resistor is electrically connected with the negative input end of the operational amplifier A3.
In addition, the invention further comprises a reference voltage generating unit configured to provide a reference voltage to the positive input terminal of the operational amplifier A3.
Specifically, the reference voltage generating unit comprises a resistor R3 and at least one NMOS tube;
when the NMOS transistor is included, one end of the resistor R3 is respectively and electrically connected with the positive input end of the operational amplifier A3, the drain electrode of the NMOS transistor and the grid electrode of the NMOS transistor, and the source electrode of the NMOS transistor is grounded;
when more than two NMOS tubes are included, all NMOS tubes are sequentially connected in series, wherein the series connection means that the source electrode of the current NMOS tube is respectively and electrically connected with the drain electrode and the grid electrode of the next NMOS tube, and the source electrode of the last NMOS tube is grounded; one end of the resistor R3 is electrically connected with the positive input end of the operational amplifier A3, the drain electrode of the first NMOS tube and the grid electrode of the first NMOS tube respectively.
Compared with the prior art, the invention has the following beneficial effects:
firstly, two externally input voltage differences are converted into corresponding currents through a conversion unit, then the currents are converted into voltages through an amplifying unit pair, and according to ohm's law, when the two voltage differences are converted into the currents, the two voltage differences need to be divided by a resistance value, so when the two voltage differences change greatly, the corresponding current changes little, and the problem that signal distortion occurs to the output voltage finally output by the invention can be avoided; in addition, the amplifying unit amplifies the input current into voltage instead of amplifying the voltage, so that the converting unit does not need to be provided with excessive resistors, and the chip area and the thermal noise can be reduced.
And secondly, mirroring the first current through the current mirror unit, and when the current mirror unit is required to provide high gain, increasing the second current output by the current mirror unit is equivalent to performing primary amplification through the current mirror unit without excessively increasing the gain of the amplifying unit, wherein the excessive increase of the gain of the amplifying unit can lead the amplifying unit to sacrifice other performances and influence the use stability of the circuit.
Drawings
FIG. 1 is a circuit diagram of a prior art three-op amplifier;
FIG. 2 is a schematic diagram of an amplifying circuit according to the present invention;
FIG. 3 is a circuit diagram of an embodiment of an amplifying circuit of the present invention;
fig. 4 is a schematic diagram of the structure of an operational amplifier A1 according to the present invention;
FIG. 5 is a circuit diagram of an embodiment of an operational amplifier A1 of the present invention;
FIG. 6 is a schematic diagram illustrating the gain simulation of the operational amplifier A1 according to the present invention;
FIG. 7 is a schematic diagram of a gain simulation of the present invention applied to a dual-channel Ethernet power supply system;
fig. 8 is a schematic diagram of phase frequency simulation of the present invention applied in a two-way ethernet power supply system.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 2, a signal amplifying circuit for use in a two-way power over ethernet system includes
A conversion unit 1 including a first voltage input terminal and a second voltage input terminal for converting a difference between a voltage input from the first voltage input terminal and a voltage input from the second voltage input terminal into a first current;
a current mirror unit 2 electrically connected to the conversion unit 1, for mirroring the first current and outputting a second current;
an amplifying unit 3 electrically connected to the mirroring unit 2 for converting the second current into an output voltage Uo;
a reference voltage generating unit 4 for supplying a reference voltage to one input terminal of the amplifying unit 3.
In actual use, two externally input voltage differences are converted into corresponding currents through the conversion unit 1, then the currents are converted into voltages through the amplification unit 3, and according to ohm's law, when the two voltage differences are converted into currents, the two voltage differences need to be divided by a resistance value, so when the two voltage differences change greatly, the corresponding current changes little, and the problem that signal distortion occurs to the finally output voltage can be avoided;
secondly, the first current is mirrored through the current mirror unit 2, when the current mirror unit 2 is required to provide a very high gain, the second current output by the current mirror unit 2 can be increased, which is equivalent to one-time amplification through the current mirror unit 2, but the gain of the amplifying unit 3 is excessively increased, and the excessive increase of the gain of the amplifying unit 3 can lead the amplifying unit to sacrifice other performances and affect the use stability of the circuit.
Specifically, as shown in fig. 3, the conversion unit 1 includes an operational amplifier A1, an operational amplifier A2, a MOS transistor Mn1, a MOS transistor Mp3, and a resistor R1; the current mirror unit 2 comprises a MOS tube Mp1 and a MOS tube Mp2;
the negative input end of the operational amplifier A1 is a first voltage input end, and the positive input end of the operational amplifier A1 is electrically connected with one end of the resistor R1, the drain electrode of the MOS tube MP3, the grid electrode of the MOS tube MP3 and the grid electrode of the MOS tube MP4 respectively; the source electrode of the MOS tube MP3 is respectively and electrically connected with the drain electrode of the MOS tube MP1, the grid electrode of the MOS tube MP2 and the output end of the operational amplifier A1; the source electrode of the MOS tube MP1 is electrically connected with the source electrode of the MOS tube MP2; the drain electrode of the MOS tube MP2 is electrically connected with the source electrode of the MOS tube MP4, the drain electrode of the MOS tube MP4 is electrically connected with the amplifying unit 3, and a second current is output;
the negative input end of the operational amplifier A2 is a second voltage input end, the positive input end of the operational amplifier A2 is respectively and electrically connected with the other end of the resistor R1 and the drain electrode of the MOS tube Mn1, the output end of the operational amplifier A2 is electrically connected with the grid electrode of the MOS tube Mn1, and the source electrode of the MOS tube Mn1 is grounded; the current flowing through the resistor R1 is a first current.
When in actual use, the source electrode of the MOS tube MP1 is connected with a working power supply; the voltage output by the two-way Ethernet power supply system is respectively connected to the negative input end of the operational amplifier A1 and the negative input end of the operational amplifier A2; assuming that the voltage input by the negative input terminal of the operational amplifier A1 is Ui1 and the voltage input by the negative input terminal of the operational amplifier A2 is Ui2, the voltage of the node a in fig. 3 is Uil, the voltage of the node B is Ui2, and the first current is (Ui 1-Ui 2)/R1; assuming that the gain of the current mirror unit 2 is m, the second current is m×1-Ui 2/R1.
In fig. 3, the amplifying unit 3 includes an operational amplifier A3 and a feedback unit 30, the output terminal of the operational amplifier A3 is electrically connected to the negative input terminal of the operational amplifier A3 through the feedback unit 30, the negative input terminal of the operational amplifier A3 is configured to input the second current, and the positive input terminal of the operational amplifier A3 is configured to input the reference voltage.
The feedback unit 30 includes a feedback resistor R2 and a compensation capacitor C1, the feedback resistor R2 is connected in parallel with the compensation capacitor C1, one end of the feedback resistor R2 is electrically connected with the output end of the operational amplifier A3, and the other end of the feedback resistor R2 is electrically connected with the negative input end of the operational amplifier A3.
In actual use, when the second current is m (Ui 1-Ui 2)/R1, the output voltage Uo output by the amplifying unit 3 is R3 x m (Ui 1-Ui 2)/R1. In addition, by introducing the compensation capacitor C1 into the feedback unit 30, the loop gain transfer function can be made to approach zero, which is beneficial to improving the use stability of the invention. In addition, the calculation formula of the output voltage output from the amplifying unit 3 can be obtained, and the output voltage Uo does not conflict with the voltage input by the negative input end of the operational amplifier A1 and the voltage input by the negative input end of the operational amplifier A2, that is, the output voltage Uo of the invention is irrelevant to the voltage Ui1 and the voltage Ui 2.
For the reference voltage generating unit 4 shown in fig. 2, in the present embodiment, the reference voltage generating unit 4 includes a resistor R3 and at least one NMOS transistor;
when the NMOS transistor is included, one end of a resistor R3 is respectively and electrically connected with the positive input end of the operational amplifier A3, the drain electrode of the NMOS transistor and the grid electrode of the NMOS transistor, and the source electrode of the NMOS transistor is grounded;
when more than two NMOS tubes are included, all NMOS tubes are sequentially connected in series, wherein the series connection means that the source electrode of the current NMOS tube is respectively and electrically connected with the drain electrode and the grid electrode of the next NMOS tube, and the source electrode of the last NMOS tube is grounded; one end of the resistor R3 is respectively and electrically connected with the positive input end of the operational amplifier A3, the drain electrode of the first NMOS tube and the grid electrode of the first NMOS tube.
In the reference voltage generating unit 4 shown in fig. 3, the reference voltage generating unit 4 includes two NMOS transistors, namely, an NMOS transistor Mn2 and an NMOS transistor Mn3, the drain of the NMOS transistor Mn2 is electrically connected to the positive input terminal of the operational amplifier A3, and in this embodiment, when the voltage VDD is input to the resistor R3, the voltage input to the positive input terminal of the operational amplifier A3 is about 1/2 VDD.
For the operational amplifier A1 and the operational amplifier A2 shown in fig. 3, the most important index is the gain, and when the accuracy requirement of 0.01% of the output accuracy is met, the gain of the operational amplifier A2 is 80dB.
In order to achieve the gain requirements of the operational amplifier A1 and the operational amplifier A2, as shown in fig. 4, in this embodiment, the operational amplifier A1 and the operational amplifier A2 each include a differential input unit 10, a folded cascode unit 11, a common-source amplifying unit 12, a first feedback unit 13, and a second feedback unit 14;
the differential input unit 10 includes a first input terminal I1 and a second input terminal I2 for converting a differential mode voltage input to the first input terminal I1 and the second input terminal I2 into a differential mode current;
the folding common-source common-gate amplifying unit 11 is electrically connected with the differential input unit 10 and converts the differential mode current into single-ended output voltage, and a first output end of the folding common-source common-gate amplifying unit 11 outputs the single-ended output voltage;
the common source amplifying unit 12 is electrically connected with the folding common source common gate amplifying unit 11 and is used for amplifying the single-ended output voltage and outputting the amplified voltage;
the first feedback unit 13 is electrically connected with the common-source amplifying unit 12 and is used for feeding back the amplified voltage to the folded common-source common-gate amplifying unit 11, and the folded common-source common-gate amplifying unit 11 adjusts the single-ended output voltage based on negative feedback of the amplified voltage;
the second feedback unit 14 is electrically connected to the second output terminal of the folded cascode amplifying unit 11, inputs a feedback voltage to the differential input unit 10, and the differential input unit 10 negatively feedback adjusts the magnitude of the differential mode current based on the feedback voltage.
Specifically, referring to fig. 5, the folded cascode amplifying unit 11 includes a MOS transistor M4, a MOS transistor M6, a MOS transistor M8, a MOS transistor M10, a MOS transistor M5, a MOS transistor M7, a MOS transistor M9, and a MOS transistor M11;
the source electrode of the MOS tube M4 is electrically connected with the source electrode of the MOS tube M5; the grid electrode of the MOS tube M4 is respectively and electrically connected with the grid electrode of the MOS tube M5, the drain electrode of the MOS tube M6 and the drain electrode of the MOS tube M8; the drain electrode of the MOS tube M4 is electrically connected with the source electrode of the MOS tube M6; the drain electrode of the MOS tube M5 is electrically connected with the source electrode of the MOS tube M7; the grid electrode of the MOS tube M6 is electrically connected with the grid electrode of the MOS tube M7; the drain electrode of the MOS tube M7 is electrically connected with the drain electrode of the MOS tube M9; the grid electrode of the MOS tube M8 is electrically connected with the grid electrode of the MOS tube M9; the source electrode of the MOS tube M8 is electrically connected with the drain electrode of the MOS tube M10; the source electrode of the MOS tube M9 is electrically connected with the drain electrode of the MOS tube M10; the source electrode of the MOS tube M8 and the source electrode of the MOS tube M9 are electrically connected with the differential input unit; the grid electrode of the MOS tube M10 is electrically connected with the grid electrode of the MOS tube M11, and the source electrode of the MOS tube M10 and the source electrode of the MOS tube M11 are grounded;
the common source amplifying unit 12 comprises an MOS tube M12 and an MOS tube M13, wherein the source electrode of the MOS tube M12 is electrically connected with the source electrode of the MOS tube M4, the grid electrode of the MOS tube M12 is electrically connected with the drain electrode of the MOS tube M7, the drain electrode of the MOS tube M12 is electrically connected with the drain electrode of the MOS tube M13, and amplified voltage is output; the grid electrode of the MOS tube M13 is electrically connected with the grid electrode of the MOS tube M10 and receives single-ended output voltage; the source electrode of the MOS tube M13 is grounded.
The first feedback unit 13 includes a resistor R4 and a capacitor C2, one end of the capacitor C2 is electrically connected with the drain electrode of the M12, the other end of the capacitor C2 is electrically connected with one end of the resistor R4, and the other end of the resistor R4 is electrically connected with the gate electrode of the MOS transistor M13. In practical use, good transient response can be obtained through the resistor R4 and the capacitor C2
Wherein the second feedback unit 14 comprises a resistor R5 and a capacitor C3; the differential input unit 10 comprises a MOS tube M1, a MOS tube M2 and a MOS tube M3;
one end of a resistor R5 is electrically connected with the grid electrode of the MOS tube M4, and the other end of the resistor R5 is respectively electrically connected with one end of a capacitor C3 and the grid electrode of the MOS tube M1; the source electrode of the MOS tube M1 is respectively and electrically connected with the other end of the capacitor C3 and the source electrode of the MOS tube M4; the drain electrode of the MOS tube M1 is electrically connected with the source electrode of the MOS tube M2 and the source electrode of the MOS tube M3 respectively;
the drain electrode of the MOS tube M2 is electrically connected with the source electrode of the MOS tube M8, the drain electrode of the MOS tube M3 is electrically connected with the source electrode of the MOS tube M8, and the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3 are used for outputting differential mode current.
In this embodiment, the working principle of the circuit shown in fig. 5 is as follows: the grid electrode of the MOS tube M2 and the grid electrode of the MOS tube M3 are respectively two input ends and are respectively used for inputting a differential signal Inp and a differential signal inn, the MOS tube M1 is used as a load of the differential input unit 10, the grid bias voltage of the MOS tube M1 is determined by the voltage of the second output end of the folding common-source common-gate amplifying unit 11, namely an X node, the voltage of the X node is transmitted to the grid electrode of the MOS tube M1 through a resistor R5, and the MOS tube M1 adjusts the drain electrode output current of the MOS tube M2 and the drain electrode output current of the MOS tube M3 based on the voltage negative feedback of the X node;
the MOS tube M4-M11 form a telescopic amplifying stage, which is used for amplifying the drain output current of the MOS tube M2 and the drain output current of the MOS tube M3 and outputting single-ended output voltage through the drain of the MOS tube M9;
the MOS tube M12 amplifies the single-ended output voltage, and outputs the amplified voltage through the drain electrode of the MOS tube M12; the amplified voltage is input to the grid electrode of the MOS tube M13, the grid electrode of the MOS tube M10 and the grid electrode of the MOS tube M11 through the capacitor C2 and the resistor R4 and used for stabilizing the amplified voltage and the discharge current, the folded common-source common-gate amplifying unit adjusts the voltage of the second output end based on the amplified voltage so as to change the grid bias voltage of the MOS tube M1, the adjusting time of the folded common-source common-gate amplifying unit is determined by the multiplication value of the resistance value of the resistor R4 and the capacitance value of the capacitor C2, and the smaller the multiplication value is, the faster the adjusting speed is.
In the two-way power over ethernet system, because the signal amplitude of the signal input by the signal amplifying circuit is smaller, if the current flowing through the MOS transistor M10 and the current flowing through the MOS transistor M11 are directly biased, it is necessary to ensure that the MOS transistor M10 and the MOS transistor M11 always operate in a saturated state, and in this case, if the common mode bias, that is, the differential signal Inp and the differential signal Inn shake, the MOS transistor M10 and the MOS transistor M11 directly enter a linear region, so that the input and output range of the operational amplifier itself is narrowed, that is, the gain of the operational amplifier is reduced. The drain voltage of the MOS tube M8 is used as the bias voltage of the second feedback unit 14, so that the magnitude of the bias voltage can be adjusted according to the change of the common mode current, and the use power consumption of the circuit can be reduced.
In addition, when the first feedback unit 13 is faster than the second feedback unit 14, the second feedback unit starts to operate.
Referring to fig. 6, the gain of the operational amplifier A1 of the present invention is simulated, and it can be found that the gain tail of the operational amplifier Q1 is 80.2dB, and the requirement of output accuracy can be satisfied.
Referring to fig. 7 and 8, the gain of the present invention reaches 27.4dB when the present invention is applied in a two-way power over ethernet system.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims (10)

1. A signal amplifying circuit for use in a two-way power over ethernet system, comprising
A conversion unit including a first voltage input terminal and a second voltage input terminal for converting a difference between a voltage input from the first voltage input terminal and a voltage input from the second voltage input terminal into a first current;
the current mirror unit is electrically connected with the conversion unit and is used for mirroring the first current and outputting a second current;
and the amplifying unit is electrically connected with the mirror image unit and is used for converting the second current into output voltage.
2. The signal amplifying circuit for use in a two-way power over ethernet system according to claim 1, wherein the switching unit comprises an operational amplifier A1, an operational amplifier A2, a MOS transistor Mn1, a MOS transistor Mp3, and a resistor R1; the current mirror unit comprises a MOS tube Mp1 and a MOS tube Mp2;
the negative input end of the operational amplifier A1 is the first voltage input end, and the positive input end of the operational amplifier A1 is electrically connected with one end of the resistor R1, the drain electrode of the MOS tube MP3, the grid electrode of the MOS tube MP3 and the grid electrode of the MOS tube MP4 respectively; the source electrode of the MOS tube MP3 is respectively and electrically connected with the drain electrode of the MOS tube MP1, the grid electrode of the MOS tube MP2 and the output end of the operational amplifier A1; the source electrode of the MOS tube MP1 is electrically connected with the source electrode of the MOS tube MP2; the drain electrode of the MOS tube MP2 is electrically connected with the source electrode of the MOS tube MP4, the drain electrode of the MOS tube MP4 is electrically connected with the amplifying unit, and the second current is output;
the negative input end of the operational amplifier A2 is the second voltage input end, the positive input end of the operational amplifier A2 is respectively and electrically connected with the other end of the resistor R1 and the drain electrode of the MOS tube Mn1, the output end of the operational amplifier A2 is electrically connected with the grid electrode of the MOS tube Mn1, and the source electrode of the MOS tube Mn1 is grounded; the current flowing through the resistor R1 is the first current.
3. A signal amplifying circuit for use in a two-way power over ethernet system according to claim 2, wherein the operational amplifier A1 and/or the operational amplifier A2 comprises a differential input unit, a folded cascode unit, a common source amplifying unit, a first feedback unit and a second feedback unit;
the differential input unit comprises a first input end and a second input end, and is used for converting differential mode voltage input to the first input end and the second input end into differential mode current;
the folding common-source common-gate amplifying unit is electrically connected with the differential input unit and used for converting the differential mode current into single-ended output voltage, and a first output end of the folding common-source common-gate amplifying unit outputs the single-ended output voltage;
the common source amplifying unit is electrically connected with the first output end of the folding common source common gate amplifying unit and is used for amplifying the single-ended output voltage and outputting an amplified voltage;
the first feedback unit is electrically connected with the common-source amplifying unit and is used for feeding back the amplified voltage to the folding common-source common-gate amplifying unit, and the folding common-source common-gate amplifying unit negatively feeds back and adjusts the single-ended output voltage based on the amplified voltage;
the second feedback unit is electrically connected with the second output end of the folding common-source common-gate amplifying unit, feedback voltage is input to the differential input unit, and the differential input unit negatively feeds back and adjusts the magnitude of the differential mode current based on the feedback voltage.
4. The signal amplifying circuit for use in a two-way power over ethernet system as in claim 3, wherein the folded cascode amplifying unit comprises a MOS transistor M4, a MOS transistor M6, a MOS transistor M8, a MOS transistor M10, a MOS transistor M5, a MOS transistor M7, a MOS transistor M9, and a MOS transistor M11;
the source electrode of the MOS tube M4 is electrically connected with the source electrode of the MOS tube M5; the grid electrode of the MOS tube M4 is electrically connected with the grid electrode of the MOS tube M5, the drain electrode of the MOS tube M6 and the drain electrode of the MOS tube M8 respectively; the drain electrode of the MOS tube M4 is electrically connected with the source electrode of the MOS tube M6; the drain electrode of the MOS tube M5 is electrically connected with the source electrode of the MOS tube M7; the grid electrode of the MOS tube M6 is electrically connected with the grid electrode of the MOS tube M7; the drain electrode of the MOS tube M7 is electrically connected with the drain electrode of the MOS tube M9; the grid electrode of the MOS tube M8 is electrically connected with the grid electrode of the MOS tube M9; the source electrode of the MOS tube M8 is electrically connected with the drain electrode of the MOS tube M10; the source electrode of the MOS tube M9 is electrically connected with the drain electrode of the MOS tube M10; the source electrode of the MOS tube M8 and the source electrode of the MOS tube M9 are electrically connected with the differential input unit; the grid electrode of the MOS tube M10 is electrically connected with the grid electrode of the MOS tube M11, and the source electrode of the MOS tube M10 and the source electrode of the MOS tube M11 are grounded;
the common source amplifying unit comprises an MOS tube M12 and an MOS tube M13, wherein the source electrode of the MOS tube M12 is electrically connected with the source electrode of the MOS tube M4, the grid electrode of the MOS tube M12 is electrically connected with the drain electrode of the MOS tube M7, the drain electrode of the MOS tube M12 is electrically connected with the drain electrode of the MOS tube M13, and the amplifying voltage is output; the grid electrode of the MOS tube M13 is electrically connected with the grid electrode of the MOS tube M10 and receives the single-ended output voltage; the source electrode of the MOS tube M13 is grounded.
5. The signal amplifying circuit for use in a two-way ethernet power sourcing system as defined in claim 4, wherein the first feedback unit comprises a resistor R4 and a capacitor C2, one end of the capacitor C2 is electrically connected to the drain of the M12, the other end of the capacitor C2 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to the gate of the MOS transistor M13.
6. The signal amplifying circuit for use in a two-way power over ethernet system according to claim 4, wherein said second feedback unit comprises a resistor R5 and a capacitor C3; the differential input unit comprises a MOS tube M1, a MOS tube M2 and a MOS tube M3;
one end of the resistor R5 is electrically connected with the grid electrode of the MOS tube M4, and the other end of the resistor R5 is respectively electrically connected with one end of the capacitor C3 and the grid electrode of the MOS tube M1; the source electrode of the MOS tube M1 is electrically connected with the other end of the capacitor C3 and the source electrode of the MOS tube M4 respectively; the drain electrode of the MOS tube M1 is electrically connected with the source electrode of the MOS tube M2 and the source electrode of the MOS tube M3 respectively;
the drain electrode of the MOS tube M2 is electrically connected with the source electrode of the MOS tube M8, the drain electrode of the MOS tube M3 is electrically connected with the source electrode of the MOS tube M8, and the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3 are used for outputting the differential mode current.
7. A signal amplifying circuit according to any of claims 1-6, wherein the amplifying unit comprises an operational amplifier A3 and a feedback unit, the output of the operational amplifier A3 is electrically connected to the negative input of the operational amplifier A3 through the feedback unit, the negative input of the operational amplifier A3 is configured to input the second current, and the positive input of the operational amplifier A3 is configured to input a reference voltage.
8. The signal amplifying circuit according to claim 7, wherein the feedback unit comprises a feedback resistor and a compensation capacitor, the feedback resistor is connected in parallel with the compensation capacitor, one end of the feedback resistor is electrically connected to the output terminal of the operational amplifier A3, and the other end of the feedback resistor is electrically connected to the negative input terminal of the operational amplifier A3.
9. The signal amplifying circuit for use in a two-way power over ethernet system according to claim 7, further comprising a reference voltage generating unit configured to provide a reference voltage to a positive input of said operational amplifier A3.
10. The signal amplifying circuit for use in a two-way power over ethernet system according to claim 9, wherein said reference voltage generating unit comprises a resistor R3 and at least one NMOS tube;
when the NMOS transistor is included, one end of the resistor R3 is respectively and electrically connected with the positive input end of the operational amplifier A3, the drain electrode of the NMOS transistor and the grid electrode of the NMOS transistor, and the source electrode of the NMOS transistor is grounded;
when more than two NMOS tubes are included, all NMOS tubes are sequentially connected in series, wherein the series connection means that the source electrode of the current NMOS tube is respectively and electrically connected with the drain electrode and the grid electrode of the next NMOS tube, and the source electrode of the last NMOS tube is grounded; one end of the resistor R3 is electrically connected with the positive input end of the operational amplifier A3, the drain electrode of the first NMOS tube and the grid electrode of the first NMOS tube respectively.
CN202310065801.5A 2023-01-16 2023-01-16 Signal amplifying circuit for two-way Ethernet power supply system Active CN116054752B (en)

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