CN116049090A - Chip initialization data storage method and chip initialization method - Google Patents
Chip initialization data storage method and chip initialization method Download PDFInfo
- Publication number
- CN116049090A CN116049090A CN202211725125.1A CN202211725125A CN116049090A CN 116049090 A CN116049090 A CN 116049090A CN 202211725125 A CN202211725125 A CN 202211725125A CN 116049090 A CN116049090 A CN 116049090A
- Authority
- CN
- China
- Prior art keywords
- data
- chip
- initialization
- data storage
- external memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000013500 data storage Methods 0.000 title claims abstract description 23
- 238000011423 initialization method Methods 0.000 title claims abstract description 10
- 230000015654 memory Effects 0.000 claims abstract description 34
- 238000004891 communication Methods 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000003068 static effect Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Software Systems (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a chip initialization data storage method and a chip initialization method, wherein the chip initialization data storage method comprises the following steps: the method comprises the steps of storing chip initialization data in an external memory, wherein the external memory is in communication connection with the chip, and a data structure of the data comprises a total information sequence, a single discontinuous register configuration information sequence, a continuous address space configuration information sequence and an end identifier. The invention can realize differential storage, and has simple structure and reduced hardware cost.
Description
Technical Field
The invention belongs to the technical field of data storage, and particularly relates to a chip initialization data storage method and a chip initialization method.
Background
For one SOC (System On Chip) chip, various application scenes exist, and the chip needs to be configured differently according to different application scenes. These configurations are typically performed after the chip is powered up and before normal operation, which we call chip initialization.
For a complex SOC chip, there are many modules with registers to be configured, and some modules with firmware to be updated. The memory addresses of the registers are continuous and discontinuous, and firmware is generally stored in a certain memory and is continuous. How to store these data and then configure them into the chip at power-up is an urgent problem to be solved.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a chip initialization data storage method and a chip initialization method, which can store data more flexibly and differentially.
The aim of the invention is achieved by the following technical scheme:
a method of chip initialization data storage, the method comprising:
the method comprises the steps of storing chip initialization data in an external memory, wherein the external memory is in communication connection with the chip, and a data structure of the data comprises a total information sequence, a single discontinuous register configuration information sequence, a continuous address space configuration information sequence and an end identifier.
Further, the total information sequence includes total information of the data in the external memory.
Further, the total information of the data comprises an initialization mark, user-defined information, control information and check codes.
Further, the initialization mark comprises a sequence type and user-defined information.
Further, the control information includes a total number of bytes of valid data.
Further, the single discrete register configuration information sequence includes a sequence type, address information, and data information.
Further, the continuous address space configuration information sequence includes a sequence type, a start address, a data length, and a data field.
Further, the external memory includes a charged erasable programmable read-only memory.
In another aspect, the present invention further provides a method for initializing a chip, where the method includes:
after the chip is powered on and reset is released each time, reading the data stored by any one of the chip initialization data storage methods;
data is configured into the various modules of the chip.
Further, the chip is connected with the external memory through the I2C communication protocol by the data reading module arranged in the chip, the data reading module analyzes the data according to a preset data format after reading the data in the external memory, and the analyzed data is written into a register or a static random access memory corresponding to the peripheral device until all the data are read to finish the chip initialization;
and when the continuous address space configuration information sequence is read, other addresses except the initial address are automatically generated inside the chip.
The invention has the beneficial effects that:
(1) The invention stores the data in the external memory, can realize differential storage, namely different application scenes, only needs to write different configuration data into the external memory, does not need to modify the chip, and can realize that one chip is suitable for various applications.
(2) According to the invention, data transmission is carried out between the external memory and the main chip through the I2C protocol, the communication protocol is simple, and the system complexity is low.
(3) The single discontinuous register configuration information sequence corresponds to one address to one data, has no other redundant bytes, has simple and efficient data storage, and is convenient for hardware analysis.
(4) The continuous address space configuration information sequence of the invention has one address corresponding to a plurality of data, and the data structure is very efficient for configuring registers or memories of the continuous address space. The memory space of the external memory can be saved because only the first address is needed to be stored and the interior of the other address chips can be automatically generated; when data is read from the external memory, transmission time can be saved and faster transmission can be realized because the address field is not required to be read every time.
Drawings
FIG. 1 is a diagram of an SOC chip system architecture with external memory provided by an embodiment of the present invention;
fig. 2 is a schematic flow chart of a chip initialization method according to an embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
For a complex SOC chip, there are many modules with registers to be configured, and some modules with firmware to be updated. The memory addresses of the registers are continuous and discontinuous, and firmware is generally stored in a certain memory and is continuous. How to store these data and then configure them into the chip at power-up is an urgent problem to be solved.
In order to solve the above technical problems, the following embodiments of the chip initialization data storage method and the chip initialization method of the present invention are proposed.
Example 1
Taking the SOC chip as an example, in order to be able to store data more flexibly and differentially, this embodiment proposes to store data in an EEPROM chip (EEPROM: electrically Erasable Programmable Read Only Memory, charged erasable programmable read only memory).
Referring to fig. 1, fig. 1 shows a SOC system-on-chip architecture with external memory according to the present embodiment, in which an AHB bus is used to connect the modules. Inside the chip, ini_ blk (initial block) is used as a data reading module, is specially used for reading data from the EEPROM, and is configured into each module of the chip through the AHB bus.
In this embodiment, the data stored in the EEPROM chip is encoded and stored according to the following format: information sequence
The Information sequence fixes 4 dwords to be 4x4 bytes in length, and the format of the Information sequence of this embodiment is shown in table 1:
table 1 the format of the Information sequence format S0-code is shown in Table 2:
table 2 format of S0-code
Cpu boot, which means that after the data of the epom is processed, the CPU needs to be evacuated for resetting;
crc _en: indicating that the crc check is to be performed on the entire data.
Length represents the total byte number of the entire eporom valid data.
The format of the single Dword initialization sequence S1 is shown in table 3:
TABLE 3 format of sequence S1
Where code=00 b indicates the type of sequence S1, addr indicates an address, and Data indicates Data. The format of the Burst Dword initialization sequence S2 is shown in table 4:
TABLE 4 format of sequence S2
Where code=01b denotes the type of the sequence S2, addr denotes an address, length denotes a Data length, and Data denotes Data.
The end flag initialization sequence S3 is shown in table 5:
table 5 format of the end tag sequence S3
In the above-defined data structure, the information sequence stores the total information of the data in the EEPROM, S1, S2, stores specific configuration information, and S3 is the end identifier.
Code=2' b00 of the S1 sequence is used to configure a single discrete register, so its data structure contains only address and data; there may be multiple S1 sequences in the EEPROM;
code=2' b01 of the S2 sequence is used to configure a continuous address space, such as SRAM, which is allocated over a continuous address space. The S2 sequence therefore contains a start address, a data length, and a data field (the data field is made up of a number of 32 bits of data, a specific number being specified by the data length field). There may be multiple S2 sequences in the EEPROM.
The chip initialization data storage method provided by the embodiment stores data in the EEPROM, can realize differential storage, namely different application scenes, only needs to write different configuration data into the EEPROM, does not need to modify the chip, and can realize that one chip is suitable for various applications. And data transmission is carried out between the EEPROM and the main chip through an I2C protocol, the communication protocol is simple, and the system complexity is low. One address of the single discontinuous register configuration information sequence corresponds to one data, no other redundant bytes exist, the data storage is simple and efficient, and the hardware analysis is convenient. The sequential address space configuration information sequence has one address corresponding to a plurality of data, and the data structure is very efficient for configuring registers or memories of the sequential address space. The memory space of the EEPROM can be saved as only the first address is needed to be stored and the interior of the other address chips can be automatically generated; when data is read from the EEPROM, the transfer time can be saved and faster transfer can be achieved since the address field does not need to be read every time.
Example 2
The embodiment provides a chip initialization method, which is implemented based on the chip initialization data storage method provided by the previous embodiment.
Referring to fig. 2, as shown in fig. 2, a flow chart of a chip initialization method provided in this embodiment is shown, and the method specifically includes the following steps:
step one: and after the chip is powered on each time and reset is released, the stored data is read.
Specifically, the chip is connected with the external memory through an I2C communication protocol by an ini_blk module disposed inside the chip, and the ini_blk module reads data in the EEPROM byte by byte, and then parses the data according to the data format described above.
Step two: data is configured into the various modules of the chip.
Specifically, the chip writes the parsed data into the register or the static random access memory of the corresponding peripheral through the bus until all the data are read out to complete the chip initialization.
It should be noted that, when the continuous address space configuration information sequence is read, other addresses than the start address are automatically generated inside the chip.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A method for chip initialization data storage, the method comprising:
the method comprises the steps of storing chip initialization data in an external memory, wherein the external memory is in communication connection with the chip, and a data structure of the data comprises a total information sequence, a single discontinuous register configuration information sequence, a continuous address space configuration information sequence and an end identifier.
2. The chip initialization data storage method of claim 1, wherein the total information sequence includes total information of data in an external memory.
3. The chip initialization data storage method according to claim 2, wherein the total information of the data includes an initialization flag, user-defined information, control information, and a check code.
4. The chip initialization data storage method of claim 3, wherein the initialization tag comprises a sequence type and user-defined information.
5. The chip initialization data storage method of claim 3, wherein the control information comprises a total number of bytes of valid data.
6. The chip initialization data storage method of claim 1, wherein the single discrete register configuration information sequence comprises a sequence type, address information, and data information.
7. The chip-initialization data storage method of claim 1, in which the contiguous address space configuration information sequence comprises a sequence type, a start address, a data length, and a data field.
8. The chip initialization data storage method of claim 7, wherein the external memory comprises a charged erasable programmable read only memory.
9. A method for initializing a chip, the method comprising:
after the chip is powered on and reset is released each time, reading the data stored by the chip initialization data storage method according to any one of claims 1 to 8;
data is configured into the various modules of the chip.
10. The chip initialization method according to claim 9, wherein the chip is connected with the external memory through an I2C communication protocol by a data reading module arranged inside the chip, the data reading module analyzes the data according to a preset data format after reading the data in the external memory, and the analyzed data is written into a register or a static random access memory of a corresponding peripheral until all the data are read out to complete chip initialization;
and when the continuous address space configuration information sequence is read, other addresses except the initial address are automatically generated inside the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211725125.1A CN116049090A (en) | 2022-12-30 | 2022-12-30 | Chip initialization data storage method and chip initialization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211725125.1A CN116049090A (en) | 2022-12-30 | 2022-12-30 | Chip initialization data storage method and chip initialization method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116049090A true CN116049090A (en) | 2023-05-02 |
Family
ID=86128857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211725125.1A Pending CN116049090A (en) | 2022-12-30 | 2022-12-30 | Chip initialization data storage method and chip initialization method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116049090A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117742805A (en) * | 2024-02-21 | 2024-03-22 | 井芯微电子技术(天津)有限公司 | Chip initialization method and device |
| CN117742805B (en) * | 2024-02-21 | 2024-05-31 | 井芯微电子技术(天津)有限公司 | Chip initialization method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6640262B1 (en) * | 1999-12-20 | 2003-10-28 | 3Com Corporation | Method and apparatus for automatically configuring a configurable integrated circuit |
| CN101561750A (en) * | 2008-12-25 | 2009-10-21 | 上海贝岭股份有限公司 | An electric meter SOC system and initialization method thereof |
| CN103677745A (en) * | 2013-12-10 | 2014-03-26 | 中国船舶重工集团公司第七0九研究所 | Method for writing and reading equipment identification in Loongson mainboard |
| CN111949597A (en) * | 2020-07-02 | 2020-11-17 | 江苏华创微系统有限公司 | Internal register structure for on-chip power-on initialization |
| CN112131172A (en) * | 2020-08-28 | 2020-12-25 | 中国船舶重工集团公司第七0九研究所 | PCIe equipment chip initialization method for reducing time delay |
-
2022
- 2022-12-30 CN CN202211725125.1A patent/CN116049090A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6640262B1 (en) * | 1999-12-20 | 2003-10-28 | 3Com Corporation | Method and apparatus for automatically configuring a configurable integrated circuit |
| CN101561750A (en) * | 2008-12-25 | 2009-10-21 | 上海贝岭股份有限公司 | An electric meter SOC system and initialization method thereof |
| CN103677745A (en) * | 2013-12-10 | 2014-03-26 | 中国船舶重工集团公司第七0九研究所 | Method for writing and reading equipment identification in Loongson mainboard |
| CN111949597A (en) * | 2020-07-02 | 2020-11-17 | 江苏华创微系统有限公司 | Internal register structure for on-chip power-on initialization |
| CN112131172A (en) * | 2020-08-28 | 2020-12-25 | 中国船舶重工集团公司第七0九研究所 | PCIe equipment chip initialization method for reducing time delay |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117742805A (en) * | 2024-02-21 | 2024-03-22 | 井芯微电子技术(天津)有限公司 | Chip initialization method and device |
| CN117742805B (en) * | 2024-02-21 | 2024-05-31 | 井芯微电子技术(天津)有限公司 | Chip initialization method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102422271B (en) | For the multipage warning order of Nonvolatile memory system | |
| KR101507628B1 (en) | System and method for data read of a synchronous serial interface nand | |
| US8473672B2 (en) | System and method for storing data using a flexible data format | |
| US20070130397A1 (en) | System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links | |
| US20080307154A1 (en) | System and Method for Dual-Ported I2C Flash Memory | |
| JP2007535760A (en) | Masking in data processing systems with applicability to development interfaces | |
| US20080162782A1 (en) | Using Transacted Writes and Caching Mechanism to Improve Write Performance in Multi-Level Cell Flash Memory | |
| US20070106873A1 (en) | Apparatus and method for translating addresses | |
| JP4855864B2 (en) | Direct memory access controller | |
| US5928338A (en) | Method for providing temporary registers in a local bus device by reusing configuration bits otherwise unused after system reset | |
| US7216211B2 (en) | Variable sized flash memory in PCI | |
| CN116049090A (en) | Chip initialization data storage method and chip initialization method | |
| US10338843B2 (en) | Methods for moving data internally and apparatuses using the same | |
| US9009389B2 (en) | Memory management table processing method, memory controller, and memory storage apparatus | |
| US7093065B2 (en) | Random access memory initialization | |
| US6813647B2 (en) | Microcomputer system reading data from secondary storage medium when receiving upper address from outside and writing data to primary storage medium | |
| CN110489361B (en) | I3C interface circuit compatible with SRAM bus | |
| CN100386748C (en) | Method and system for chip selecting of peripheral device in singe board computer | |
| US20200151119A1 (en) | Method and apparatus for performing access control between host device and memory device | |
| EP4250093A1 (en) | Memory configuration within a data processing system | |
| US7213142B2 (en) | System and method to initialize registers with an EEPROM stored boot sequence | |
| CN116775526B (en) | Expansion device and electronic equipment | |
| KR100526547B1 (en) | Method for managing nand flash memory in terminal including dual dhip | |
| JP2007310927A (en) | Nonvolatile memory, memory controller, and nonvolatile storage device and system | |
| US20030051106A1 (en) | Multi-memory architecture and access controller therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |