CN117742805B - Chip initialization method and device - Google Patents
Chip initialization method and device Download PDFInfo
- Publication number
- CN117742805B CN117742805B CN202410190031.1A CN202410190031A CN117742805B CN 117742805 B CN117742805 B CN 117742805B CN 202410190031 A CN202410190031 A CN 202410190031A CN 117742805 B CN117742805 B CN 117742805B
- Authority
- CN
- China
- Prior art keywords
- memory
- initialization data
- loaded
- controller
- loading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000011423 initialization method Methods 0.000 title claims abstract description 16
- 230000015654 memory Effects 0.000 claims abstract description 382
- 238000000034 method Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 5
- 238000004590 computer program Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000003993 interaction Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 230000009191 jumping Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 101000741965 Homo sapiens Inactive tyrosine-protein kinase PRAG1 Proteins 0.000 description 1
- 102100038659 Inactive tyrosine-protein kinase PRAG1 Human genes 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Stored Programmes (AREA)
Abstract
The disclosure provides a chip initialization method and device. The method is applied to a chip, the chip comprises a controller and an I2C bus, and the I2C bus is used for connecting the controller and N memories, wherein N is a natural number larger than 1. The controller determines N memories to be loaded with the initialization data and a first memory to be loaded with the initialization data. The controller performs the following loading operations of the initialization data starting from the first memory: for each memory needing to be loaded with initialization data, after the loading of the respective corresponding initialization data is completed, the controller starts the link of the memory pointing to the next memory for loading the initialization data, and loads the initialization data corresponding to the memory through the next memory for loading the initialization data until the last memory completes the loading of the corresponding initialization data, so that the initialization work of the chip can be completed through a plurality of memories in a boot mode.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of computers, in particular to a chip initialization method and device.
Background
The I2C bus plays a very important role in the chip initialization phase as a base protocol bus commonly used in chips.
In the existing process of chip initialization, the I2C bus may initialize the chip in boot mode. In the boot mode, the total amount of data to be initialized and loaded is required to be matched with the capacity of a single memory, if no corresponding memory can finish the loading of the data, the initialization of the chip cannot be finished by using the boot mode, and other methods are required to be searched for to finish the initialization of the chip.
Therefore, there is a need to propose a chip initialization method to solve at least one of the above-mentioned problems.
Disclosure of Invention
The embodiment of the disclosure provides a chip initialization method and device.
In a first aspect, the present disclosure provides a chip initialization method applied to a chip, the chip including a controller and an I2C bus, the I2C bus being used to connect the controller and N memories, where N is a natural number greater than 1, including:
The controller determines N memories needing to be loaded with initialization data and a first memory loading the initialization data;
the controller starts from the first memory to execute the following loading operation of initialization data:
For each memory needing to be loaded with the initialization data, after the loading of the initialization data corresponding to each memory is completed, the controller starts a link of the memory pointing to the next memory for loading the initialization data, and loads the initialization data corresponding to the memory through the next memory for loading the initialization data until the last memory completes the loading of the corresponding initialization data.
In some optional embodiments, the memory includes a first address space and a second address space, where the first address space is used to store the initialization data corresponding to the memory, and the second address space is used to store a link of the memory to a next memory to which the initialization data is loaded.
In some alternative embodiments, for each memory to be loaded with the initialization data, the method further includes:
loading initialization data corresponding to each memory from a first address space of each memory, and
The link of the memory to the next memory to which the initialization data is loaded is opened by the second address space of the respective memory.
In some alternative embodiments, the link to the next memory to which the initialization data is loaded includes identification information and control signals of the next memory to which the initialization data is loaded.
In some alternative embodiments, the controller opens a link to the memory pointing to the next memory to which the initialization data is loaded, including:
And the controller starts a link of the memory pointing to the next memory for loading the initialization data according to the identification information and the control signal of the next memory for loading the initialization data.
In some optional embodiments, before the initializing data corresponding to the memory is loaded by the memory that loads the initializing data next, the method further includes:
The controller respectively matches the identification information of the memory to which the initialization data is loaded next pointed by the link with the identification information of the N memories;
And the controller determines the next memory for loading the initialization data pointed by the link in the N memories according to the matching result.
In some optional embodiments, before the controller determines that N memories of the initialization data need to be loaded and loads the first memory of the initialization data, the method further includes:
the controller stores the initialization data corresponding to each memory into the corresponding memory.
In some alternative embodiments, the controller determining the first of the memories to load the initialization data includes:
and the controller determines to load the first memory of the initialization data according to the pin of the chip.
In some alternative embodiments, the initialization data includes an address of at least one register and data in the register.
In a second aspect, the present disclosure provides a chip comprising a controller and an I2C bus, the I2C bus for connecting the controller and N memories, wherein N is a natural number greater than 1, wherein
The controller is configured to determine N memories needing to be loaded with initialization data and a first memory loading the initialization data;
the controller is further configured to perform the following initialization data loading operations starting from the first of the memories:
For each memory needing to be loaded with the initialization data, after the loading of the initialization data corresponding to each memory is completed, the controller starts a link of the memory pointing to the next memory for loading the initialization data, and loads the initialization data corresponding to the memory through the next memory for loading the initialization data until the last memory completes the loading of the corresponding initialization data.
The chip initialization method and device provided by the embodiment of the disclosure are applied to a chip, the chip comprises a controller and an I2C bus, and the I2C bus is used for connecting the controller and N memories, wherein N is a natural number larger than 1. The controller determines N memories to be loaded with the initialization data and a first memory to be loaded with the initialization data. The controller performs the following loading operations of the initialization data starting from the first memory: for each memory needing to be loaded with initialization data, after the loading of the respective corresponding initialization data is completed, the controller starts the link of the memory pointing to the next memory for loading the initialization data, and loads the initialization data corresponding to the memory through the next memory for loading the initialization data until the last memory completes the loading of the corresponding initialization data. According to the method and the device, the initialization data are stored in the memories, and the links of the memories pointing to the next memory are set for each memory storing the initialization data, so that after the initialization data in the first memory are loaded to the chip for processing, the loading of the initialization data can be continued by jumping to the next memory through the links until the loading work of all the initialization data is completed, and the initialization work of the chip can be completed through the memories in a boot mode.
Drawings
Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings. The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention. In the drawings:
FIG. 1 is a system architecture diagram of one embodiment of a chip initialization system according to the present disclosure;
FIG. 2 is a schematic diagram of one operational timing of an I2C bus according to the present disclosure;
FIG. 3 is a schematic diagram of a boot state machine according to the present disclosure;
FIG. 4A is a flow chart of one embodiment of a chip initialization method according to the present disclosure;
FIG. 4B is an exploded flow chart according to one embodiment of step 402 of the present disclosure;
fig. 5 is a schematic structural view of one embodiment of a chip initializing device according to the present disclosure.
Detailed Description
The present disclosure is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 illustrates an exemplary system architecture 100 to which embodiments of the chip initialization methods and apparatus of the present disclosure may be applied.
As shown in fig. 1, system architecture 100 may include a chip 101, memories 102, 103, terminal devices 104, 105, a network 106, and a server 107.
The chip 101 and the memories 102 and 103 are connected through an I2C bus, so that data interaction between the chip 101 and the memories 102 and 103 is completed. The chip 101 and the terminal devices 104 and 105 are connected in a wired or wireless manner to realize data interaction.
The network 106 is used as a medium to provide communication links between the terminal devices 104, 105 and the server 107. The network 106 may include various connection types, such as wired, wireless communication links, or fiber optic cables, among others.
A user may interact with the server 107 via the network 106 using the terminal devices 104, 105 to receive or send messages or the like. Various communication client applications may be installed on the terminal devices 104, 105, such as voice interaction type applications, video conferencing type applications, short video social type applications, web browser applications, shopping type applications, search type applications, instant messaging tools, mailbox clients, social platform software, and the like.
The terminal devices 104, 105 may be hardware or software. When the terminal devices 104, 105 are hardware, they may be various electronic devices with microphones and speakers, including but not limited to smartphones, tablet computers, electronic book readers, MP3 players (Moving Picture Experts Group Audio Layer III, dynamic video expert compression standard audio plane 3), MP4 players (Moving Picture Experts Group Audio Layer IV, dynamic video expert compression standard audio plane 4), portable computers, desktop computers, and the like. When the terminal devices 104, 105 are software, they can be installed in the above-listed electronic devices. Which may be implemented as a plurality of software or software modules, or as a single software or software module. The present invention is not particularly limited herein.
The server 107 may be hardware or software. When the server 107 is hardware, it may be implemented as a distributed server cluster composed of a plurality of servers, or may be implemented as a single server. When server 107 is software, it may be implemented as a plurality of software or software modules (e.g., to provide distributed services), or as a single software or software module. The present invention is not particularly limited herein.
In some cases, the chip initialization method provided in the present disclosure may be performed by the chip 101, specifically, may also be performed by a controller of the chip 101, for example, "the controller determines N memories to be loaded with initialization data and a first memory to be loaded with initialization data". The present disclosure is not limited in this regard.
It should be understood that the number of chips, memories, terminal devices, networks, and servers in fig. 1 are merely illustrative. There may be any number of chips, memories, terminal devices, networks, and servers, as desired for implementation.
With continued reference to FIG. 2, FIG. 2 shows a schematic diagram of one operational timing of the I2C bus according to the present disclosure;
The operation timing diagram of the I2C bus may represent a process of initializing data loading at a time.
As shown in fig. 2, slaveaddr (slave addresses) may be represented as addresses of respective memories in the present disclosure. Peradrmsb (the upper bits of the slave address) may be represented as the upper bits of the address of the respective memory. Peradrlsb (the low order bits of the slave address) may be represented as the low order bits of the memory address. ReadData, may be represented as an address space in memory that stores initialization data.
By way of example, the individual memories may be EEPROMs (electrically erasable programmable read Only memory), wherein the EEPROM's 0-byte address and 1-byte address, i.e., peradrmsb address and Peradrlsb address, together occupy 16-bit addresses, and the 0-byte address and 1-byte address may be used to collectively represent the number of registers that can be loaded in the memory, which can be loaded in a single byte mode, i.e., a 1-byte address mode, up to 255 registers. The memory can load up to 8191 registers in the double byte mode, i.e., the 2 byte address mode. And, in the initialization data loading process in the boot mode, the address of 2 bytes to 7 bytes of the memory needs to be set to 0xFF, otherwise, the initialization data loading process in the boot mode is ended.
In this disclosure, the memory may be loaded in the form of registers, each of which is made up of 8 byte addresses, where the first 4 byte addresses of a register represent the address of an internal register and the last 4 byte addresses represent the data contained in that register. The address and data are organized in either MSB (high order) or LSB (low order). This means that the most significant byte is at the low address and the least significant byte is at the high address, or vice versa. Furthermore, the address and data increment in bytes (MSB or LSB) rather than growing in byte boundaries as in normal memory.
Referring to table 1, table 1 shows a data format table of an EEPROM according to the present disclosure.
TABLE 1
Wherein PerAdr +0 may represent a 0-byte address of the EEPROM, which may be a high order of an address of the memory, perAdr +1 may represent a 1-byte address of the EEPROM, which may be a low order of an address of the memory, and PerAdr +2-byte addresses to PerAdr +7-byte addresses are set to 0xFF in the initialization data loading process. Next, registers representing the memory are started from PerAdr +8 bytes addresses, one for every 8 bytes.
With continued reference to fig. 3, fig. 3 is a schematic diagram of a boot state machine according to the present disclosure.
The Boot state machine (Boot STATE MACHINE ) is a special finite state machine (FINITE STATE MACHINE) that describes the different stages and possible state transitions during the computer system Boot process. Each phase of the Boot state machine corresponds to a particular state and can only transition to the next state after all conditions of the current state are met. In the present disclosure, a Boot state machine may be used to represent the state of different stages of the controller during the chip initialization data loading process.
The Boot state machine mainly comprises the following states:
First, IDLE state: when the chip is powered on/restarted, the controller enters an IDLE state, and if a boot mode is selected before the chip is powered on/restarted, the controller jumps to a START (START) state.
Second, START state: the controller enters an ADDR (address) state from START when the controller requests loading of data from memory for chip initialization in the START state.
Third, ADDR state: the controller determines the first memory to be loaded with initialization data in the ADDR state and then sends the address of the first memory to be loaded with initialization data.
Fourth, the PADDR (peripheral address) state, after the controller sends the address of the memory where the initialization data is first loaded, the controller enters the ADDR state again to send the PADDR of the memory, where the PADDR may refer to the address of the memory where the register in the memory where the first data is to be loaded is located.
Fifth, REC (receive) state: after the controller has transmitted the PADDR of the memory, it enters the REC state, in which the initialization data is loaded from the memory.
Sixth, STOP (STOP) state: after the controller completes the loading operation of the initialization data, the STOP state is entered, and the IDLE state is entered when the STOP signal is detected.
Seventh, RESTART state, when the initialization data needs to be loaded from the plurality of memories, each memory except the last memory to which the initialization data is loaded, after each memory has been loaded with the corresponding initialization data, the controller enters the RESTART state, specifically, a control signal may be sent to prevent the controller from entering the STOP state by pointing to the link of the next memory to which the initialization data is loaded through the memory to which the initialization data is loaded. For example, a NACK (Negative Acknowledgement, a negative feedback) message may be sent to prevent the controller from entering the STOP state, thereby causing the controller to enter the rest state, continuing to load the initialization data through the next memory that loads the initialization data.
With continued reference to fig. 4A, fig. 4A illustrates a flowchart 400 of one embodiment of a chip initialization method according to the present disclosure, the chip initialization method illustrated in fig. 4A being applicable to the chip illustrated in fig. 1. The chip includes a controller and an I2C bus, the I2C bus being used to connect the controller and the at least one memory.
The I2C (Inter-INTEGRATED CIRCUIT) bus is a serial communication interface, mainly used for connecting a microcontroller and low-speed peripherals, such as sensors, LCD drivers, EEPROM memories, etc. The I2C bus is widely used in various electronic devices, such as smart phones, tablet computers, smart home, etc.
The controller of the chip refers to a control logic unit inside the chip, and is mainly responsible for controlling and scheduling the functional modules inside the chip. The controller of the chip may be an integrated hardware circuit or may be a software program implemented by a microprocessor or microcontroller on the chip. At the hardware level, some chips may incorporate dedicated controller circuitry for managing and controlling the operation of the various functional modules on the chip. These controllers typically have specific functions and interfaces that enable communication with external devices, data storage, clock management, interrupt handling, etc. At the software level, some chips may be equipped with embedded microprocessors or microcontrollers, with control of the functional modules within the chip being achieved by software programs. These programs may be written by a chip developer, developed and debugged through programming languages and development tools.
In this embodiment, the memory may be an EEPROM memory, and N is a natural number greater than 1.
The process 400 includes the steps of:
In step 401, the controller determines N memories to be loaded with initialization data and a first memory to be loaded with initialization data.
Here, the initialization data may refer to data that needs to be loaded from N memories to a chip for processing in the chip initialization process.
In the initialization process of the chip, the initialization data may be stored in N memories, and part of the initialization data is stored in each memory. The controller may sequentially load the initialization data from the N memories to the chip for processing to complete the initialization operation of the chip, and the first memory to load the initialization data may refer to a first memory to load the initialization data from the N memories.
In some alternative embodiments, the first memory that the controller determines to load the initialization data may be the first memory that the controller determines to load the initialization data according to the pins of the chip. That is, for the first memory to load initialization data, the controller may retrieve the memory address from the pin of the chip.
In some alternative embodiments, the initialization data may include an address of at least one register and data in each register, that is, the initialization data may be stored in each memory in the form of a register, and thus, during the loading of the initialization data, the controller may perform processing by loading the address of the read register in each memory and corresponding data into the chip to implement the initialization of the chip.
At step 402, the controller performs a load operation of the initialization data from the first memory.
Specifically, for each memory to be loaded with initialization data, after loading of the corresponding initialization data is completed, the controller opens a link of the memory to a next memory to be loaded with initialization data, and loads the initialization data corresponding to the memory through the next memory to be loaded with initialization data until the last memory completes loading of the corresponding initialization data.
In this embodiment, after determining the address of the memory of the first loading initialization data, the controller starts loading the initialization data from the memory of the first loading initialization data, and after the initialization data of the memory of the first loading initialization data is loaded, the controller starts the link of the memory of the first loading initialization data to the memory of the second loading initialization data, then continues to load the initialization data corresponding to the memory of the second loading initialization data through the memory of the second loading initialization data, after the initialization data corresponding to the memory of the second loading initialization data is loaded, the controller continues to start the link of the memory of the second loading initialization data to the memory of the third loading initialization data, loads the initialization data corresponding to the memory of the third loading initialization data through the memory of the third loading initialization data, and ends the loading operation of the initialization data until the memory of the last loading initialization data completes the loading of the corresponding initialization data, so as to achieve the initialization of the chip.
For example, the memories to be loaded with the initialization data are the memories A, B, C, D, and each memory corresponds to the initialization data a, B, C, D, and the order in which each memory loads the initialization data may be that the initialization data is loaded through the memory a, then the initialization data is loaded through the memory C, then the initialization data is loaded through the memory D, and finally the initialization data is loaded through the memory B.
Firstly, the controller determines the address of the memory A, loads the corresponding initialization data a through the memory A, after the initialization data a is loaded, the controller starts the link of the memory A pointing to the memory C, then loads the corresponding initialization data C through the memory C, after the initialization data C is loaded, the controller starts the link of the memory C pointing to the memory D, loads the corresponding initialization data D through the memory D, after the initialization data D is loaded, the controller starts the link of the memory D pointing to the memory B, finally loads the corresponding initialization data B through the memory B, and after the initialization data B is loaded, the loading work of the initialization data is ended, which means that the initialization work of the chip is completed.
In some alternative embodiments, the memory may include a first address space for storing initialization data corresponding to the memory and a second address space for storing a link of the memory to a next memory to which the initialization data is loaded.
Wherein the first address space and the second address space may both be part of the address space of the memory, alternatively the second address space may be the last eight-bit address space of the memory, and the first address space may be other address spaces than the last eight-bit address.
In some alternative embodiments, for each memory to be loaded with initialization data, the initialization data corresponding to each memory may be loaded from the first address space of each memory, and the link of the memory pointing to the next memory to be loaded with initialization data is opened through the second address space of each memory.
For example, for memory a, initialization data a may be loaded from a first address space of memory a, and a link to memory C for memory a may be opened through a second address space of memory a.
Here, the capacities of the respective memories may be the same or different.
For example, the total capacity of the memory a may be 2KB, that is 2097152 bits, where the capacity of the first address space of the memory a may be 2097144 bits of 0-2097142 addresses, and the capacity of the first address space of the memory a may be 8 bits of 2097145-2097152 addresses. Here, at most 2097144 bits of initialization data can be stored for the memory a.
The total capacity of memory B may be 2KB, 4KB, 8KB, or the like. The total amount of initialization data that can be stored in different capacities is also different, and will not be described in detail herein.
In some alternative embodiments, the link to the next memory to which the initialization data is loaded includes identification information and control signals of the next memory to which the initialization data is loaded.
Here, each memory may be provided therein with a link to the next load initialization data, i.e., identification information and a control signal of the memory of the next load initialization data.
Wherein the identification information of the memory is used to uniquely identify the memory, and the control signal may be used to send a blocking signal to block the controller from entering a stopped state to stop the loading of the initialization data.
In some alternative embodiments, the controller opens the link of the memory to the next memory to which the initialization data is loaded, in particular, the controller opens the link of the memory to the next memory to which the initialization data is loaded according to the identification information and the control signal of the next memory.
Here, the controller may determine the next memory to which the initialization data needs to be loaded through the identification information of the memory, and prevent the controller from entering a stopped state through the control signal, so that the controller may continue to load the initialization data through the next memory to which the initialization data needs to be loaded.
In some alternative embodiments, the memory to which the initialization data is loaded may also be one memory, i.e., one memory may complete the loading of the initialization data, at which time the link of that memory to the next memory need not be opened.
In some alternative implementations, referring to fig. 4B, fig. 4B is an exploded flow chart of one embodiment of step 402 according to the present disclosure.
As shown in fig. 4B, before loading the initialization data corresponding to the memory by the next memory for loading the initialization data, steps 4021 to 4022 may be further included.
In step 4021, the controller matches the identification information of the memory to which the link points for the next load initialization data with the identification information of the N memories, respectively.
In this embodiment, specifically, the controller may send the identification information of the memory to which the link points for the next loading initialization data to each memory, and compare the identification information of each memory with the identification information of the memory to which the link points for the next loading initialization data.
In some alternative embodiments, the controller may send the identification information of the memory to which the link points for the next load initialization data to the memory to which the load of initialization data is not completed, and compare the identification information of the memory to which the load of initialization data is not completed with the identification information of the memory to which the link points for the next load initialization data.
In step 4022, the controller determines, according to the matching result, a memory to which the initialization data is to be loaded next to be pointed to by the link in the N memories.
In this embodiment, by comparing the identification information of each memory with the identification information of the memory to which the link points for the next initialization data to be loaded, a memory corresponding to the same identification information as the identification information of the memory to which the link points for the next initialization data to be loaded can be obtained, and a memory corresponding to the same identification information as the identification information of the memory to which the link points for the next initialization data to be loaded is determined as the memory to which the initialization data to be loaded is to be loaded continuously.
After determining the memory to which the initialization data is to be loaded next to be pointed to by the link, the corresponding initialization data is loaded through the memory.
In some alternative embodiments, before the controller determines N memories to be loaded with the initialization data and the first memory to be loaded with the initialization data, the controller may further store the initialization data corresponding to each memory into the corresponding memory.
It will be appreciated that, to load the initialization data from each memory, the initialization data required for the initialization should be stored in each memory before the chip is initialized, so that the initialization data stored in each memory can be loaded into the chip for processing during the chip initialization.
In some alternative embodiments, before storing the initialization data in each memory, the capacity of each memory and the total amount of the initialization data that can be stored in the memory may be determined, and the initialization data of each memory that can correspond to the memory may be stored in each memory according to the capacity of each memory.
The initialization process of the chip is explained below in connection with the boot state machine.
In this embodiment, when loading of initialization data is performed in boot mode, the controller enters a START state after the chip is powered up. Then, in the START state, the controller requests to load the initialization data so as to enable the controller to enter an ADDR state, for the memory of the first loading initialization data, the memory of the first loading initialization data is determined through a pin of the chip, then after the memory of the first loading initialization data is determined, the controller enters a PADDR state, the PADDR of the memory of the first loading initialization data is sent in the PADDR state, after the PADDR of the memory of the first loading initialization data is determined, the controller enters a REC state, in the REC state, the memory of the first loading initialization data can START to load the initialization data corresponding to the memory of the first loading initialization data from the position of the memory of the first loading initialization data pointed by the PADDR to the chip, after the memory of the first loading initialization data is loaded with the corresponding initialization data, the controller STARTs a link pointing to the memory of the next loading initialization data, then, in the PADDR state, the controller repeats the above-mentioned initialization operation of the corresponding to the memory of the next loading initialization data until the memory of the first loading initialization data is completed, and the controller enters a rest state.
Here, the manner in which the controller acquires each memory address is acquired from the identification information of the memory obtained by parsing the link of the memory to which the initialization data is loaded next in the previous memory except for the memory to which the initialization data is loaded first.
The chip initialization method provided by the embodiment of the disclosure is applied to a chip, the chip comprises a controller and an I2C bus, and the I2C bus is used for connecting the controller and N memories, wherein N is a natural number greater than 1. The controller determines N memories to be loaded with the initialization data and a first memory to be loaded with the initialization data. The controller performs the following loading operations of the initialization data starting from the first memory: for each memory needing to be loaded with initialization data, after the loading of the respective corresponding initialization data is completed, the controller starts the link of the memory pointing to the next memory for loading the initialization data, and loads the initialization data corresponding to the memory through the next memory for loading the initialization data until the last memory completes the loading of the corresponding initialization data. According to the method and the device, the initialization data are stored in the memories, and the links of the memories pointing to the memories for loading the initialization data next are set for each memory for storing the initialization data, so that after the initialization data in the first memory are loaded to the chip for processing, the initialization data can be continuously loaded by jumping to the next memory for loading the initialization data through the links until the loading work of all the initialization data is completed, and the initialization work of the chip can be completed through the memories in a boot mode.
With further reference to fig. 5, as an implementation of the method shown in the foregoing figures, the present disclosure provides an embodiment of a chip device, where the chip device includes a controller and an I2C bus, and the I2C bus is used to connect the controller and N memories, where N is a natural number greater than 1. The device embodiment corresponds to the method embodiment shown in fig. 4A, running on the controller of the chip. The device comprises: a determining unit 501 and an executing unit 502. Wherein, the determining unit 501 is configured to determine N memories to be loaded with initialization data and a first memory to be loaded with initialization data; an execution unit 502 configured to perform the following loading operation of the initialization data, starting from the first memory: for each memory needing to be loaded with initialization data, after the loading of the respective corresponding initialization data is completed, the controller starts the link of the memory pointing to the next memory for loading the initialization data, and loads the initialization data corresponding to the memory through the next memory for loading the initialization data until the last memory completes the loading of the corresponding initialization data.
In some alternative embodiments, the memory includes a first address space for storing initialization data corresponding to the memory and a second address space for storing a link of the memory to a next memory to which the initialization data is loaded.
In some alternative embodiments, execution unit 502 is further configured to:
loading initialization data corresponding to each memory from a first address space of each memory, and
The link of the memory to the next memory to which initialization data is loaded is opened by the second address space of the respective memory.
In some alternative embodiments, the link to the next memory to which the initialization data is loaded includes identification information and control signals of the next memory to which the initialization data is loaded.
In some alternative embodiments, execution unit 502 is further configured to:
And opening the link of the memory pointing to the next memory loaded with the initialization data according to the identification information and the control signal of the next memory loaded with the initialization data.
In some alternative embodiments, execution unit 502 is further configured to:
Respectively matching the identification information of the memory for loading the initialization data next pointed by the link with the identification information of the N memories;
And determining the memory of the next loading initialization data pointed by the link in the N memories according to the matching result.
In some alternative embodiments, the storage unit 503 is configured to:
and storing the initialization data corresponding to each memory into the corresponding memory.
In some alternative embodiments, the determining unit 501 is further configured to:
and determining a first memory for loading initialization data according to the pins of the chip.
In some alternative embodiments, the initialization data includes an address of at least one register and data in the register.
It should be noted that, the implementation details and technical effects of each unit in the chip device provided in the embodiments of the present disclosure may refer to the descriptions of other embodiments in the present disclosure, which are not repeated herein.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to implement a chip initialization method as shown in the embodiment and alternative implementations thereof shown in fig. 4A.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments described in the present disclosure may be implemented by means of software, or may be implemented by means of hardware. The name of the unit does not in any way constitute a limitation of the unit itself, and the determining unit may also be described as "a unit for determining N memories to be loaded with initialization data and a first memory to be loaded with initialization data", for example.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this disclosure is not limited to the specific combinations of features described above, but also covers other embodiments which may be formed by any combination of features described above or equivalents thereof without departing from the spirit of the disclosure. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).
Claims (9)
1. A chip initialization method, applied to a chip, the chip comprising a controller and an I2C bus, the I2C bus being configured to connect the controller and N memories, where N is a natural number greater than 1, the method comprising:
The controller determines N memories needing to be loaded with initialization data and a first memory loading the initialization data;
the controller starts from the first memory to execute the following loading operation of initialization data:
For each memory to be loaded with the initialization data, after completing loading of the initialization data corresponding to each memory, the controller starts a link of the memory pointing to the next memory to be loaded with the initialization data, loads the initialization data corresponding to the memory through the next memory to be loaded with the initialization data until the last memory completes loading of the corresponding initialization data, wherein the memory comprises a first address space and a second address space, the first address space is used for storing the initialization data corresponding to the memory, and the second address space is used for storing the link of the memory pointing to the next memory to be loaded with the initialization data.
2. The method of claim 1, wherein for each memory to be loaded with the initialization data, the method further comprises:
loading initialization data corresponding to each memory from a first address space of each memory, and
The linking of the memory to the next memory to which the initialization data is loaded is opened by the second address space of the respective memory.
3. The method of claim 1, wherein the link to the next memory to which the initialization data is loaded comprises identification information and control signals of the next memory to which the initialization data is loaded.
4. A method according to claim 3, wherein the controller opening a link to the memory pointing to the next memory to which the initialization data is loaded comprises:
And the controller starts a link of the memory pointing to the next memory for loading the initialization data according to the identification information and the control signal of the next memory for loading the initialization data.
5. A method according to claim 3, wherein before loading the initialization data corresponding to the memory by the memory that loads the initialization data next, the method further comprises:
The controller respectively matches the identification information of the memory to which the initialization data is loaded next pointed by the link with the identification information of the N memories;
And the controller determines the next memory for loading the initialization data pointed by the link in the N memories according to the matching result.
6. The method of claim 1, wherein the controller determines N of the memories to load the initialization data and before loading a first of the memories of the initialization data, the method further comprises:
and the controller stores the initialization data corresponding to each memory into the corresponding memory.
7. The method of claim 1, wherein the controller determining the first of the memories to load the initialization data comprises:
and the controller determines to load the first memory of the initialization data according to the pin of the chip.
8. The method of claim 1, wherein the initialization data comprises an address of at least one register and data in the register.
9. A chip is characterized in that the chip comprises a controller and an I2C bus, wherein the I2C bus is used for connecting the controller and N memories, N is a natural number larger than 1, and N is a natural number larger than 1, wherein the I2C bus is used for connecting the controller and N memories
The controller is configured to determine N memories needing to be loaded with initialization data and a first memory loading the initialization data;
the controller is further configured to perform the following initialization data loading operations starting from the first of the memories:
For each memory to be loaded with the initialization data, after completing loading of the initialization data corresponding to each memory, the controller starts a link of the memory pointing to the next memory to which the initialization data is loaded, loads the initialization data corresponding to the memory through the next memory to which the initialization data is loaded, and loads the corresponding initialization data until the last memory completes loading of the corresponding initialization data, wherein the memory comprises a first address space and a second address space, the first address space is used for storing the initialization data corresponding to the memory, and the second address space is used for storing the link of the memory pointing to the next memory to which the initialization data is loaded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410190031.1A CN117742805B (en) | 2024-02-21 | 2024-02-21 | Chip initialization method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410190031.1A CN117742805B (en) | 2024-02-21 | 2024-02-21 | Chip initialization method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117742805A CN117742805A (en) | 2024-03-22 |
| CN117742805B true CN117742805B (en) | 2024-05-31 |
Family
ID=90261303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410190031.1A Active CN117742805B (en) | 2024-02-21 | 2024-02-21 | Chip initialization method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117742805B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101815990A (en) * | 2007-10-02 | 2010-08-25 | 高通股份有限公司 | Memory controller for performing memory block initialization and copy |
| CN106294213A (en) * | 2016-08-02 | 2017-01-04 | 芯启源电子科技有限公司 | Storage device, electronic equipment and buffer management method |
| CN114121068A (en) * | 2020-08-31 | 2022-03-01 | 三星电子株式会社 | Nonvolatile memory device, nonvolatile memory, and method of operating memory controller |
| CN114968130A (en) * | 2022-08-01 | 2022-08-30 | 深圳云豹智能有限公司 | Chain table initialization device, method, system, computer equipment and storage medium |
| CN116049090A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | Chip initialization data storage method and chip initialization method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6857041B2 (en) * | 2002-03-29 | 2005-02-15 | Intel Corporation | Method and apparatus providing an interface to allow physical memory to be initialized using firmware/hardware methods |
| US8595426B2 (en) * | 2011-04-11 | 2013-11-26 | Sandisk Il Ltd. | Handling commands within a write-once read-many storage device configuration |
-
2024
- 2024-02-21 CN CN202410190031.1A patent/CN117742805B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101815990A (en) * | 2007-10-02 | 2010-08-25 | 高通股份有限公司 | Memory controller for performing memory block initialization and copy |
| CN106294213A (en) * | 2016-08-02 | 2017-01-04 | 芯启源电子科技有限公司 | Storage device, electronic equipment and buffer management method |
| CN114121068A (en) * | 2020-08-31 | 2022-03-01 | 三星电子株式会社 | Nonvolatile memory device, nonvolatile memory, and method of operating memory controller |
| CN114968130A (en) * | 2022-08-01 | 2022-08-30 | 深圳云豹智能有限公司 | Chain table initialization device, method, system, computer equipment and storage medium |
| CN116049090A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | Chip initialization data storage method and chip initialization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117742805A (en) | 2024-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8943232B2 (en) | System method for enumerating client devices embedded in a user device during reboot, wake up or restart of user device | |
| US6810444B2 (en) | Memory system allowing fast operation of processor while using flash memory incapable of random access | |
| US11074083B2 (en) | Fast loading kernel image file for booting | |
| CN112765271A (en) | Block chain transaction index storage method and device, computer equipment and medium | |
| CN105912362B (en) | A kind of method, apparatus and electronic equipment loading plug-in unit | |
| CN110928935B (en) | Data access command processing method, device and system | |
| CN112198820B (en) | Interrupt service implementation method, device, equipment and storage medium | |
| JP6136127B2 (en) | Controller, electronic apparatus and USB device control method | |
| WO2023070823A1 (en) | Bootloader loading method, apparatus and system, electronic device and medium | |
| WO2008138258A1 (en) | Peripheral device operation method, peripheral device and host | |
| US20200401384A1 (en) | Electronic device and operation method thereof | |
| CN111459523A (en) | Image quality chip software upgrading method and device, electronic equipment and storage medium | |
| WO2024093542A1 (en) | Usb drive-free communication method and apparatus, and electronic device and storage medium | |
| WO2024078218A1 (en) | System booting method and electronic device | |
| WO2023060893A1 (en) | Storage space management method and apparatus, and device and storage medium | |
| CN110795369A (en) | Method and terminal for realizing MIDO slave function based on GPIO pin | |
| CN117742805B (en) | Chip initialization method and device | |
| US20200218710A1 (en) | Electronic device and data management method thereof | |
| WO2023193528A1 (en) | File decompression method and apparatus, and electronic device and computer-readable storage medium | |
| CN117098105A (en) | Firmware upgrading method, device and system for embedded equipment cluster | |
| US6349388B1 (en) | Timer processing engine for supporting multiple virtual minimum time timers | |
| JP2004078402A (en) | Data transfer control device, electronic device, program, and method of manufacturing electronic device | |
| CN109982136B (en) | Volume adjusting method and device | |
| US9086895B1 (en) | Controlling hardware driver selection | |
| CN111913666A (en) | Method and device compatible with Nand particles with different protocols, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |