CN116017184B - Composite dielectric gate double-transistor pixel reading circuit based on inverter chain transimpedance amplifier - Google Patents
Composite dielectric gate double-transistor pixel reading circuit based on inverter chain transimpedance amplifier Download PDFInfo
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Abstract
The invention discloses a composite dielectric gate double-transistor pixel reading circuit based on an inverter chain transimpedance amplifier, and belongs to the field of integrated circuits. The circuit comprises a composite dielectric gate double-transistor photosensitive detector pixel, a switch S1, a slope generator, an inverter chain transimpedance amplifier, a driving stage and a counter, wherein the control end of the composite dielectric gate double-transistor photosensitive detector pixel is connected with the slope generator, the first end is grounded, and the second end is connected with the input end of the inverter chain transimpedance amplifier; the output end of the inverter chain trans-impedance amplifier is connected with the input end of the driving stage; the output of the driver stage acts as an enable signal for the counter. The circuit of the invention avoids the problem that the direct current working level of the amplifier is not in a linear amplification interval, and is not easy to be interfered by high-frequency noise of an input end, so that the high-speed and high-precision reading of the double-transistor photosensitive detector with the composite dielectric gate is realized.
Description
Technical Field
The invention relates to a composite dielectric gate double-transistor pixel reading circuit based on an inverter chain transimpedance amplifier, and belongs to the field of integrated circuits.
Background
Aiming at the problems that a common imaging device (such as CCD and CMOS-APS) in the imaging field has small pixel photosensitive area filling factor, small full-well charge quantity and the like, the Chinese patent publication No. CN102938409B provides a composite dielectric gate double-transistor photosensitive detector which is characterized in that a single device has reset, photosensitive and reading functions, and compared with the common imaging device, the pixel photosensitive area filling factor is improved, and the full-well charge quantity is increased.
As a new generation of imaging devices, such a composite dielectric gate two transistor photodetector utilizes a variable threshold MOSFET signal readout region for readout. Based on the characteristics, the circuit capable of realizing rapid logic inversion by detecting the threshold voltage can realize high-speed and high-precision reading of the double-transistor photosensitive detector with the composite dielectric gate.
There have been some reports on composite dielectric gate two-transistor detectors. For example, CN 114071041A discloses a "composite dielectric gate two-transistor pixel readout circuit based on a switched capacitor", which avoids the design of a conventional voltage regulator structure, solves the problem of loop stability that may occur, and in the readout phase, the feedback loop of the operational amplifier is disconnected, and the circuit detects the threshold voltage by using the cascade structure of the open loop operational amplifier and the comparator to realize rapid logic inversion. However, the invention adopts an open loop operational amplifier structure in the reading stage, and has the following disadvantages: the problem that the direct current working level shifts to the linear working area when the output end is opened in the reading stage is solved, the hidden danger that the working level of the output end is influenced by the high-frequency noise of the input end through gain cannot be avoided by the open loop structure, the open loop structure operational amplifier is low in gain and low in working speed by the open loop structure operational amplifier and the open loop structure operational amplifier, and therefore the logic turnover speed of the composite dielectric gate double-transistor pixel reading circuit based on the switch capacitor is low after the threshold voltage is detected, noise interference is prone to occur, and the low-speed and low-precision reading effect is achieved.
Disclosure of Invention
In order to solve at least one technical problem, the invention provides a composite dielectric gate double-transistor pixel reading circuit based on an inverter chain transimpedance amplifier, so as to realize high-speed and high-precision reading of a composite dielectric gate double-transistor photosensitive detector.
The technical scheme adopted by the invention is as follows:
the composite dielectric gate double-transistor pixel reading circuit based on the inverter chain transimpedance amplifier comprises a composite dielectric gate double-transistor photosensitive detector pixel, a switch S1, a slope generator, the inverter chain transimpedance amplifier, a driving stage and a counter; the pixel control end of the composite dielectric gate double-transistor photosensitive detector is connected with a slope generator, the first end of the composite dielectric gate double-transistor photosensitive detector is grounded, and the second end of the composite dielectric gate double-transistor photosensitive detector is connected with the input end of the inverter chain transimpedance amplifier; the output end of the inverter chain trans-impedance amplifier is connected with the input end of the driving stage; the output end of the driving stage is used as an enabling signal of the counter; there are three external connection voltages in the circuit: the first voltage V1, the second voltage V2, and the third voltage V3.
Further, the composite dielectric gate two-transistor photodetector pixel includes a MOS-C (Metal-Oxide-Semiconductor-Capacitor) signal collection region and a MOSFET (Metal-Oxide-Semiconductor field effect transistor, metal-Oxide-Semiconductor Field-Effect Transistor) signal readout region. In the exposure mode, the MOS-C signal collection area generates a depletion area in the substrate under the action of the forward bias of the grid electrode and the substrate, so as to collect photo-generated carriers; in a readout mode, the threshold voltage of a transistor of the MOSFET signal readout region is correspondingly changed according to the collected photo-generated carrier charge quantity, so that the photo-generated carrier signal is read out; the MOSFET signal reading area is an N-type MOSFET transistor, and the grid electrode, the source electrode and the drain electrode of the MOSFET signal reading area respectively correspond to the control end, the first end and the second end of the composite dielectric gate double-transistor pixel.
Further, the inverter chain transimpedance amplifier, the driving stage and the counter work at the first voltage V1.
Further, one end of the switch S1 is connected to the second voltage V2 and v2=0.5×v1, and the other end is connected to the input end of the inverter chain transimpedance amplifier.
Further, the ramp generator comprises a constant current source, a feed-forward amplifier and a feedback loop formed by connecting a capacitor and a switch S2 in parallel, and realizes ramp voltage output by utilizing integral discharge of the constant current source to the feedback capacitor, and the circuit works under the third voltage V3.
Further, the inverter chain transimpedance amplifier comprises an open loop feedforward amplifier (N is an odd number) formed by N-level inverter cascading and a feedback network formed by resistors; the resistor is a transistor on-state resistor.
Further, the driving stage is an inverter cascade driver, and the output end of the driving stage is used as a counter enabling signal.
Further, when the enable signal of the counter is logic 1, the counter is enabled, and in the process of timing by the timer, the value of the output port of the counter is increased by 1 after each clock period is ended.
In the present invention, an inverter chain transimpedance amplifier is critical.
The inverter chain transimpedance amplifier structure comprises an open loop feedforward amplifier (N is odd) formed by cascading N-level inverters and a feedback network formed by resistors, wherein each level of inverter comprises a pair of P-type doped MOSFET (PMOS) and N-type doped MOSFET (NMOS) which are connected in series, the PMOS source electrode is connected with a first voltage V1, the NMOS source electrode is connected with 0 potential, the grid electrodes of the PMOS source electrode and the NMOS source electrode are connected as input ends, the drain electrode is connected as output ends, the width-to-length ratio of the two tubes is the inverse (typical value is 2.5:1) of the ratio of hole mobility to electron mobility, so that when the input ends and the output ends are both in a saturated working area, the two tubes are in a saturated working area, and the inverter chain is formed by sequentially cascading the single number of the inverters according to the input end of the last inverter output end of the previous inverter. The resistance in the feedback network is the transistor on-resistance.
The working principle/process of the invention is as follows:
the invention has two working phases, including a reset phase and a read-out phase, which are alternately performed, after the last read-out phase is completed, the circuit enters the reset phase, the slope generator is in a unit negative feedback connection state, the output voltage is short-circuited with the input potential of the negative terminal, the input potential of the negative terminal is equal to the input reference potential of the positive terminal, which is obtained by virtual short, so that the output of the slope generator is 0V with a constant level, and the N-type MOSFET signal read-out transistor in the pixel of the composite medium gate double transistor photosensitive detector is completely closed because the 0V is lower than the threshold voltage of the pixel of the composite medium gate double transistor photosensitive detector, and the branch current of the source and the drain is 0. The input end of the inverter chain trans-impedance amplifier is connected with a second voltage V2 (V2 = 0.5 x V1), because the inverter chain trans-impedance amplifier is connected in a closed loop, no current flows through a feedback resistor of the inverter chain trans-impedance amplifier, and therefore the output end of the inverter chain trans-impedance amplifier is also the second voltage V2, the cascading positions of all levels of inverters in the inverter chain are all near the middle level, PMOS and NMOS in all levels of inverters are in the direct current working level of a saturated working area, the phase waits for a reading phase, a driving stage outputs a high level V1, an enabling signal of a counter is logic '1', and the counter is enabled, but the counter is not electrified because the counter is in a reset phase, and the counting value is cleared and cannot be counted. After the reset phase, the circuit enters a reading phase, the counter is quickly electrified and is in an enabling state, the counter starts to count from 0, the ramp generator is an integrating circuit for negative feedback of the capacitor, and the ramp voltage output from 0V to V3 is realized by integrating and discharging of the constant current source to the feedback capacitor. In the time period that the slope voltage does not rise to the threshold voltage of the pixel of the double-transistor photosensitive detector with the composite dielectric gate, the N-type MOSFET signal reading transistor in the pixel of the double-transistor photosensitive detector with the composite dielectric gate is completely closed, the current of the branch where the source electrode and the drain electrode are located is 0, the feedback resistor in the inverter chain transimpedance amplifier still does not flow through current, the output end of the inverter chain transimpedance amplifier is also the second voltage V2, the cascading position of all levels of inverters in the inverter chain is the potential near the middle level, the PMOS and the NMOS in all levels of the inverters are in the direct current working level of the saturated working area, the driving stage still outputs the high level V1, and the counter keeps the enabled state and continuously counts. At the moment when the slope voltage rises to the threshold voltage of the pixel of the double-transistor photosensitive detector with the composite medium gate, an N-type MOSFET signal readout transistor in the pixel of the double-transistor photosensitive detector with the composite medium gate is immediately conducted, microampere current appears in a branch where a source electrode and a drain electrode are located, at the moment, all transistors of an inverter chain are in a saturated working state and have high gain, a large capacitor does not exist in the inverter chain, the transient response speed is high, the inverter chain transimpedance amplifier rapidly responds to the current by utilizing the high-gain and high-speed feedforward amplifier of the inverter chain, and the feedback resistor amplifies the current to enable the output level of the transimpedance amplifier to rapidly rise from V2 to V1, so that the function of rapidly detecting the threshold voltage of the pixel with the double-transistor with the composite medium gate and completing logic inversion is realized, the output level of a driving stage with the inversion function is rapidly reduced to 0V by the V1 level, an enabling signal of a counter is not enabled any more, the counter is stopped, the value of the counter is the gray value of the double-transistor photosensitive detector with the composite medium gate is stopped, and the readout is completed.
The invention also provides a composite dielectric gate double-transistor photosensitive detector which comprises the composite dielectric gate double-transistor pixel reading circuit based on the inverter chain transimpedance amplifier.
The invention also provides an application of the composite dielectric gate double-transistor pixel reading circuit or the composite dielectric gate double-transistor photosensitive detector based on the inverter chain transimpedance amplifier in the imaging field.
Further, the method can be used for a double-transistor photosensitive detector with a composite dielectric gate, and belongs to the field of imaging.
The invention has the beneficial effects that:
the inverter chain transimpedance amplifier structure in the circuit can rapidly detect the threshold voltage of the composite dielectric gate double-transistor pixel and complete logic inversion, so that the high-speed and high-precision readout of the composite dielectric gate double-transistor photosensitive detector is realized.
The composite dielectric gate double-transistor pixel reading circuit based on the inverter chain transimpedance amplifier provided by the invention avoids the design of an open loop structure amplifier on the basis of avoiding the design of a conventional voltage stabilizer structure and solving the problem of loop stability possibly occurring, and replaces the cascade structure of the open loop operational amplifier and the comparator in the scheme by using the inverter chain transimpedance amplifier with a closed loop connection method. Because the closed loop structure is adopted, the feedforward amplifier is an inverter chain structure, the inverter chain transimpedance amplifier is easy to determine the direct current working level of the linear amplification working state in the resetting stage, and because no current flows through the feedback resistor, the direct current working level at the output end of the inverter chain transimpedance amplifier resets to one half of the power supply level along with the direct current working level at the input end, when the reading stage is started, each node of the inverter chain is at the middle level, the problem of shifting the linear working interval is avoided, all transistors of the inverter chain are in the saturated working state and have high gain, and the inverter chain has no large capacitance and has high transient response speed; the closed loop structure has the advantages that the closed loop structure is insensitive to high-frequency noise of the input end, the hidden danger that the working level of the output end is influenced by the high-frequency noise of the input end through gain is effectively avoided, and therefore the circuit has high speed and high gain. In summary, compared with the prior art, the circuit provided by the invention avoids the problem that the direct current working level of the amplifier is not in a linear amplification interval, is not easy to be interfered by high-frequency noise at the input end, and can realize high-speed and high-precision reading of the double-transistor photosensitive detector with the composite dielectric gate.
The composite dielectric gate double-transistor pixel reading circuit based on the inverter chain transimpedance amplifier can be used for a composite dielectric gate double-transistor photosensitive detector and is used for the imaging field.
Drawings
FIG. 1 is a schematic diagram of a composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier according to the present invention.
Description of the embodiments
The technical solution of the present invention will be described in more detail below with reference to the accompanying drawings.
Example 1: composite dielectric gate double-transistor pixel reading circuit based on inverter chain transimpedance amplifier
Fig. 1 is a schematic diagram of a composite dielectric gate double-transistor pixel readout circuit based on an inverter chain transimpedance amplifier in the present embodiment, which includes a composite dielectric gate double-transistor photosensitive detector pixel 1, a switch 2, a ramp generator 3, a single-stage inverter chain transimpedance amplifier 4, a driving stage 5 with an inverting function, and a counter 6. The specific structure of the pixel 1 of the composite dielectric gate double-transistor photosensitive detector is described in the Chinese patent publication No. CN 102938409B. The MOSFET signal readout area in the composite dielectric gate double-transistor photosensitive detector pixel 1 is an N-type MOSFET transistor, the grid electrode of the MOSFET signal readout area is connected with the slope generator 3, the source electrode of the MOSFET signal readout area is grounded, and the drain electrode of the MOSFET signal readout area is connected with the input end of the single-stage inverter transimpedance amplifier 4; the output end of the single-stage inverter transimpedance amplifier 4 is connected with the input end of the driving stage 5 with the inverting function; the output of the drive stage 5 with an inverting function serves as an enable signal for the counter 6. There are three external connection voltages in the circuit: the first voltage V1 is used for supplying voltage to the single-stage inverter chain transimpedance amplifier 4, the driving stage 5 with the inverting function and the counter 6; a second voltage V2 connected to one end of the switch 2; and a third voltage V3 for supplying voltage to the ramp generator 3.
The reference potential of the positive end of the feedforward amplifier in the slope generator 3 is 0V, and under the voltage of a V3 power supply, the slope voltage output with the range of 0V-V3 is realized by utilizing the integral discharge of a constant current source to a feedback capacitor.
The single-stage inverter chain transimpedance amplifier 4 comprises an open loop feedforward amplifier formed by a single-stage inverter and a feedback network formed by transistor on-resistance, wherein the feedback network formed by the transistor on-resistance has the advantages of small area and high integration level, and the single-stage inverter feedforward amplifier has the characteristics of high speed and high gain, and can rapidly detect the threshold voltage of the composite dielectric gate double-transistor pixel and complete logic inversion. The single-stage inverter chain transimpedance amplifier 4 outputs a logic "1" corresponding to a level V1 and outputs a logic "0" corresponding to a level V2.
A driving stage 5 having an inverting function, the input level of which is the output level of the single-stage inverter chain transimpedance amplifier 4, the driving stage 5 outputting a 0V level for an input level having a potential V1, the counter enable signal being logic "0", the counter 6 not being enabled; for an input level of potential V2, the driving stage 5 outputs V1 level, the enable signal of the counter is logic "1", and the counter 6 is enabled.
Example 2: example 1 specific application of the Circuit
The specific working mode of the composite dielectric gate double-transistor pixel reading circuit based on the inverter chain transimpedance amplifier is described below:
there are three external connection voltages in the circuit: the first voltage V1 is 1.2V and is used for voltage supply of a single-stage inverter chain transimpedance amplifier 4, a driving stage 5 with an inverting function and a counter 6; the second voltage V2 is 0.6V and is connected with one end of the switch 2; the third voltage V3 is 5V for the supply voltage of the ramp generator 3.
During circuit operation, switches S1 and S2 share a switch enable signal divided into two time periods: phi 1 andtwo switches are turned on (referred to as phi 1 phase) for a time period when the enable signal is phi 1, which is +.>During the period of time two switches are open (called +.>Phase), phi 1 phase is the reset phase, +.>The phase is the readout phase. The switch enable signal is also used as the power-on signal of the counter, the counter 6 is not powered on in the phi 1 phase, and the counter is in the phi 1 phase>In phase counter 6 is powered up so that counter 6 is only +.>The phase and drive stage 5 output is 1.2V level to enable it.
In the phase phi 1, the switch S2 is conducted, the ramp generator 3 is in a unit negative feedback connection state, the output voltage is short-circuited with the input potential of the negative terminal, the input potential of the negative terminal is equal to the input reference potential of the positive terminal by the short-circuit, so that in the phase phi 1, the output of the ramp generator 3 is 0V with a constant level, and 0V is lower than the threshold voltage of the pixel 1 of the double-transistor photosensitive detector with the composite medium gate, the N-type MOSFET signal readout transistor in the pixel 1 of the double-transistor photosensitive detector with the composite medium gate is completely closed, the current of the branch where the source electrode and the drain electrode are located is 0, the input end of the single-stage inverter chain-span resistor amplifier 4 is 0.6V due to the conduction of the switch S1, the output end of the single-stage inverter chain-span-resistor amplifier 4 is also 0.6V due to the fact that no current flows through the feedback resistor, the driving stage 5 outputs 1.2V level, the enabling signal of the counter 6 is logic '1', the counter 6 is enabled, but the counter 6 is not powered up due to the phase phi 1, the count value cannot be counted.
The phase is after phi 1 phase, at +.>In phase, counter 6 is rapidly powered up and in an enabled state, starting counting from 0. The switches S1 and S2 are turned off, the ramp generator 3 is an integrating circuit with negative feedback of the capacitor, and the ramp voltage output from 0V to 5V is realized by integrating and discharging of the feedback capacitor by the constant current source. Without the ramp voltage rising to the threshold of the composite dielectric gate two transistor photodetector pixel 1In the voltage period, an N-type MOSFET signal readout transistor in the composite dielectric gate double-transistor photosensitive detector pixel 1 is completely turned off, the current of a branch where a source electrode and a drain electrode are located is 0, no current flows through a feedback resistor in the single-stage inverter chain transimpedance amplifier 4, the input end and the output end of the feedback resistor are still kept at 0.6V potential, the driving stage 5 still outputs 1.2V level, and the counter 6 is kept in an enabled state and continuously counts. At the moment that the slope voltage rises to the threshold voltage of the composite medium gate double-transistor photosensitive detector pixel 1, an N-type MOSFET signal readout transistor in the composite medium gate double-transistor photosensitive detector pixel 1 is immediately conducted, microampere-level current appears in a branch where a source electrode and a drain electrode are located, a single-stage inverter chain transimpedance amplifier 4 rapidly responds to the microampere-level current by using a high-gain and high-speed feed-forward amplifier, the single-stage inverter chain transimpedance amplifier 4 rapidly amplifies the microampere-level current by using a feedback resistor, the output level of the transimpedance amplifier 4 rapidly rises from 0.6V to 1.2V, the function of rapidly detecting the threshold voltage of the composite medium gate double-transistor pixel and completing logic inversion is realized, the output level of a driving stage 5 with an inversion function rapidly drops to 0V from 1.2V level, an enabling signal of a counter 6 is logic 0, the counter 6 is not enabled any more, the count is stopped, and the instantaneous counter value is the gray value of the composite medium gate double-transistor photosensitive detector, and readout is completed.
Claims (8)
1. The composite dielectric gate double-transistor pixel reading circuit based on the inverter chain transimpedance amplifier is characterized by comprising a composite dielectric gate double-transistor photosensitive detector pixel, a switch S1, a slope generator, the inverter chain transimpedance amplifier, a driving stage and a counter; the pixel control end of the composite dielectric gate double-transistor photosensitive detector is connected with a slope generator, the first end of the composite dielectric gate double-transistor photosensitive detector is grounded, and the second end of the composite dielectric gate double-transistor photosensitive detector is connected with the input end of the inverter chain transimpedance amplifier; the output end of the inverter chain trans-impedance amplifier is connected with the input end of the driving stage; the output end of the driving stage is used as an enabling signal of the counter; there are three external connection voltages in the circuit: a first voltage V1, a second voltage V2, a third voltage V3; the inverter chain transimpedance amplifier, the driving stage and the counter work under the first voltage V1; one end of the switch S1 is connected to the second voltage V2 and v2=0.5v1, and the other end is connected to the input end of the inverter chain transimpedance amplifier; the third voltage V3 is used for supplying voltage to the slope generator.
2. The composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier according to claim 1, wherein the inverter chain transimpedance amplifier comprises an open loop feed forward amplifier consisting of N-stage inverter cascades and a feedback network consisting of resistors; wherein N is an odd number.
3. The composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier according to claim 2, wherein each inverter stage comprises a pair of P-type doped MOSFET and N-type doped MOSFET, PMOS and NMOS, connected in series; the PMOS source electrode is connected with a first voltage V1, the NMOS source electrode is connected with 0 potential, the grid electrode of the PMOS source electrode and the grid electrode of the NMOS source electrode are connected as input ends, the drain electrode of the NMOS source electrode is connected as output ends, and the width-to-length ratio of the two transistors is the reciprocal of the ratio of hole mobility to electron mobility; the inverter chain is formed by sequentially cascading a plurality of inverters according to the output end of the previous inverter and the input end of the next inverter.
4. The inverter chain transimpedance amplifier-based composite dielectric gate two-transistor pixel readout circuit according to claim 1, wherein the composite dielectric gate two-transistor photodetector pixel comprises a MOS-C signal collection region and a MOSFET signal readout region.
5. The composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier according to claim 1, wherein the ramp generator comprises a constant current source, a feed-forward amplifier and a feedback loop formed by connecting a capacitor in parallel with a switch S2, and the ramp voltage output is realized by integrating discharge of the constant current source to the feedback capacitor, and the circuit operates at the third voltage V3.
6. The composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier according to claim 1, wherein the driving stage is an inverter cascade driver, and the output terminal thereof is a counter enable signal.
7. A composite dielectric gate two-transistor photo detector comprising the composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier as claimed in any one of claims 1 to 6.
8. An imaging device comprising the composite dielectric gate two-transistor pixel readout circuit based on an inverter chain transimpedance amplifier according to any one of claims 1 to 6 or the composite dielectric gate two-transistor photodetector according to claim 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310321390.1A CN116017184B (en) | 2023-03-29 | 2023-03-29 | Composite dielectric gate double-transistor pixel reading circuit based on inverter chain transimpedance amplifier |
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| CN202310321390.1A CN116017184B (en) | 2023-03-29 | 2023-03-29 | Composite dielectric gate double-transistor pixel reading circuit based on inverter chain transimpedance amplifier |
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| CN116017184B true CN116017184B (en) | 2023-07-21 |
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| US20050068438A1 (en) * | 2003-09-30 | 2005-03-31 | Innovative Technology Licensing, Llc | Low noise CMOS amplifier for imaging sensors |
| CN111147078B (en) * | 2019-12-10 | 2023-04-21 | 南京威派视半导体技术有限公司 | Analog-to-digital conversion circuit based on composite dielectric gate double-transistor photosensitive detector |
| CN114071034B (en) * | 2021-11-10 | 2022-08-19 | 南京大学 | Composite dielectric gate double-transistor pixel reading circuit based on switched capacitor |
| CN114039562B (en) * | 2021-11-16 | 2022-08-30 | 成都明夷电子科技有限公司 | Low-cost over-frequency high-speed trans-impedance amplifier |
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