CN116013981A - High electron mobility transistor and preparation method thereof - Google Patents

Abstract

The application provides a high electron mobility transistor and a preparation method thereof, and relates to the technical field of semiconductors, and the high electron mobility transistor comprises a substrate and a functional layer which is arranged on the substrate and has a heterojunction interface, wherein the functional layer comprises an active region and an inactive region, a first P-type layer is arranged in the inactive region of the functional layer, the first P-type layer is used for removing two-dimensional electron gas of the inactive region covered by the first P-type layer so as to correspondingly form a depletion region, so that an isolation function formed in an ion implantation or mesa etching process in the prior art is realized, a barrier layer and a channel layer are not damaged while the isolation function is realized, and no lattice and surface defect state damage is caused.

Description

High electron mobility transistor and preparation method thereof

Technical Field

The application relates to the technical field of semiconductors, in particular to a high electron mobility transistor and a preparation method thereof.

Background

The gallium nitride-based High Electron Mobility Transistor (HEMT) has the advantages of strong breakdown field, high electron mobility, high thermal conductivity and the like, so that the gallium nitride-based high electron mobility transistor is expected to replace a traditional silicon-based device in the field of power electronics. Due to the fact that the III-nitride material is not centrosymmetric, the vicinity of the interface of the AlGaN heterojunction and the GaN heterojunction has strong piezoelectric polarization and spontaneous polarization effects, interface charges and electric fields are induced, and an electron potential well is formed at the interface. These accumulated high concentration electrons move at high speed in a direction parallel to the heterojunction interface to form a two-dimensional electron gas (2 DEG). The two-dimensional electron gas is conducted and closed through the grid switch. The inter-module HEMTs need to be isolated. At present, the existing isolation technology mainly adopts two methods of plasma mesa etching or ion implantation.

The ion implantation is to use up electrons in the channel layer by high-energy implantation of F+, O+ ion beams in the barrier layer AlGaN so as to achieve the isolation purpose, but the defect that the deep level defect is introduced by the high-energy implantation ions to influence the dynamic characteristics of the device is large in lattice damage, difficult in photoresist removal and high in cost. The mesa etching is to etch isolation channels among the device units by utilizing reactive plasmas so as to achieve the purpose of isolating the conduction channels, but the mesa etching is easy to introduce a large number of acceptor-like defects and surface states on the surface of the isolation region, so that the device is electrically leaked. In addition, the mesa etching is non-planar isolation, and gate electrode metal directly contacts the exposed 2DEG on the side wall of the mesa, so that an additional leakage channel is generated.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, and provides a high electron mobility transistor and a preparation method thereof, which can realize effective isolation without damaging a barrier layer and a channel layer, and have no lattice and surface defect state damage, low cost and simple and feasible process.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

in an aspect of the embodiments of the present application, a high electron mobility transistor is provided, including a substrate and a functional layer disposed on the substrate and having a heterojunction interface, where the functional layer includes an active region and an inactive region, a first P-type layer is disposed in the inactive region of the functional layer, the first P-type layer is configured to remove two-dimensional electron gas in the inactive region covered by the first P-type layer to form a depletion region correspondingly, and a source electrode, a drain electrode and a gate electrode are disposed in the active region of the functional layer.

Optionally, a second P-type layer is further disposed in the active region of the functional layer, and the second P-type layer is located between the functional layer and the gate electrode.

Optionally, the source electrode and the drain electrode each include an ohmic metal layer and an interconnection metal layer which are sequentially stacked, and the ohmic metal layer and the functional layer form ohmic contact.

Optionally, a groove is disposed in the active region of the functional layer, the groove extending from a surface of a side of the functional layer facing away from the substrate to a heterojunction interface of the functional layer, and the ohmic metal layer is disposed in the groove to be in contact with two-dimensional electron gas at the heterojunction interface.

Optionally, the depletion region is disposed around the periphery of the active region.

Optionally, the inactive region of the functional layer includes a depletion region and a resistive region, and a resistor is further disposed in the resistive region of the functional layer.

Optionally, the resistor area of the functional layer is further provided with a first metal part and a second metal part which are spaced apart, the resistor comprises a two-dimensional electron gas resistor of which the functional layer is positioned in the resistor area, and the first metal part is electrically connected with the second metal part through the two-dimensional electron gas resistor.

Optionally, the first P-type layer is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer.

Optionally, the thickness of the first P-type layer is 20nm to 300nm.

In another aspect of the embodiments of the present application, there is provided a method for manufacturing a high electron mobility transistor, the method including: epitaxially growing a functional layer with a heterojunction interface on a substrate, wherein the functional layer comprises an active region and a non-active region; epitaxially growing a P-type layer on the functional layer, wherein the P-type layer covers the active region and the inactive region; etching the P-type layer to form a first P-type layer in the non-active region of the functional layer, wherein the first P-type layer is used for removing two-dimensional electron gas of the non-active region covered by the first P-type layer to correspondingly form a depletion region; a source electrode, a drain electrode, and a gate electrode are formed in an active region of the functional layer.

The beneficial effects of this application include:

the application provides a high electron mobility transistor and a preparation method thereof, the high electron mobility transistor comprises a substrate and a functional layer which is arranged on the substrate and has a heterojunction interface, wherein the functional layer comprises an active region and an inactive region, a first P-type layer is arranged in the inactive region of the functional layer, the first P-type layer is used for removing two-dimensional electron gas of the inactive region covered by the first P-type layer so as to correspondingly form a depletion region, so that an isolation function formed in an ion implantation or mesa etching process in the prior art is realized, a barrier layer and a channel layer are not damaged while the isolation function is realized, and no crystal lattice and surface defect state damage is caused.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a preparation state of a high electron mobility transistor according to an embodiment of the present application;

FIG. 2 is a schematic diagram showing a second embodiment of a preparation state of a high electron mobility transistor according to the present invention;

FIG. 3 is a third schematic diagram of a preparation state of a high electron mobility transistor according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram showing a preparation state of a high electron mobility transistor according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram showing a preparation state of a high electron mobility transistor according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another embodiment of a preparation state of a high electron mobility transistor;

FIG. 7 is a second schematic diagram of a preparation state of another HEMT according to an embodiment of the present disclosure;

FIG. 8 is a third schematic diagram of a preparation state of another HEMT according to an embodiment of the present disclosure;

fig. 9 is a top view of another hemt provided in an embodiment of the present application.

Icon: 100-a substrate; 110-a nucleation layer; 120-a buffer layer; 130-a channel layer; 140-an interposer; 150-barrier layer; 160-an aluminum nitride layer; 170-P-type layer; 171-a first P-type layer; 172-a second P-type layer; 180-functional layer; 181-grooves; 182-resistive contact grooves; 210-an active region; 220-depletion region; 230-gate electrode; 241-ohmic metal layer of source electrode; 242-an interconnect metal layer of the source electrode; 251-ohmic metal layer of the drain electrode; 252-an interconnect metal layer of the drain electrode; 260-a resistive region; 271-a first metal portion; 272-a second metal part.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Related terms such as "below" or "above" … "or" upper "or" lower "or" horizontal "or" vertical "may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It should be understood that these terms, and those terms discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In an aspect of the embodiments of the present application, as shown in fig. 5 or 8, a high electron mobility transistor is provided, including a substrate 100 and a functional layer 180, wherein the functional layer 180 is disposed on the substrate 100, and the functional layer 180 includes at least a heterojunction structure, thereby being capable of forming a two-dimensional electron gas at a heterojunction interface of the heterojunction structure, the functional layer 180 includes an active region 210 and a non-active region, and the active region 210 can be used to fabricate a source electrode, a drain electrode, and a gate electrode 230, thereby forming the high electron mobility transistor.

In order to isolate the active region 210, a first P-type layer 171 may be disposed in the inactive region of the functional layer 180, so that the first P-type layer 171 at least covers a portion of the inactive region, and the first P-type layer 171 is capable of removing the two-dimensional electron gas at the heterojunction interface in the functional layer 180 in the area covered by the first P-type layer 171, so that the area covered by the first P-type layer 171 in the inactive region corresponds to the depletion region 220, and the two-dimensional electron gas in the depletion region 220 is removed, so that the depletion region 220 can be isolated, i.e. the active region 210 is effectively isolated.

For example, as shown in fig. 5, the functional layer 180 includes an active region 210 and an inactive region located at the periphery of the active region 210, a first P-type layer 171 covering the inactive region is disposed in the inactive region, and under the action of the first P-type layer 171, two-dimensional electron gas in the inactive region in the functional layer 180 is depleted and removed, so that the whole inactive region serves as a depletion region 220 to play a role of isolation.

As shown in fig. 8, the functional layer 180 includes an active region 210 and an inactive region located at the periphery of the active region 210, and a first P-type layer 171 is disposed in a partial region in the inactive region, that is, the first P-type layer 171 partially covers the inactive region, so that two-dimensional electron gas in the region covered by the first P-type layer 171 is depleted and removed under the action of the first P-type layer 171, thereby making a part of the inactive region of the functional layer 180 serve as a depletion region 220 to play a role of isolation.

In summary, the present application achieves the isolation function formed in the ion implantation or mesa etching process in the prior art by disposing the first P-type layer 171 in the inactive region to form the depletion region 220, and does not damage the barrier layer 150 and the channel layer 130 while playing the isolation function, and has no damage to the lattice and surface defect states, so that (at least) one photolithography process can be saved compared with the ion implantation or mesa etching process, thereby achieving low cost and simple process.

In some embodiments, the substrate 100 may be a silicon, sapphire, silicon carbide, gallium nitride, or the like substrate, which is not particularly limited herein.

In some embodiments, the functional layer 180 may include a plurality of active semiconductor layers, at least two of which may be used to form a heterojunction structure, thereby generating a two-dimensional electron gas at a heterojunction interface. The heterojunction structure may be a channel layer 130/barrier layer 150 sequentially stacked on the substrate 100.

In some embodiments, as shown in fig. 5 or 8, a buffer layer 120 may be further disposed between the channel layer 130 and the substrate 100, a nucleation layer 110 may be disposed between the buffer layer 120 and the substrate 100, and an insertion layer 140 may be disposed between the barrier layer 150 and the channel layer 130, so that the device may have better performance. The nucleation layer 110 may be an aluminum nitride layer 160, the buffer layer 120 may be a gallium nitride layer, the channel layer 130 may be a gallium nitride layer, the insertion layer 140 may be an aluminum nitride layer 160, and the barrier layer 150 may be an aluminum gallium nitride layer. In addition, an aluminum nitride layer 160 may be disposed on the upper surface of the barrier layer 150, and the aluminum nitride layer 160 may serve as an etch stop layer signal trap for the P-type layer 170 while improving electron mobility.

In addition, when the device electrode is disposed in the active region 210, a plurality of transistor structures may be disposed, that is, the number of the drain electrode, the gate electrode 230 and the source electrode in the active region 210 is not limited, for example, as shown in fig. 5, two transistors are formed from the left to the right source electrode, the gate electrode 230, the drain electrode, the gate electrode 230 and the source electrode in the active region 210, and the two transistor structures are disposed in a manner of sharing the drain electrode, so that the device area can be effectively reduced.

The active device disposed in the active region 210 may be a depletion device or an enhancement device, for example, as shown in fig. 5 or 8, where a second P-type layer 172 is disposed in the active region 210 of the functional layer 180, and the second P-type layer 172 is located between the functional layer 180 and the gate electrode 230, so that the two-dimensional electron gas under the gate can be depleted by using the second P-type layer 172, thereby forming an enhancement type high electron mobility transistor. As shown in fig. 1 to 2, the first P-type layer 171 and the second P-type layer 172 may be etched by the entire P-type layer 170.

Alternatively, in order to make the source electrode and the drain electrode have better electrical properties, as shown in fig. 5, the source electrode and the drain electrode may each include an ohmic metal layer and an interconnection metal layer that are sequentially stacked, where the ohmic metal layer 241 of the source electrode and the ohmic metal layer 251 of the drain electrode may form ohmic contacts with the functional layer 180 respectively by way of high-temperature annealing, so as to establish electrical connection with two-dimensional electron gas at the channel. The interconnection metal layer 242 of the source electrode and the interconnection metal layer 252 of the drain electrode may be formed in the same process as the gate electrode 230.

In some embodiments, the ohmic metal layer 241 of the drain electrode and the source electrode may be a stacked metal, such as Ti/Al/Ni/Au or other metal combinations. The interconnect metal layer may be a laminated metal such as Ti/Al/Ni/Au or other metal combinations. The gate electrode 230 may be a laminated metal such as Ti/Al/Ni/Au or other metal combinations.

Alternatively, as shown in fig. 3 or fig. 7, the active region 210 of the functional layer 180 is provided with grooves 181 by etching, where the grooves 181 extend from a side surface (upper surface) of the functional layer 180 facing away from the substrate 100 to the heterojunction interface of the functional layer 180, and the number of the grooves 181 should be one-to-one corresponding to the sum of the numbers of source electrodes and drain electrodes in the active region 210, for example, two source electrodes and one drain electrode are provided in fig. 4, and accordingly, three grooves 181 need to be etched on the functional layer 180. As shown in fig. 4 or fig. 8, the ohmic metal layers 251 of the source electrode and the drain electrode may be correspondingly filled in the grooves 181, so that the ohmic metal layers 251 of the source electrode and the drain electrode may contact the two-dimensional electron gas at the heterojunction interface, thereby further improving the conduction performance between the source electrode and the drain electrode and the two-dimensional electron gas.

Alternatively, in order to enable the depletion region 220 to have a good isolation effect on the active region 210, the depletion region 220 may be disposed around the periphery of the active region 210. For example, as shown in fig. 9, a first P-type layer 171 having a zigzag shape is disposed at the periphery of the active region 210, so that a zigzag depletion region 220 is correspondingly formed, that is, the active region 210 in the inner ring is closed and isolated by the zigzag depletion region 220.

Optionally, as shown in fig. 8 and fig. 9, the first P-type layer 171 covers a part of the inactive area of the functional layer 180, so that the inactive area includes a depletion region 220 and a resistive region 260, where the resistive region 260 is isolated from the active region 210 by the depletion region 220, and correspondingly, a resistor may be disposed in the resistive region 260 of the functional layer 180, so as to implement an internal integrated resistor of the high electron mobility transistor, which helps to improve the device performance and reduce adverse effects such as parasitic inductance caused when the external resistor is connected to the device through a wire.

Alternatively, as shown in fig. 8 and 9, the resistor includes a two-dimensional electron gas resistor located in the resistive region 260 of the functional layer 180, where the two-dimensional electron gas resistor is formed, and when the definition of the depletion region 220 is achieved in the foregoing manner, the P-type layer 170 is removed in the resistive region 260, so that the two-dimensional electron gas of the functional layer 180 located in the resistive region 260 is retained in the resistive region 260, and the two-dimensional electron gas of the resistive region 260 is used as the two-dimensional electron gas resistor. In other embodiments, the resistor may also be a polysilicon resistor or a thin film resistor, and the specific form of the resistor is not limited in the present application.

In order to achieve good electrical connection, after the functional layer 180 is formed, the first metal portion 271 and the second metal portion 272 may be fabricated in the resistive region 260 of the functional layer 180, where the first metal portion 271 and the second metal portion 272 are disposed at intervals, and the first metal portion 271 and the second metal portion 272 may respectively form ohmic contact with the functional layer 180 of the resistive region 260, thereby achieving good electrical connection between the first metal portion 271 and the second metal portion 272 through the two-dimensional electron gas resistance of the resistive region 260. When the resistor is a two-dimensional electron gas resistor, the structure of the semiconductor device can be fully utilized to manufacture the resistor, so that the resistor can be integrated in the semiconductor device, and the volume of the semiconductor device is reduced.

In some embodiments, the first metal portion 271 and the second metal portion 272 may be fabricated in the same process step with the ohmic metal layer of the source and drain of the active region 210, as shown in fig. 7, when the functional layer 180 of the active region 210 is etched to form the recess 181, the functional layer 180 of the resistive region 260 may be simultaneously etched to form the resistive contact groove 182, and similarly, the resistive contact groove 182 may also extend from the surface of the functional layer 180 to the heterojunction interface, as shown in fig. 8, when the ohmic metal layer is filled in the recess 181, the first metal portion 271 and the second metal portion 272 may be simultaneously filled in the resistive contact groove 182, thereby, by annealing at a high temperature, the first metal portion 271 and the second metal portion 272 form good ohmic contact with the two-dimensional electron gas in the resistive region 260, respectively, and in subsequent interconnection, the resistive access may be realized through the first metal portion 271 and the second metal portion 272.

Optionally, the first P-type layer 171 is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer.

Alternatively, the thickness of the first P-type layer 171 is 20nm to 300nm, whereby effective removal of the two-dimensional electron gas can be ensured.

In another aspect of the embodiments of the present application, there is provided a method for manufacturing a high electron mobility transistor, the method including:

s010: a functional layer 180 having a heterojunction interface is epitaxially grown on the substrate 100, the functional layer 180 including an active region 210 and a non-active region.

S020: a P-type layer 170 is epitaxially grown on functional layer 180, P-type layer 170 covering active region 210 and inactive region.

S030: the P-type layer 170 is etched to form a first P-type layer 171 in the non-active region of the functional layer 180, and the first P-type layer 171 is used to remove the two-dimensional electron gas of the non-active region covered by the first P-type layer 171 to form the depletion region 220 correspondingly.

S040: a source electrode, a drain electrode, and a gate electrode 230 are formed in the active region 210 of the functional layer 180.

Therefore, the isolation function formed in the ion implantation or mesa etching process in the prior art is realized by arranging the first P-type layer 171 in the non-active region to form the depletion region 220, the barrier layer 150 and the channel layer 130 are not damaged while the isolation function is realized, the damage of crystal lattice and surface defect states is avoided, and compared with the ion implantation or mesa etching process, one photoetching process can be saved, so that the low cost is realized, and the process is simple.

In one method of preparation: as shown in fig. 1, a nucleation layer 110, a buffer layer 120, a channel layer 130, an insertion layer 140, a barrier layer 150, an aluminum nitride layer 160, and a P-type layer 170 are sequentially formed on a substrate 100 by epitaxial growth; as shown in fig. 2, the P-type layer 170 is patterned by photolithography and etching, so that a second P-type layer 172 located in the area of the gate electrode 230 is reserved in the active area 210 of the functional layer 180 and a first P-type layer 171 covering the non-active area is reserved, thereby removing the two-dimensional electron gas of the non-active area through the first P-type layer 171 to form a depletion region 220, so as to effectively isolate the active area 210, and the second P-type layer 172 can deplete the two-dimensional electron gas of the area under the gate, thereby realizing an enhanced device; as shown in fig. 3, a plurality of grooves 181 are formed by etching in the active region 210 of the functional layer 180; as shown in fig. 4, an ohmic metal layer is filled in each groove 181, and then a passivation layer is deposited on the surface of the device, wherein the passivation layer can be made of silicon nitride, silicon dioxide, aluminum nitride, aluminum oxide and the like, the thickness of the passivation layer can be 50nm to 1000nm, and then the surface of the passivation layer is subjected to planarization treatment; as shown in fig. 5, the ohmic metal layer 251 of the drain electrode, the ohmic metal layer 241 of the source electrode, and the second P-type layer 172 are respectively formed on the passivation layer at positions corresponding to the positions, and an interconnection metal layer is formed in each of the openings corresponding to the ohmic metal layer 251 of the drain electrode and the ohmic metal layer 241 of the source electrode, and a gate metal is formed in the opening corresponding to the second P-type layer 172 as the gate electrode 230.

In another preparation method: as shown in fig. 1, a nucleation layer 110, a buffer layer 120, a channel layer 130, an insertion layer 140, a barrier layer 150, an aluminum nitride layer 160, and a P-type layer 170 are sequentially formed on a substrate 100 by epitaxial growth; as shown in fig. 6, the P-type layer 170 is patterned by photolithography and etching, so that the second P-type layer 172 located in the gate electrode 230 is reserved in the active region 210 of the functional layer 180, the first P-type layer 171 is reserved in a part of the inactive region of the functional layer 180, and the P-type layer 170 of the resistive region 260 is removed; as shown in fig. 7, a plurality of grooves 181 are formed in the active region 210 of the functional layer 180, respectively, by etching, and a plurality of resistive contact grooves 182 are formed in the resistive region 260 of the functional layer 180; as shown in fig. 8 and 9, ohmic metal layers are respectively filled in each of the grooves 181 and ohmic metal layers are respectively filled in each of the resistive contact grooves 182 to serve as the first metal portions 271 and the second metal portions 272, respectively, whereby a resistor is formed in the resistive region 260, then a passivation layer is deposited on the device surface, and then the passivation layer surface is planarized; as shown in fig. 8, the ohmic metal layer 251 of the drain electrode, the ohmic metal layer 241 of the source electrode, and the second P-type layer 172 are respectively formed on the passivation layer at positions corresponding to the positions, and an interconnection metal layer is formed in each of the openings corresponding to the ohmic metal layer 251 of the drain electrode and the ohmic metal layer 241 of the source electrode, and a gate metal is formed in the opening corresponding to the second P-type layer 172 as the gate electrode 230.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. The high electron mobility transistor is characterized by comprising a substrate and a functional layer which is arranged on the substrate and provided with a heterojunction interface, wherein the functional layer comprises an active region and an inactive region, a first P-type layer is arranged in the inactive region of the functional layer and used for removing two-dimensional electron gas of the inactive region covered by the first P-type layer to form a depletion region correspondingly, and a source electrode, a drain electrode and a gate electrode are arranged in the active region of the functional layer.

2. The high electron mobility transistor of claim 1 wherein a second P-type layer is further disposed in the active region of the functional layer, the second P-type layer being located between the functional layer and the gate electrode.

3. The high electron mobility transistor of claim 1 wherein the source electrode and the drain electrode each comprise an ohmic metal layer and an interconnect metal layer disposed in sequence, the ohmic metal layer forming an ohmic contact with the functional layer.

4. The hemt of claim 3, wherein a recess is provided in an active region of said functional layer, said recess extending from a side surface of said functional layer facing away from said substrate to a heterojunction interface of said functional layer, said ohmic metal layer being located in said recess to be in gaseous contact with two-dimensional electrons at said heterojunction interface.

5. The hemt of claim 1, wherein said depletion region is disposed around the periphery of said active region.

6. The high electron mobility transistor according to any one of claims 1 to 5, wherein the inactive region of the functional layer includes a depletion region and a resistive region, and a resistor is further provided in the resistive region of the functional layer.

7. The hemt of claim 6, wherein first and second spaced apart metal portions are further provided in a resistive region of said functional layer, said resistor comprising a two-dimensional electron gas resistor with said functional layer in said resistive region, said first metal portion being electrically connected to said second metal portion by said two-dimensional electron gas resistor.

8. The hemt of claim 1, wherein said first P-type layer is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer.

9. The high electron mobility transistor of claim 1 wherein the first P-type layer has a thickness of 20nm to 300nm.

10. A method of manufacturing a high electron mobility transistor, the method comprising:

epitaxially growing a functional layer with a heterojunction interface on a substrate, wherein the functional layer comprises an active region and a non-active region;

epitaxially growing a P-type layer on the functional layer, wherein the P-type layer covers the active region and the inactive region;

etching the P-type layer to form a first P-type layer in the non-active region of the functional layer, wherein the first P-type layer is used for removing two-dimensional electron gas of the non-active region covered by the first P-type layer to correspondingly form a depletion region;

and forming a source electrode, a drain electrode and a gate electrode in the active region of the functional layer.

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