CN115995457A

CN115995457A - Test structure

Info

Publication number: CN115995457A
Application number: CN202111210782.8A
Authority: CN
Inventors: 郁扬; 王立柱; 刘旭; 王代平; 蔡燕飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-10-18
Filing date: 2021-10-18
Publication date: 2023-04-21

Abstract

A test structure, comprising: a substrate; a plurality of adjacent sample cells located on the substrate, each of the plurality of sample cells including a sample to be tested and a first wiring structure; and the wiring units are positioned on the substrate, each wiring unit comprises a second wiring structure, and the second wiring structure is connected with samples to be tested or the first wiring structures of two adjacent sample units. The test structure can be formed by performing unit splicing on the sample unit and the wiring unit according to the design rule, so that the structure is converted into a large number of repeatedly-testable circuits.

Description

Test structure

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular, to test structures.

Background

In semiconductor processing, back-end-of-line processes are typically used to connect individual transistors within a cell and to place and route between cells, including metal and conductive plugs. The effect of defects in the back-end-of-line process on the circuit is mainly two, one is that the open structure in the design is shorted, the reasons for which include that originally unconnected metals are linked up because of the defects. Another is that the structure that is connected in the design is broken, which includes the absence of metal in the process, and the absence of conductive plugs in contact with the metal. Therefore, knowing the quality of the back-end process is important in the semiconductor process, and reducing defects in the process can effectively improve yield and reduce cost.

In the prior art, various structures generating defects need to be realized through a layout, and the probability of generating defects of a certain structure needs to be further researched, so that the structures need to be repeated in a large amount, and the open circuit or short circuit state of the structures needs to be measured through a circuit. Conventional layout designs require an overall consideration of the arrangement of samples having a certain structure and the layout of their wiring.

However, in the above method, since the types of defects are many, the surrounding environment is complicated, it is very difficult to convert these structures into testable structures by wiring layout, and highly depending on design experience is required, and at the same time, the above method is low in design efficiency since the arrangement of the samples and the layout of the wirings thereof are required to be considered as a whole.

Disclosure of Invention

The invention solves the technical problem of providing a test structure, and only a defect structure possibly appearing in a single sample unit is needed to be designed, and the test structure is formed by splicing the sample unit, the wiring unit and the filling unit according to design rules, so that the structure is converted into a large number of repeatedly-testable circuits. In addition, the wiring unit and the sample unit are separated, so that the environment of the structure can be well reproduced, and the interference and influence of a test line can be avoided.

In order to solve the above technical problems, the technical solution of the present invention provides a test structure, including: a substrate; a plurality of adjacent sample cells located on the substrate, each of the plurality of sample cells including a sample to be tested and a first wiring structure; and the wiring units are positioned on the substrate, each wiring unit comprises a second wiring structure, and the second wiring structure is connected with samples to be tested or the first wiring structures of two adjacent sample units.

Optionally, the types of the plurality of sample units include: a first sample type and a second sample type; types of the number of wiring units include: a first wiring type corresponding to the first sample type, a second wiring type corresponding to the second sample type.

Optionally, when the type of the sample unit is a first sample type, the first wiring structure includes: the power supply conductive layers are arranged along a second direction, the third conductive layers are arranged along a first direction, and each third conductive layer is connected with the sample to be tested through 1 fourth conductive layer; the sample to be tested comprises an input end and an output end, and conductive plugs are arranged among the fourth conductive layers, the input end of the sample to be tested, the output end of the sample to be tested, the fourth conductive layers and the third conductive layers.

Optionally, when the type of the sample unit is a second sample type, the first wiring structure includes: the power supply conductive layers are arranged along the second direction, and each power supply conductive layer is connected with the sample to be tested through 1 fourth conductive layer; the sample to be tested comprises an input end and an output end, and conductive plugs are arranged among the fourth conductive layers, the input end of the sample to be tested, the output end of the sample to be tested, the fourth conductive layers and the power conductive layers.

Optionally, when the type of the wiring unit is a first wiring type, the second wiring structure includes: the power supply conductive layers are arranged along a second direction, the third conductive layers are arranged along the second direction, the third conductive layers are positioned between 2 power supply conductive layers along the second direction, and the third conductive layers are connected through the fourth conductive layers; and a conductive plug is arranged between each third conductive layer and each fourth conductive layer.

Optionally, when the type of the wiring unit is a second wiring type, the second wiring structure includes: 3 power supply conductive layers and 1 fourth conductive layer positioned on the power supply conductive layers, wherein the power supply conductive layers are arranged along the second direction; the first power conducting layer along the second direction is connected with the third power conducting layer along the second direction through the fourth conducting layer; and conductive plugs are arranged between the first power supply conductive layer and the fourth conductive layer along the second direction and between the third power supply conductive layer and the fourth conductive layer along the second direction.

Optionally, when the type of the sample unit is a first sample type, the sample units are arranged in an nxm array, and the connection method between the sample units and between the sample unit and the wiring unit includes: the second power conducting layer along the second direction in the sample unit of the nth row is overlapped with the first power conducting layer along the second direction in the sample unit of the (n+1) th row, wherein N is a natural number which is more than or equal to 1 and less than N; adjacent third conductive layers in adjacent sample cells of the same row are connected; adjacent power supply conductive layers in adjacent sample units in the same row are connected; the sample units and the wiring units are arranged along a first direction, the Mth sample unit of the 2i-1 th row and the Mth sample unit of the 2i th row are connected through one wiring unit, and the first sample unit of the 2i th row and the first sample unit of the 2i+1 th row are connected through one wiring unit, wherein i is a natural number which is more than or equal to 1 and less than N/2; adjacent sample units in the same row are connected with adjacent third conductive layers in the wiring units; adjacent sample cells in the same row are connected to adjacent power conducting layers in the wiring cells.

Optionally, when the type of the sample unit is the second sample type, the sample units are arranged in an n×m array, and the distance between two adjacent rows of sample units is the distance between two power supply conductive layers in the sample units; the connection method between the sample units and the wiring unit comprises the following steps: adjacent power supply conductive layers in adjacent sample units in the same row are connected; the sample units and the wiring units are arranged along a first direction, and the first sample unit in the ith row and the first sample unit in the (i+1) th row are connected through one wiring unit; the ith row of the Mth sample unit and the (i+1) th row of the Mth sample unit are electrically connected through a wiring unit, wherein i is a natural number which is more than or equal to 1 and less than N; adjacent sample cells in the same row are connected to adjacent power conducting layers in the wiring cells.

Optionally, the test structure further includes: the filling units are positioned on the substrate, and the filling units are used for filling the arranged gap positions according to the arrangement shapes of the sample units and the wiring units; the filling unit comprises 2 power supply conductive layers, and the 2 power supply conductive layers are distributed along a second direction.

Optionally, the intervals among the power supply conductive layers in the sample unit, the wiring unit and the filling unit are the same.

Optionally, the length of the sample to be measured is: 1-10 micrometers, wherein the width of the sample to be detected is as follows: 1-10 microns.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the test structure provided by the technical scheme of the invention, a plurality of adjacent sample units are positioned on a substrate, and each sample unit comprises a sample to be tested and a first wiring structure; and the wiring units are positioned on the substrate, each wiring unit comprises a second wiring structure, and the second wiring structure is connected with samples to be tested or the first wiring structures of two adjacent sample units. The technical scheme of the invention has simple design and convenient layout and wiring, and a test structure can be formed by carrying out unit splicing on the sample units and the wiring units according to the design rule only by designing a possibly-occurring defect structure in a single sample unit, thereby realizing the conversion of the structure into a large number of repeatedly-testable circuits. In addition, the wiring unit and the sample unit are separated, so that the environment of the structure can be well reproduced, and the interference and influence of a test line can be avoided. In addition, the layout structure is formed by unit splicing, so that the applicability of the technical scheme is strong, and the defect test can be performed by adopting the test structure of the technical scheme as long as the technical scheme accords with the standard digital unit architecture.

Drawings

FIG. 1 is a schematic diagram of a test structure;

FIG. 2 is a schematic diagram of another test structure;

FIG. 3 is a schematic diagram of a test structure according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first sample type according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a first wiring type according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a filling unit according to an embodiment of the invention;

FIG. 7 is a schematic diagram of a test structure according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a second sample type according to another embodiment of the present invention;

fig. 9 is a schematic diagram of a second wiring type structure according to another embodiment of the present invention;

fig. 10 is a schematic structural diagram of a filling unit according to another embodiment of the present invention.

Detailed Description

As described in the background art, since the defects are very various and the surrounding environment is complex, it is very difficult to convert these structures into testable structures by wiring layout, and it is necessary to highly depend on design experience, and at the same time, since it is necessary to consider the arrangement of the samples and the layout of the wirings thereof as a whole, the above-described method is low in design efficiency. The following detailed description refers to the accompanying drawings.

Fig. 1 is a schematic diagram of a test structure. A plurality of samples 100 to be tested are designed as short-circuited samples; a serial structure is formed among the plurality of samples 100 to be tested through a plurality of third conductive layers 103, power conductive layers 101 and power conductive layers 102; the third conductive layer 103 has conductive plugs 104 between the sample 100 to be tested, the power conductive layer 101 and the power conductive layer 102. The test method for the test structure of the embodiment comprises the following steps: connecting 1 first pad 105 to the power conducting layer 101, connecting 1 second pad 106 to the power conducting layer 102, applying a first voltage to the first pad 105, applying a second voltage to the second pad 106, wherein the first voltage is larger than the second voltage, judging whether open circuit defects exist in the plurality of samples 100 to be tested by testing current on the first pad 105, and if the current is 0 ampere, indicating that at least one of the plurality of samples 100 to be tested is open circuit; if the current is greater than 0 ampere, no one of the number of samples 100 under test is indicated as open.

Fig. 2 is a schematic diagram of another test structure. The plurality of samples 200 to be tested are designed as open-circuit samples; a parallel structure is formed among the plurality of samples 200 to be tested through a plurality of third conductive layers 203, power conductive layers 201 and power conductive layers 202; the third conductive layer 203 has conductive plugs 204 between the sample 200 to be tested, the power conductive layer 201 and the power conductive layer 202. The test method for the test structure of the embodiment comprises the following steps: connecting 1 first pad 205 to the power conducting layer 201, connecting 1 second pad 206 to the power conducting layer 202, applying a first voltage to the first pad 205, applying a second voltage to the second pad 206, wherein the first voltage is greater than the second voltage, determining whether a short circuit defect exists in the plurality of samples 200 to be tested by testing current on the first pad 205, and if the current is greater than 0 ampere, indicating that at least one of the plurality of samples 200 to be tested is short-circuited; if the current is 0 ampere, it indicates that none of the several samples 200 under test is shorted.

The test structure needs to integrally consider the arrangement of the samples to be tested and the layout of the wirings, has low design efficiency, and needs to perform design layout and wiring one by one. Also, because of the large variety of defects, the surrounding environment is complex, and it is very difficult to convert these structures into testable structures by wiring layout, requiring a high degree of design experience.

In order to solve the technical problem, an embodiment of the present invention provides a test structure, including: a plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; and the wiring units are positioned on the substrate, each wiring unit comprises a second wiring structure, and the second wiring structure is connected with samples to be tested or the first wiring structures of two adjacent sample units. The technical scheme of the invention has simple design and convenient layout and wiring, and a test structure can be formed by carrying out unit splicing on the sample units and the wiring units according to the design rule only by designing a possibly-occurring defect structure in a single sample unit, thereby realizing the conversion of the structure into a large number of repeatedly-testable circuits. In addition, the wiring unit and the sample unit are separated, so that the environment of the structure can be well reproduced, and the interference and influence of a test line can be avoided. In addition, the layout structure is formed by unit splicing, so that the defect test structure is high in applicability and can be used for performing the defect test as long as the defect test structure accords with a standard digital unit architecture.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

FIG. 3 is a schematic diagram of a test structure according to an embodiment of the invention.

Referring to fig. 3, a substrate; a plurality of adjacent sample cells 310 located on the substrate, each of the plurality of sample cells 310 including a sample 300 to be tested and a first wiring structure; and a plurality of wiring units 320 on the substrate, wherein each wiring unit 320 comprises a second wiring structure, and the second wiring structure is connected with the sample 300 to be tested or the first wiring structure of two adjacent sample units.

In this embodiment, the types of the plurality of sample units 310 are first sample types, and the types of the wiring units 320 are first wiring types corresponding to the first sample types.

In this embodiment, the length of the sample unit 310 is: 1-10 microns, the width of the sample unit 310 is: 1-10 microns; the length of the wiring unit 310 is: 1-10 micrometers, the width of the wiring unit 310 is: 1-10 microns; the length of the sample 300 to be measured is: 1-10 micrometers, the width of the sample 300 to be measured is: 1-10 microns.

The wiring unit is used for connecting the two sample units to form a test circuit.

FIG. 4 is a schematic diagram of a first sample type according to an embodiment of the present invention.

Referring to fig. 4, each of the plurality of sample units 310 includes a sample 300 to be tested and a first wiring structure. The first wiring structure includes: 2 power supply conductive layers 301, 2 third conductive layers 302 located on the same layer as the power supply conductive layers 301, and 2 fourth conductive layers 303 located on the power supply conductive layers 301, wherein the power supply conductive layers 301 are arranged along a second direction Y, the third conductive layers 302 are arranged along a first direction X, and each third conductive layer 302 is connected with the sample 300 to be tested through 1 fourth conductive layer 303; the sample 300 to be tested includes an input end and an output end, and conductive plugs 304 are respectively disposed between the fourth conductive layers 303 and the input end of the sample 300 to be tested, between the fourth conductive layers 303 and the output end of the sample 300 to be tested, and between the fourth conductive layers 303 and the third conductive layers 302. Each of the power conductive layers 301 has a space a therebetween.

In this embodiment, the sample 300 to be tested is designed as a short-circuited sample.

The power conducting layer 301 is used as a power wiring for simulating the real chip environment and conforming to the design rule of the digital unit. 2 different power voltages may be applied to the 2 power conductive layers 301, respectively.

In this embodiment, the width of the power conductive layer 301 is 40 nm to 500 nm, and the length of the power conductive layer 301 is 2 μm to 12 μm. The spacing a between the power conductive layers 301 is 100 nm to 10 μm.

The third conductive layer 302 is a metal wire for connecting the pad, the adjacent sample cell 310, or the adjacent wiring cell 320.

The fourth conductive layer 303 is used to connect the input end and the output end of the sample 300 to be tested with the third conductive layer 302.

In this embodiment, the width of the fourth conductive layer 303 is 20 nm to 500 nm, and the length of the fourth conductive layer 303 is 100 nm to 100 μm.

In this embodiment, the length and width of the conductive plugs 304 are 20 nm to 100 nm.

Fig. 5 is a schematic diagram of a first wiring type structure according to an embodiment of the present invention.

Referring to fig. 5, each of the wiring units 320 includes a second wiring structure including: 3 power supply conductive layers 301, 2 third conductive layers 302 located on the same layer as the power supply conductive layers 301, and 1 fourth conductive layer 303 located on the power supply conductive layers 301, wherein the power supply conductive layers 301 are arranged along a second direction Y, the third conductive layers 302 are arranged along the second direction Y, each third conductive layer 302 is located between 2 power supply conductive layers 301 along the second direction Y, and each third conductive layer 302 is connected through the fourth conductive layer 303; a conductive plug 304 is provided between each of the third conductive layer 302 and the fourth conductive layer 303. Each of the power conductive layers 301 has a space a therebetween.

The wiring unit 320 serves to connect two adjacent rows of 2 sample units 310, so that the pitch a of each power conductive layer 301 in the wiring unit 320 is the same as the pitch a of each power conductive layer 301 in the sample unit 310.

The third conductive layer 302 is a metal wire that is used to connect adjacent sample cells 310.

The fourth conductive layer 303 functions to connect 2 third conductive layers 302 in the wiring unit.

With continued reference to fig. 3, the sample units 310 are arranged in an nxm array, and the connection method between the sample units 310 and the wiring unit 320 includes: the second power conducting layer 301 along the second direction Y in the sample unit of the nth row is overlapped with the first power conducting layer 301 along the second direction in the sample unit of the n+1th row, wherein N is a natural number greater than or equal to 1 and less than N; adjacent third conductive layers 302 in adjacent sample cells 310 of the same row are connected; adjacent power conducting layers 301 in adjacent sample cells 310 of the same row are connected; the sample units 310 and the wiring units 320 are arranged along a first direction X, the 2i-1 th row of the Mth sample unit 310 and the 2 i-th row of the Mth sample unit 310 are connected through one wiring unit 320, and the 2 i-th row of the first sample unit 310 and the 2i+1-th row of the first sample unit 310 are connected through one wiring unit 320, wherein i is a natural number which is greater than or equal to 1 and less than N/2; adjacent sample cells 310 and adjacent third conductive layers 302 in wiring cells 320 of the same row are connected; adjacent sample cells 310 of the same row are connected to adjacent power conducting layers 301 in wiring cells 320.

With continued reference to fig. 3, the test structure of the present embodiment further includes: and a plurality of filling units 330 on the substrate, wherein the filling units 330 are used for filling the arranged gap positions according to the arrangement shapes of the sample units 310 and the wiring units 320.

Fig. 6 is a schematic structural diagram of a filling unit according to an embodiment of the invention.

Referring to fig. 6, the filling unit 330 includes 2 power conductive layers 301, and the 2 power conductive layers 301 are arranged along the second direction Y. Each of the power conductive layers 301 has a space a therebetween.

The purpose of the filler element 330 is to comply with digital cell design rules.

To meet the design rule of the digital unit, the pitches among the power conductive layers 310 in the sample unit 310, the wiring unit 320 and the filling unit 330 are the same.

With continued reference to fig. 3, the test method for the test structure according to the present embodiment includes: the third conductive layer 302 in the first row of the first sample unit 310 is connected to 1 first pad 315, the third conductive layer 302 in the nth row of the mth sample unit 310 is connected to 1 second pad 316, a first voltage is applied to the first pad 315, a second voltage is applied to the second pad 316, the first voltage is greater than the second voltage, by testing a current on the first pad 315, it is determined whether an open defect exists in the plurality of samples 300 to be tested, and if the current is 0 ampere, it is indicated that at least one sample 300 to be tested in the plurality of samples 300 to be tested is open; if the current is greater than 0 ampere, it indicates that none of the number of samples 300 under test 300 is open.

It should be noted that, the first pad 315 and the second pad 316 are only formed when the test structure is tested, and are not included in the layout design of the test structure. The first pad 315 and the second pad 316 serve as a voltage applying terminal and a testing terminal.

The test structure of the embodiment is simple in design and convenient in layout and wiring, and the test structure can be formed by performing unit splicing on the sample unit 310, the wiring unit 320 and the filling unit 330 according to design rules only by designing the sample 300 to be tested in the single sample unit 310 as a short-circuit sample, so that the structure is converted into a large number of repeatedly testable circuits. Also, since the wiring unit 320 and the sample unit 310 are separated, the environment of the structure can be well reproduced without being disturbed and affected by the test line. In addition, because the test structure of the embodiment forms a layout structure through unit splicing, the test structure has strong applicability, and can be used for testing defects as long as the test structure accords with a standard digital unit architecture.

FIG. 7 is a schematic diagram of a test structure according to another embodiment of the present invention.

Referring to fig. 7, a substrate; a plurality of adjacent sample units 410 located on the substrate, each of the plurality of sample units 410 including a sample 400 to be tested and a first wiring structure; and a plurality of wiring units 420 on the substrate, wherein each wiring unit 420 comprises a second wiring structure, and the second wiring structure is connected with the sample 400 to be tested or the first wiring structure of two adjacent sample units.

In this embodiment, the types of the plurality of sample units 410 are second sample types, and the types of the wiring units 420 are second wiring types corresponding to the second sample types.

In this embodiment, the length of the sample unit 410 is: 1-10 microns, the width of the sample unit 410 is: 1-10 microns; the length of the wiring unit 410 is: 1-10 microns, the width of the wiring unit 410 is: 1-10 microns; the length of the sample 400 to be measured is: 1-10 micrometers, the width of the sample 400 to be measured is: 1-10 microns.

FIG. 8 is a schematic diagram of a second sample type according to another embodiment of the present invention.

Referring to fig. 8, each of the plurality of sample units 410 includes a sample 400 to be tested and a first wiring structure. The first wiring structure includes: 2 power supply conductive layers 401, and 2 fourth conductive layers 403 located on the power supply conductive layers 401, wherein the 2 power supply conductive layers 401 are arranged along the second direction Y, and each power supply conductive layer 401 is connected with the sample 400 to be tested through 1 fourth conductive layer 403; the sample 400 to be tested includes an input end and an output end, and conductive plugs 404 are disposed between each of the fourth conductive layers 403 and the input end of the sample 400 to be tested, each of the fourth conductive layers 403 and the output end of the sample 400 to be tested, and each of the fourth conductive layers 403 and the power conductive layers 401. Each of the power conductive layers 401 has a space a therebetween.

In this embodiment, the sample 400 to be tested is designed as an open-circuit sample.

The power conducting layer 401 is used as a power wiring for simulating the real chip environment and conforming to the design rule of the digital unit. 2 different power voltages may be applied to the 2 power conductive layers 401, respectively.

In this embodiment, the width of the power conductive layer 401 is 40 nm to 500 nm, and the length of the power conductive layer 401 is 2 micrometers to 12 micrometers. The spacing a between the power conductive layers 401 is 100 nm to 10 μm.

The fourth conductive layer 403 is used to connect the input end and the output end of the sample 400 to be tested with the power conductive layer 401.

In this embodiment, the width of the fourth conductive layer 403 is 20 nm to 500 nm, and the length of the fourth conductive layer 403 is 100 nm to 100 μm.

In this embodiment, the length and width of the conductive plugs 404 are 20 nm to 100 nm.

Fig. 9 is a schematic diagram of a second wiring type structure according to another embodiment of the present invention.

Referring to fig. 9, each of the wiring units 420 includes a second wiring structure including: 3 power supply conductive layers 401, and 1 fourth conductive layer 403 located on the power supply conductive layers 401, wherein the power supply conductive layers 401 are arranged along a second direction Y; a first one of the power supply conductive layers 401 in the second direction Y and a third one of the power supply conductive layers 401 in the second direction Y are connected by the fourth conductive layer 403; a first one of the power conductive layers 401 and the fourth conductive layer 403 along the second direction Y, and a third one of the power conductive layers 401 and the fourth conductive layer 403 along the second direction Y have a conductive plug 404 therebetween. Each of the power conductive layers 401 has a space a therebetween.

The wiring unit 420 serves to connect two adjacent rows of 2 sample units 410, so that the pitch a of each power conductive layer 401 in the wiring unit 420 is the same as the pitch a of each power conductive layer 401 in the sample unit 410.

The fourth conductive layer 403 serves to connect the first power conductive layer 401 in the second direction Y and the third power conductive layer 401 in the second direction Y in the wiring unit 420.

With continued reference to fig. 7, the sample units 410 are arranged in an nxm array, and the distance between two adjacent rows of sample units 410 is the distance a between two power conductive layers 401 in the sample units 410; the connection method between the sample units 410 and the wiring unit 420 includes: adjacent power conductive layers 401 in adjacent sample cells 410 of the same row are connected; the sample cells 410 and the wiring cells 420 are arranged in the first direction X, and the i-th row of the first sample cells 410 and the i+1-th row of the first sample cells 410 are connected by one wiring cell 420; the ith row of the mth sample cell 410 and the (i+1) th row of the mth sample cell 410 are electrically connected by one wiring unit 420, wherein i is a natural number greater than or equal to 1 and less than N; adjacent sample cells 410 of the same row are connected to adjacent power conducting layers 401 in wiring units 420.

With continued reference to fig. 7, the test structure of the present embodiment further includes: and a plurality of filling units 430 on the substrate, wherein the filling units 430 are used to fill the arranged gap positions according to the arrangement shapes of the sample units 410 and the wiring units 420.

Referring to fig. 10, the filling unit 430 includes 2 power conductive layers 401, and the 2 power conductive layers 401 are arranged along the second direction Y. Each of the power conductive layers 401 has a space a therebetween.

The purpose of the filler element 430 is to comply with digital element design rules.

To meet the digital cell design rules, the spacing between the power conductive layers 410 in the sample cell 410, the routing cell 420, and the fill cell 430 is the same.

With continued reference to fig. 7, the test method for the test structure according to the present embodiment includes: connecting 1 first pad 415 on a first power conductive layer 401 along a second direction Y, connecting 1 second pad 416 on a last power conductive layer 401 along the second direction Y, applying a first voltage on the first pad 415, applying a second voltage on the second pad 416, wherein the first voltage is larger than the second voltage, judging whether short circuit defects exist in the plurality of samples 400 to be tested by testing current on the first pad 415, and if the current is larger than 0 ampere, indicating that at least one sample 400 to be tested in the plurality of samples 400 to be tested is short-circuited; if the current is 0 ampere, it indicates that none of the number of samples 400 to be tested 400 is shorted.

It should be noted that, the first pad 415 and the second pad 416 are only formed when the test structure is tested, and are not included in the layout design of the test structure. The first pad 415 and the second pad 416 serve as a voltage applying terminal and a testing terminal.

The test structure of the embodiment is simple in design and convenient in layout and wiring, and the test structure can be formed by performing unit splicing on the sample unit 410, the wiring unit 420 and the filling unit 430 according to design rules only by designing the sample 400 to be tested in the single sample unit 410 as an open-circuit sample, so that the structure is converted into a large number of repeatedly testable circuits. Also, since the wiring unit 420 and the sample unit 410 are separated, the environment of the structure can be well reproduced without being disturbed and affected by the test line. In addition, because the test structure of the embodiment forms a layout structure through unit splicing, the test structure has strong applicability, and can be used for testing defects as long as the test structure accords with a standard digital unit architecture.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A test structure, comprising:

a substrate;

a plurality of adjacent sample cells located on the substrate, each of the plurality of sample cells including a sample to be tested and a first wiring structure;

and the wiring units are positioned on the substrate, each wiring unit comprises a second wiring structure, and the second wiring structure is connected with samples to be tested or the first wiring structures of two adjacent sample units.

2. The test structure of claim 1, wherein the types of the plurality of sample units comprise: a first sample type and a second sample type; types of the number of wiring units include: a first wiring type corresponding to the first sample type, a second wiring type corresponding to the second sample type.

3. The test structure of claim 2, wherein when the type of sample cell is a first sample type, the first wiring structure comprises: the power supply conductive layers are arranged along a second direction, the third conductive layers are arranged along a first direction, and each third conductive layer is connected with the sample to be tested through 1 fourth conductive layer; the sample to be tested comprises an input end and an output end, and conductive plugs are arranged among the fourth conductive layers, the input end of the sample to be tested, the output end of the sample to be tested, the fourth conductive layers and the third conductive layers.

4. The test structure of claim 2, wherein when the type of sample cell is a second sample type, the first wiring structure comprises: the power supply conductive layers are arranged along the second direction, and each power supply conductive layer is connected with the sample to be tested through 1 fourth conductive layer; the sample to be tested comprises an input end and an output end, and conductive plugs are arranged among the fourth conductive layers, the input end of the sample to be tested, the output end of the sample to be tested, the fourth conductive layers and the power conductive layers.

5. The test structure of claim 2, wherein when the type of wiring unit is a first wiring type, the second wiring structure comprises: the power supply conductive layers are arranged along a second direction, the third conductive layers are arranged along the second direction, the third conductive layers are positioned between 2 power supply conductive layers along the second direction, and the third conductive layers are connected through the fourth conductive layers; and a conductive plug is arranged between each third conductive layer and each fourth conductive layer.

6. The test structure of claim 2, wherein when the type of wiring unit is a second wiring type, the second wiring structure comprises: 3 power supply conductive layers and 1 fourth conductive layer positioned on the power supply conductive layers, wherein the power supply conductive layers are arranged along the second direction; the first power conducting layer along the second direction is connected with the third power conducting layer along the second direction through the fourth conducting layer; and conductive plugs are arranged between the first power supply conductive layer and the fourth conductive layer along the second direction and between the third power supply conductive layer and the fourth conductive layer along the second direction.

7. The test structure of claim 2, wherein when the type of the sample unit is a first sample type, the sample units are arranged in an nxm array, and the connection method between the sample units, between the sample unit and the wiring unit comprises: the second power conducting layer along the second direction in the sample unit of the nth row is overlapped with the first power conducting layer along the second direction in the sample unit of the (n+1) th row, wherein N is a natural number which is more than or equal to 1 and less than N; adjacent third conductive layers in adjacent sample cells of the same row are connected; adjacent power supply conductive layers in adjacent sample units in the same row are connected; the sample units and the wiring units are arranged along a first direction, the Mth sample unit of the 2i-1 th row and the Mth sample unit of the 2i th row are connected through one wiring unit, and the first sample unit of the 2i th row and the first sample unit of the 2i+1 th row are connected through one wiring unit, wherein i is a natural number which is more than or equal to 1 and less than N/2; adjacent sample units in the same row are connected with adjacent third conductive layers in the wiring units; adjacent sample cells in the same row are connected to adjacent power conducting layers in the wiring cells.

8. The test structure of claim 2, wherein when the sample unit is of a second sample type, the sample units are arranged in an nxm array, and a distance between two adjacent rows of sample units is a distance between two power conductive layers in the sample units; the connection method between the sample units and the wiring unit comprises the following steps: adjacent power supply conductive layers in adjacent sample units in the same row are connected; the sample units and the wiring units are arranged along a first direction, and the first sample unit in the ith row and the first sample unit in the (i+1) th row are connected through one wiring unit; the ith row of the Mth sample unit and the (i+1) th row of the Mth sample unit are electrically connected through a wiring unit, wherein i is a natural number which is more than or equal to 1 and less than N; adjacent sample cells in the same row are connected to adjacent power conducting layers in the wiring cells.

9. The test structure of claim 1, wherein the test structure further comprises: the filling units are positioned on the substrate, and the filling units are used for filling the arranged gap positions according to the arrangement shapes of the sample units and the wiring units; the filling unit comprises 2 power supply conductive layers, and the 2 power supply conductive layers are distributed along a second direction.

10. The test structure of claim 9, wherein the spacing between the power conducting layers in the sample cell, the routing cell, and the fill cell is the same.

11. The test structure of claim 1, wherein the length of the sample to be tested is: 1-10 micrometers, wherein the width of the sample to be detected is as follows: 1-10 microns.