CN117672888A - Semiconductor structure, forming method, layout design method, circuit and working method - Google Patents

Semiconductor structure, forming method, layout design method, circuit and working method Download PDF

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Publication number
CN117672888A
CN117672888A CN202211042640.XA CN202211042640A CN117672888A CN 117672888 A CN117672888 A CN 117672888A CN 202211042640 A CN202211042640 A CN 202211042640A CN 117672888 A CN117672888 A CN 117672888A
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China
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circuit
edge
layer
wiring
metal
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Inventor
郁扬
王代平
于海洋
钱茂程
蔡燕飞
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202211042640.XA priority Critical patent/CN117672888A/en
Publication of CN117672888A publication Critical patent/CN117672888A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor structure, a forming method, a layout design method, a circuit and a working method, the structure comprises: a substrate comprising a middle region and an edge region located around the middle region; a plurality of layers of vertically stacked first and second metal layers located on the intermediate region, the first metal layer being parallel to a first direction, the second metal layer being parallel to a second direction, the first and second directions being parallel to a surface of the substrate, and the first and second directions being mutually perpendicular; the edge circuit unit comprises a short circuit unit or an open circuit unit, the edge circuit unit comprises at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the top surface of the metal structure is flush with the top surface of the first metal layer. The semiconductor structure improves the utilization rate of the chip.

Description

Semiconductor structure, forming method, layout design method, circuit and working method
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure, a method for forming the same, a layout design method, a circuit and a working method.
Background
As the size of semiconductor process nodes is reduced, the size and pitch of structures such as metal, vias, etc. are reduced, and new processes such as Self-aligned Double/Quadruple Pattern (SADP/SADP) are introduced to fabricate these structures, which are very complex, and have many defects at the line end (line end), corresponding to the edges of the chip, so that a margin area needs to be left at the edges of the chip to ensure the normal operation of the internal non-edge area.
There are two effects of these defects on the circuit, one is that the open structure in the design shorts out, which may be due to the fact that originally unconnected metals are linked up by the defect, etc. Another is that the structure that is connected in the design breaks, which may be due to metal missing in the process, or via not in contact with metal, etc.
Leaving margin at the edges of the chip can result in an increase in area of the chip, with the extra area increase caused by the margin being considerable for some complex, memory-rich chips.
Therefore, process monitoring of the chip edge is important.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure, a forming method, a layout design method, a circuit and a working method, so as to monitor the process of the edge of a chip.
In order to solve the above technical problems, the present invention provides a semiconductor structure, including: a substrate comprising a middle region and an edge region located around the middle region; a plurality of layers of vertically stacked first and second metal layers located on the intermediate region, the first metal layer being parallel to a first direction, the second metal layer being parallel to a second direction, the first and second directions being parallel to a surface of the substrate, and the first and second directions being mutually perpendicular; the edge circuit unit comprises a short circuit unit or an open circuit unit, the edge circuit unit comprises at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the metal structure is flush with the top surface of the first metal layer.
Optionally, the plurality of edge circuit units are located on edge regions on two sides of the middle region along the first direction, and the plurality of edge circuit units are arranged on the edge regions along the second direction.
Optionally, the edge circuit unit includes a short circuit unit; the metal structure comprises: the first input end, the first output end, the first power end, the first grounding end and a plurality of third metal layers; the short circuit unit further includes: a first plug on the third metal layer, on the first input end or on the first output end, a first connection layer on the first plug, the first connection layer being perpendicular to the third metal layer; the first connecting layer is electrically connected with the first input end, the first output end and the third metal layers, and a circuit between the first input end and the first output end is a short circuit.
Optionally, the manner in which the plurality of short-circuit units are connected is as follows: in the series connection mode, the first input end of the former short circuit unit is connected with the first output end of the latter short circuit unit.
Optionally, the first input terminal of the previous short-circuit unit is connected to the first output terminal of the next short-circuit unit through a first wiring unit, and the first wiring unit includes: the first wiring layer is connected with the first input end, the second wiring layer is connected with the first output end, the third wiring layer is electrically connected with the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are parallel to the first metal layer, and the third wiring layer is parallel to the first connecting layer.
Optionally, the first wiring unit further includes: the fourth power end is connected with the first power end, and the fourth grounding end is connected with the first grounding end, and the fourth power end and the fourth grounding end are parallel to the first metal layer.
Optionally, the method further comprises: a fifth power terminal and a fifth ground terminal on the middle region, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the first power end is connected with a fifth power end of the middle area through a first wiring unit, and the first grounding end is connected with a fifth grounding end of the middle area through the first wiring unit.
Optionally, the edge circuit unit includes an open circuit unit; the metal structure comprises: the second power end, the second grounding end and a plurality of fourth metal layers and fifth metal layers which are alternately arranged; the open circuit unit further includes: the second plug is positioned on the fourth metal layer and the second power end, the third plug is positioned on the fifth metal layer and the second grounding end, the second connecting layer is positioned on the second plug, the third connecting layer is positioned on the third plug, the fourth metal layer is vertical to the second connecting layer, and the fifth metal layer is vertical to the third connecting layer; the second connecting layer is electrically connected with the fourth metal layer and the second power supply end, the third connecting layer is electrically connected with the fifth metal layer and the second grounding end, and a circuit between the second grounding end and the second power supply end is an open circuit.
Optionally, the connection manner of the open circuit units is as follows: in a parallel mode, the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.
Optionally, the plurality of open circuit units are connected by a second wiring unit, the second wiring unit including: the fourth wiring layer is connected with the second power end, the fifth wiring layer is connected with the second grounding end, the sixth wiring layer is electrically connected with the fourth wiring layers, the seventh wiring layer is electrically connected with the fifth wiring layers, the fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and the seventh wiring layer are parallel to the second connecting layer.
Optionally, the method further comprises: a fifth power terminal and a fifth ground terminal on the middle region, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the second power end is connected with a fifth power end of the middle area through a second wiring unit, and the second grounding end is connected with a fifth grounding end of the middle area through the second wiring unit.
Optionally, the method further comprises: a plurality of filling units for filling voids of an edge region, the filling units comprising: the third power end and the third grounding end are parallel to the first metal layer, the third power end is connected with the first power end, and the third grounding end is connected with the first grounding end.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a middle region and an edge region positioned around the middle region; forming a plurality of vertically stacked first metal layers and second metal layers on the intermediate region, wherein the first metal layers are parallel to a first direction, the second metal layers are parallel to a second direction, the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction are mutually perpendicular; and forming a plurality of connected edge circuit units on the edge area, wherein the edge circuit units comprise short circuit units or open circuit units, the edge circuit units comprise at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the top surface of the metal structure is flush with the top surface of the first metal layer.
Optionally, the metal structure is formed simultaneously with the first metal layer; the edge circuit units are positioned on the edge areas on two sides of the middle area along the first direction, and the edge circuit units are arranged on the edge areas along the second direction.
Optionally, the edge circuit unit includes a short circuit unit; the metal structure comprises: the first input end, the first output end, the first power end, the first grounding end and a plurality of third metal layers; the short circuit unit further includes: a first plug on the third metal layer, on the first input end or on the first output end, a first connection layer on the first plug, the first connection layer being perpendicular to the third metal layer; the first connecting layer is electrically connected with the first input end, the first output end and the third metal layers, and a circuit between the first input end and the first output end is a short circuit.
Optionally, the manner in which the plurality of short-circuit units are connected is as follows: in the series connection mode, the first input end of the former short circuit unit is connected with the first output end of the latter short circuit unit.
Optionally, the first input terminal of the previous short-circuit unit is connected to the first output terminal of the next short-circuit unit through a first wiring unit, and the first wiring unit includes: the first wiring layer is connected with the first input end, the second wiring layer is connected with the first output end, the third wiring layer is electrically connected with the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are parallel to the first metal layer, and the third wiring layer is parallel to the first connecting layer.
Optionally, the first connection layer is formed simultaneously with the second metal layer.
Optionally, the edge circuit unit includes an open circuit unit; the metal structure comprises: the second power end, the second grounding end and a plurality of fourth metal layers and fifth metal layers which are alternately arranged; the open circuit unit further includes: the second plug is positioned on the fourth metal layer and the second power end, the third plug is positioned on the fifth metal layer and the second grounding end, the second connecting layer is positioned on the second plug, the third connecting layer is positioned on the third plug, the fourth metal layer is vertical to the second connecting layer, and the fifth metal layer is vertical to the third connecting layer; the second connecting layer is electrically connected with the fourth metal layer and the second power supply end, the third connecting layer is electrically connected with the fifth metal layer and the second grounding end, and a circuit between the second grounding end and the second power supply end is an open circuit.
Optionally, the connection manner of the open circuit units is as follows: in a parallel mode, the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.
Optionally, the plurality of open circuit units are connected by a second wiring unit, the second wiring unit including: the fourth wiring layer is connected with the second power end, the fifth wiring layer is connected with the second grounding end, the sixth wiring layer is electrically connected with the fourth wiring layers, the seventh wiring layer is electrically connected with the fifth wiring layers, the fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and the seventh wiring layer are parallel to the second connecting layer.
Optionally, the second connection layer and the third connection layer are formed simultaneously with the second metal layer.
Optionally, the method further comprises: forming a plurality of filling units for filling voids in the edge region, the filling units comprising: the third power supply end and the third grounding end are parallel to the first metal layer.
Correspondingly, the technical scheme of the invention also provides an edge monitoring circuit, which comprises: a plurality of connected edge circuit units.
Optionally, the edge circuit unit includes a short circuit unit; the mode that a plurality of short-circuit units are connected is the series connection mode.
Optionally, the short-circuit unit includes a first input end and a first output end, and a circuit between the first input end and the first output end is a short-circuit; the first input end of the former short-circuit unit is connected with the first output end of the latter short-circuit unit.
Optionally, the edge circuit unit includes an open circuit unit; the open circuit units are connected in parallel.
Optionally, the open circuit unit includes: the circuit between the second grounding end and the second power end is an open circuit; the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.
Correspondingly, the technical scheme of the invention also provides a working method of the edge monitoring circuit, which comprises the following steps: providing an edge monitoring circuit, the edge monitoring circuit comprising: a plurality of connected edge circuit units; after the edge monitoring circuit is electrified, judging whether the edge monitoring circuit is in a short circuit or open circuit state; judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit, and overhauling the edge monitoring circuit if the edge monitoring circuit is abnormal.
Optionally, the edge circuit unit includes a short circuit unit; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is required.
Optionally, the edge circuit unit includes an open circuit unit; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is needed.
Correspondingly, the technical scheme of the invention also provides a semiconductor layout design method, which comprises the following steps: the layout comprises a middle area and edge areas positioned around the middle area; providing an edge circuit unit; and a plurality of connected edge circuit units are arranged in the edge area.
Optionally, the edge circuit unit includes a short circuit unit; the mode that a plurality of short-circuit units are connected is the series connection mode.
Optionally, the edge circuit unit includes an open circuit unit; the open circuit units are connected in parallel.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the semiconductor structure, a plurality of connected edge circuit units are arranged on an edge area. The structure of the edge circuit unit is known, so that the environment at the edge of the chip can be well realized, the edge defect can be conveniently studied, meanwhile, the circuit at the edge of the chip can be utilized, and the area utilization rate of the chip is improved; in addition, the structure of the edge circuit unit is repeated, so that the layout and the wiring at the edge of the chip are convenient, the constraint can be carried out by using fewer design rules, and the circuit with the scannable and testable edge structure can be realized; the edge circuit unit has simple structure and strong applicability, and can be used for measuring the back-end process only by conforming to the standard digital unit architecture, thereby being applicable to each node of the mature process and the advanced process.
Further, the plurality of edge circuit units are connected through the first wiring unit or the second wiring unit. The wiring unit is separated from the edge circuit unit, the environment of the chip edge structure can be well reproduced, and the wiring unit is not interfered and influenced by the test circuit.
Further, the first power end is connected with a fifth power end of the middle area through a first wiring unit, and the first grounding end is connected with a fifth grounding end of the middle area through the first wiring unit; the second power end is connected with the fifth power end of the middle area through a second wiring unit, and the second grounding end is connected with the fifth grounding end of the middle area through a second wiring unit. Therefore, scanning research can be performed in non-edge areas such as the middle area of the chip, and the area of the chip is not wasted.
According to the working method of the edge monitoring circuit, whether the edge monitoring circuit is normal or not is judged, and if the edge monitoring circuit is abnormal, the edge monitoring circuit is overhauled. And if the edge monitoring circuit is normal, utilizing the edge monitoring circuit.
Drawings
FIGS. 1-4 are top views of a semiconductor structure in accordance with one embodiment of the present invention;
fig. 5-7 are top views of semiconductor structures in accordance with another embodiment of the present invention;
FIGS. 8-10 are schematic diagrams of an edge monitoring circuit according to an embodiment of the invention;
FIGS. 11-13 are schematic diagrams of an edge monitoring circuit according to another embodiment of the invention;
FIG. 14 is a flow chart of a method of operation of the edge monitoring circuit in accordance with an embodiment of the present invention;
fig. 15 is a flow chart of a semiconductor layout design method in an embodiment of the invention.
Detailed Description
As described in the background, process monitoring of the chip edge is important.
Specifically, the process at the edge of the chip monitors the Metal and the Via hole, most of which are the middle-back stage process, and the detection content is open circuit and short circuit, so that the test circuit is relatively simple, and the number of corresponding layers prepared on the process is relatively small, and the number of the corresponding layers is usually two Metal layers and one Via hole layer, such as Metal1, metal2 and Via1. Thus, the manufacturing process is simpler, and the processing and testing can be completed rapidly. But has the disadvantage that no addressable circuits requiring transistors can be designed without the front-end process.
In the conventional method, a designer needs to implement various structures generating defects through a layout, simulate the surrounding environment of the defects in a certain area, and try to change the environment. It is further necessary to study the probability of defects occurring in a structure, and to repeat such a structure in a large number and measure its open or short circuit state by a circuit. However, a large number of repetitions of the structure may result in a change in the originally designed edge environment, and the boundaries of the chip may no longer be bordered. Meanwhile, defects at the boundary of the chip are various, the environment is complex, the experience of a designer is highly depended, the design layout and wiring are required to be carried out one by one, and the design efficiency is low.
In order to solve the above problems, the technical scheme of the invention provides a semiconductor structure, a forming method, a layout design method, a circuit and a working method, wherein a plurality of connected edge circuit units are arranged on an edge area. The structure of the edge circuit unit is known, so that the environment at the edge of the chip can be well realized, the edge defect can be conveniently studied, meanwhile, the circuit at the edge of the chip can be utilized, and the area utilization rate of the chip is improved; in addition, the structure of the edge circuit unit is repeated, so that the layout and the wiring at the edge of the chip are convenient, the constraint can be carried out by using fewer design rules, and the circuit with the scannable and testable edge structure can be realized; the edge circuit unit has simple structure and strong applicability, and can be used for measuring the back-end process only by conforming to the standard digital unit architecture, thereby being applicable to each node of the mature process and the advanced process.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1-4 are top views of semiconductor structures in accordance with an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided, which includes a middle region I and an edge region II located around the middle region I.
The edge region II surrounds the intermediate region I, only a part of the edge region II lying in the first direction X being schematically shown.
With continued reference to fig. 1, a plurality of vertically stacked first metal layers (not shown) and second metal layers (not shown) are formed on the intermediate region I, wherein the first metal layers are parallel to a first direction X, the second metal layers are parallel to a second direction Y, the first direction X and the second direction Y are parallel to the surface of the substrate 100, and the first direction X and the second direction Y are perpendicular to each other.
The first direction X and the second direction Y are horizontal directions and vertical directions which are fixed when the semiconductor layout is designed, and based on the setting of the directions, the direction designs of the first metal layer and the second metal layer in the semiconductor structure also need to meet the design rule, namely, the first metal layer needs to be parallel to the first direction X, and the second metal layer needs to be parallel to the second direction Y.
In this embodiment, further comprising: a fifth power terminal 120 and a fifth ground terminal 121 are formed on the intermediate region I in parallel to the first direction X.
With continued reference to fig. 1 and 2, fig. 2 is a schematic structural diagram of the single edge circuit unit in fig. 1, in which a plurality of connected edge circuit units are formed on an edge region II, the edge circuit units include one or more layers of metal structures, the metal structures are parallel to the first metal layer, and top surfaces of the metal structures are level with top surfaces of the first metal layer. The edge circuit unit is used for monitoring defects of products.
In this embodiment, the metal structure is formed simultaneously with the first metal layer.
The edge circuit units are located on edge areas II on two sides of the middle area I along the first direction X, and the edge circuit units are arranged on the edge areas II along the second direction Y.
In this embodiment, the edge circuit unit includes a short circuit unit. The short-circuit unit is a unit of a short-circuit.
In this embodiment, the metal structure includes: a first input terminal 101, a first output terminal 102, a first power terminal 103, a first ground terminal 104, and a number of third metal layers 105.
In this embodiment, the first power terminal 103 is connected to the fifth power terminal 120 of the intermediate area I through a first wiring unit, and the first ground terminal 104 is connected to the fifth ground terminal 121 of the intermediate area I through a first wiring unit. Therefore, scanning research can be performed in non-edge areas such as the middle area of the chip, and the area of the chip is not wasted.
In this embodiment, the short circuit unit further includes: a first plug (not shown) on the third metal layer 105, on the first input terminal 101 or on the first output terminal 102, a first connection layer 106 on the first plug, the first connection layer 106 being perpendicular to the third metal layer 105.
In this embodiment, the first connection layer 106 is formed simultaneously with the second metal layer.
The first connection layer 106 is electrically connected to the first input end 101, the first output end 102 and the plurality of third metal layers 105, and a circuit between the first input end 101 and the first output end 102 is a short circuit.
In this embodiment, the manner in which the plurality of short-circuit units are connected is as follows: in series, the first input 101 of the preceding shorting cell is connected to the first output 102 of the following shorting cell.
Referring to fig. 1 and 3, fig. 3 is a schematic structural diagram of a single first wiring unit in fig. 1, in this embodiment, a first input terminal 101 of a previous shorting unit is connected to a first output terminal 102 of a subsequent shorting unit through the first wiring unit, where the first wiring unit includes: a first wiring layer 110 connected to the first input terminal 101, a second wiring layer 111 connected to the first output terminal 102, and a third wiring layer 112 electrically connecting the first wiring layer 110 and the second wiring layer 111, the first wiring layer 110 and the second wiring layer 111 being parallel to the first metal layer, the third wiring layer 112 being parallel to the first connection layer 106.
The third wiring layers 112 at both ends of the second direction Y are respectively connected with external circuits to apply voltage to monitor the effect of the series connection of the plurality of short-circuit units.
With continued reference to fig. 1 and 3, in this embodiment, the first wiring unit further includes: a fourth power terminal 113 connected to the first power terminal 103, and a fourth ground terminal 114 connected to the first ground terminal 104, the fourth power terminal 113 and the fourth ground terminal 114 being parallel to the first metal layer.
In this embodiment, the first power terminal 103 is connected to the fifth power terminal 120 of the intermediate area I through the fourth power terminal 113 of the first wiring unit, and the first ground terminal 104 is connected to the fifth ground terminal 121 of the intermediate area I through the fourth ground terminal 114 of the first wiring unit. Therefore, scanning research can be performed in non-edge areas such as the middle area of the chip, and the area of the chip is not wasted.
The first wiring unit is separated from the short-circuit unit, and the environment of the chip edge structure can be well reproduced without being interfered and influenced by the test circuit.
Referring to fig. 1 and fig. 4, fig. 4 is a schematic structural diagram of a single filling unit, and the method for forming a semiconductor structure further includes: forming a plurality of filling units for filling the gaps of the edge region II, the filling units comprising: the third power supply terminal 130 and the third ground terminal 131 are parallel to the first metal layer, the third power supply terminal 130 is connected to the first power supply terminal 103, and the third ground terminal 131 is connected to the first ground terminal 104.
The third power terminal 130 and the third ground terminal 131 are formed simultaneously with the first metal layer.
Correspondingly, the embodiment of the invention also provides the semiconductor structure as shown in fig. 1 to 4.
And a plurality of connected edge circuit units are arranged on the edge zone II. The structure of the edge circuit unit is known, so that the environment at the edge of the chip can be well realized, the edge defect can be conveniently studied, meanwhile, the circuit at the edge of the chip can be utilized, and the area utilization rate of the chip is improved; in addition, the structure of the edge circuit unit is repeated, so that the layout and the wiring at the edge of the chip are convenient, the constraint can be carried out by using fewer design rules, and the circuit with the scannable and testable edge structure can be realized; the edge circuit unit has simple structure and strong applicability, and can be used for measuring the back-end process only by conforming to the standard digital unit architecture, thereby being applicable to each node of the mature process and the advanced process.
Fig. 5-7 are top views of semiconductor structures in accordance with another embodiment of the present invention.
Referring to fig. 5, a substrate 200 is provided, which includes a middle region I and an edge region II located around the middle region I.
The edge region II surrounds the intermediate region I, only a part of the edge region II lying in the first direction X being schematically shown.
With continued reference to fig. 5, a plurality of vertically stacked first metal layers (not shown) and second metal layers (not shown) are formed on the intermediate region I, wherein the first metal layers are parallel to a first direction X, the second metal layers are parallel to a second direction Y, the first direction X and the second direction Y are parallel to the surface of the substrate 200, and the first direction X and the second direction Y are perpendicular to each other.
In this embodiment, further comprising: a fifth power terminal 220 and a fifth ground terminal 221 parallel to the first direction X are formed on the intermediate region I.
With continued reference to fig. 5 and 6, fig. 6 is a schematic structural diagram of the single edge circuit unit in fig. 5, in which a plurality of connected edge circuit units are formed on the edge region II, the edge circuit units include one or more layers of metal structures, the metal structures are parallel to the first metal layer, and the metal structures are flush with the top surface of the first metal layer.
In this embodiment, the metal structure is formed simultaneously with the first metal layer.
The edge circuit units are located on edge areas II on two sides of the middle area I along the first direction X, and the edge circuit units are arranged on the edge areas II along the second direction Y.
In this embodiment, the edge circuit unit includes an open circuit unit. The open circuit unit is a unit of an open circuit.
In this embodiment, the metal structure includes: a second power terminal 201, a second ground terminal 202, and a plurality of fourth and fifth metal layers 203 and 204 alternately arranged.
In this embodiment, the open circuit unit further includes: a second plug (not shown) on the fourth metal layer 203 and on the second power terminal 201, a third plug (not shown) on the fifth metal layer 204 and on the second ground terminal 202, a second connection layer 205 on the second plug, a third connection layer 206 on the third plug, the fourth metal layer 203 being perpendicular to the second connection layer 205, the fifth metal layer 204 being perpendicular to the third connection layer 206.
The second connection layer 205 is electrically connected to the fourth metal layer 203 and the second power supply terminal 201, the third connection layer 206 is electrically connected to the fifth metal layer 204 and the second ground terminal 202, and a circuit between the second ground terminal 202 and the second power supply terminal 201 is an open circuit.
In this embodiment, the connection manner of the open circuit units is as follows: in parallel, the second power terminals 201 of the open circuit units are connected, and the second ground terminals 202 of the open circuit units are connected.
Referring to fig. 5 and 7, fig. 7 is a schematic structural diagram of a single second wiring unit in fig. 5, and in this embodiment, a plurality of open-circuit units are connected by the second wiring unit, where the second wiring unit includes: a fourth wiring layer 207 connected to the second power source terminal 201, a fifth wiring layer 208 connected to the second ground terminal 202, a sixth wiring layer 209 electrically connected to the fourth wiring layers 207, a seventh wiring layer 210 electrically connected to the fifth wiring layers 208, the fourth wiring layer 207 and the fifth wiring layer 208 being parallel to the first metal layer, and the sixth wiring layer 209 and the seventh wiring layer 210 being parallel to the second connection layer 205.
The sixth wiring layer 209 is electrically connected to the second power terminals 201 of the open circuit cells to be connected to an external power source for pressurization, and the seventh wiring layer 210 is electrically connected to the second ground terminals 202 of the open circuit cells to be connected to the external power source for pressurization for monitoring the effect of the parallel connection of the open circuit cells.
The second wiring unit is separated from the open circuit unit, and the environment of the chip edge structure can be better reproduced, so that the interference and influence of the test circuit can be avoided.
In this embodiment, the second connection layer 205 and the third connection layer 206 are formed simultaneously with the second metal layer.
In this embodiment, the second power terminal 201 is connected to the fifth power terminal 220 of the middle area through the fourth wiring layer 207 of the second wiring unit, and the second ground terminal 202 is connected to the fifth ground terminal 221 through the fifth wiring layer 208 of the second wiring unit and the middle area.
In this embodiment, further comprising: forming a plurality of filling units for filling the gaps of the edge region II, the filling units comprising: the third power supply end and the third grounding end are parallel to the first metal layer, the third power supply end is connected with the second power supply end 201, and the third grounding end is connected with the second grounding end 202.
Correspondingly, the embodiment of the invention also provides a semiconductor structure as shown in fig. 5 to 7.
Fig. 8 to 10 are schematic diagrams of an edge monitoring circuit according to an embodiment of the invention.
Referring to fig. 8 to 10, fig. 8 is a schematic diagram of an edge monitoring circuit, fig. 9 is a circuit schematic diagram of an edge circuit unit in fig. 8, and fig. 10 is a circuit schematic diagram of a first wiring unit in fig. 8, including: a plurality of connected edge circuit units.
In this embodiment, the edge circuit unit includes a short circuit unit sample; the mode of connecting a plurality of short circuit units sample is a series mode.
The short circuit unit sample includes: the circuit between the first input end IN and the first output end OUT is a short circuit, and the short circuit unit sample further comprises a first power supply end VDD1 and a first ground end VSS1; the first input terminal IN of the preceding shorting unit is connected to the first output terminal OUT of the following shorting unit.
The first input terminal IN of the previous shorting unit is connected with the first output terminal OUT of the next shorting unit through a first wiring unit including: the first end L1 and the second end L2 are connected, the first end L1 is connected with the first input end IN of the previous short-circuit unit, and the second end L2 is connected with the first output end OUT of the next short-circuit unit.
In this embodiment, pad1 and pad2 are used to power on several edge circuit cells connected in series.
The edge monitoring circuit is composed of a plurality of short-circuit units and a first wiring unit, and is simple in circuit structure and high in utilization rate.
Fig. 11 to 13 are schematic diagrams of an edge monitoring circuit according to another embodiment of the invention.
Referring to fig. 11 to 13, fig. 11 is a schematic diagram of an edge monitoring circuit, fig. 12 is a circuit schematic diagram of an edge circuit unit in fig. 11, and fig. 13 is a circuit schematic diagram of a second wiring unit in fig. 11, including: a plurality of connected edge circuit units.
In this embodiment, the edge circuit unit includes an open circuit unit sample; the mode of connecting a plurality of open circuit units is a parallel mode.
The open circuit unit sample includes: the circuit between the second grounding terminal VSS and the second power terminal VDD is an open circuit; the second power terminals VDD of the open circuit cells sample are connected, and the second ground terminals VSS of the open circuit cells sample are connected.
The open circuit unit samples are connected through a second wiring unit, and the second wiring unit comprises: the first connecting line L1 and the second connecting line L2, the first connecting line L1 is connected with a plurality of second power ends VDD, and the second connecting line L2 is connected with a plurality of second grounding ends VSS.
In this embodiment, pad1 and pad2 are used to power on several edge circuit cells that are in parallel.
The edge monitoring circuit is composed of a plurality of open-circuit units and a second wiring unit, and is simple in circuit structure and high in utilization rate.
Fig. 14 is a flowchart illustrating an operation method of the edge monitoring circuit according to an embodiment of the invention.
Referring to fig. 14, the operation method of the edge monitoring circuit includes:
step S10: providing an edge monitoring circuit, the edge monitoring circuit comprising: a plurality of connected edge circuit units;
step S20: after the edge monitoring circuit is electrified, judging whether the edge monitoring circuit is in a short circuit or open circuit state;
step S30: judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit, and overhauling the edge monitoring circuit if the edge monitoring circuit is abnormal.
In an embodiment, the edge circuit unit includes a short circuit unit; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is required. And if the edge monitoring circuit is normal, utilizing the edge monitoring circuit.
In another embodiment, the edge circuit cell comprises an open cell; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is needed. And if the edge monitoring circuit is normal, utilizing the edge monitoring circuit.
Through monitoring the structure at the edge of the chip, the defects in the process can be reduced, the yield is effectively improved, meanwhile, the utilization rate of the edge area of the chip is improved, the cost of a wafer factory is reduced, the redundant area of the chip is reduced, and the competitiveness of the product is improved.
Fig. 15 is a flow chart of a semiconductor layout design method in an embodiment of the invention.
Referring to fig. 15, the semiconductor layout design method includes:
step S100: providing a layout, wherein the layout comprises a middle area and an edge area positioned around the middle area;
step S200: providing an edge circuit unit;
step S300: and a plurality of connected edge circuit units are arranged in the edge area.
In an embodiment, the edge circuit unit includes a short circuit unit; the mode that a plurality of short-circuit units are connected is the series connection mode.
The plurality of short-circuit units are connected through the first wiring unit. The structure description of the short-circuit unit and the first wiring unit is shown in fig. 1 to 4, and will not be repeated here.
In another embodiment, the edge circuit cell comprises an open cell; the open circuit units are connected in parallel.
The open circuit units are connected through a second wiring unit. The structure description of the open circuit unit and the second wiring unit is shown in fig. 5 to 7, and will not be repeated here.
The layout edge area design consists of edge circuit units and wiring units, and the layout design is simple.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (34)

1. A semiconductor structure, comprising:
a substrate comprising a middle region and an edge region located around the middle region;
a plurality of layers of vertically stacked first and second metal layers located on the intermediate region, the first metal layer being parallel to a first direction, the second metal layer being parallel to a second direction, the first and second directions being parallel to a surface of the substrate, and the first and second directions being mutually perpendicular;
The edge circuit unit comprises a short circuit unit or an open circuit unit, the edge circuit unit comprises at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the top surface of the metal structure is flush with the top surface of the first metal layer.
2. The semiconductor structure of claim 1, wherein a plurality of said edge circuit cells are located on edge regions on both sides of said intermediate region along a first direction, and wherein a plurality of said edge circuit cells are arranged along a second direction on edge regions.
3. The semiconductor structure of claim 2, wherein the edge circuit cell comprises a shorting cell; the metal structure comprises: the first input end, the first output end, the first power end, the first grounding end and a plurality of third metal layers; the short circuit unit further includes: a first plug on the third metal layer, on the first input end or on the first output end, a first connection layer on the first plug, the first connection layer being perpendicular to the third metal layer; the first connecting layer is electrically connected with the first input end, the first output end and the third metal layers, and a circuit between the first input end and the first output end is a short circuit.
4. The semiconductor structure of claim 3, wherein the plurality of shorting cells are connected in a manner such that: in the series connection mode, the first input end of the former short circuit unit is connected with the first output end of the latter short circuit unit.
5. The semiconductor structure of claim 4, wherein the first input terminal of the previous shorting unit is connected to the first output terminal of the next shorting unit through a first wiring unit comprising: the first wiring layer is connected with the first input end, the second wiring layer is connected with the first output end, the third wiring layer is electrically connected with the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are parallel to the first metal layer, and the third wiring layer is parallel to the first connecting layer.
6. The semiconductor structure of claim 5, wherein the first wiring unit further comprises: the fourth power end is connected with the first power end, and the fourth grounding end is connected with the first grounding end, and the fourth power end and the fourth grounding end are parallel to the first metal layer.
7. The semiconductor structure of claim 3, further comprising: a fifth power terminal and a fifth ground terminal on the middle region, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the first power end is connected with a fifth power end of the middle area through a first wiring unit, and the first grounding end is connected with a fifth grounding end of the middle area through the first wiring unit.
8. The semiconductor structure of claim 2, wherein the edge circuit cell comprises an open cell; the metal structure comprises: the second power end, the second grounding end and a plurality of fourth metal layers and fifth metal layers which are alternately arranged; the open circuit unit further includes: the second plug is positioned on the fourth metal layer and the second power end, the third plug is positioned on the fifth metal layer and the second grounding end, the second connecting layer is positioned on the second plug, the third connecting layer is positioned on the third plug, the fourth metal layer is vertical to the second connecting layer, and the fifth metal layer is vertical to the third connecting layer; the second connecting layer is electrically connected with the fourth metal layer and the second power supply end, the third connecting layer is electrically connected with the fifth metal layer and the second grounding end, and a circuit between the second grounding end and the second power supply end is an open circuit.
9. The semiconductor structure of claim 8, wherein the plurality of open cells are connected in a manner such that: in a parallel mode, the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.
10. The semiconductor structure of claim 9, wherein a plurality of open cells are connected by a second wiring cell, the second wiring cell comprising: the fourth wiring layer is connected with the second power end, the fifth wiring layer is connected with the second grounding end, the sixth wiring layer is electrically connected with the fourth wiring layers, the seventh wiring layer is electrically connected with the fifth wiring layers, the fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and the seventh wiring layer are parallel to the second connecting layer.
11. The semiconductor structure of claim 8, further comprising: a fifth power terminal and a fifth ground terminal on the middle region, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the second power end is connected with a fifth power end of the middle area through a second wiring unit, and the second grounding end is connected with a fifth grounding end of the middle area through the second wiring unit.
12. The semiconductor structure of claim 1, further comprising: a plurality of filling units for filling voids of an edge region, the filling units comprising: the third power end and the third grounding end are parallel to the first metal layer, the third power end is connected with the first power end, and the third grounding end is connected with the first grounding end.
13. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a middle region and an edge region positioned around the middle region;
forming a plurality of vertically stacked first metal layers and second metal layers on the intermediate region, wherein the first metal layers are parallel to a first direction, the second metal layers are parallel to a second direction, the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction are mutually perpendicular;
And forming a plurality of connected edge circuit units on the edge area, wherein the edge circuit units comprise short circuit units or open circuit units, the edge circuit units comprise at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the metal structure is flush with the top surface of the first metal layer.
14. The method of forming a semiconductor structure of claim 13, wherein the metal structure is formed simultaneously with the first metal layer; the edge circuit units are positioned on the edge areas on two sides of the middle area along the first direction, and the edge circuit units are arranged on the edge areas along the second direction.
15. The method of forming a semiconductor structure of claim 14, wherein the edge circuit cell comprises a shorting cell; the metal structure comprises: the first input end, the first output end, the first power end, the first grounding end and a plurality of third metal layers; the short circuit unit further includes: a first plug on the third metal layer, on the first input end or on the first output end, a first connection layer on the first plug, the first connection layer being perpendicular to the third metal layer; the first connecting layer is electrically connected with the first input end, the first output end and the third metal layers, and a circuit between the first input end and the first output end is a short circuit.
16. The method of forming a semiconductor structure as claimed in claim 15, wherein the plurality of shorting cells are connected in a manner such that: in the series connection mode, the first input end of the former short circuit unit is connected with the first output end of the latter short circuit unit.
17. The method of forming a semiconductor structure of claim 16, wherein the first input terminal of the preceding shorting cell is connected to the first output terminal of the following shorting cell through a first wiring cell comprising: the first wiring layer is connected with the first input end, the second wiring layer is connected with the first output end, the third wiring layer is electrically connected with the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are parallel to the first metal layer, and the third wiring layer is parallel to the first connecting layer.
18. The method of forming a semiconductor structure of claim 15, wherein the first connection layer is formed simultaneously with the second metal layer.
19. The method of forming a semiconductor structure of claim 15, wherein the edge circuit cell comprises an open cell; the metal structure comprises: the second power end, the second grounding end and a plurality of fourth metal layers and fifth metal layers which are alternately arranged; the open circuit unit further includes: the second plug is positioned on the fourth metal layer and the second power end, the third plug is positioned on the fifth metal layer and the second grounding end, the second connecting layer is positioned on the second plug, the third connecting layer is positioned on the third plug, the fourth metal layer is vertical to the second connecting layer, and the fifth metal layer is vertical to the third connecting layer; the second connecting layer is electrically connected with the fourth metal layer and the second power supply end, the third connecting layer is electrically connected with the fifth metal layer and the second grounding end, and a circuit between the second grounding end and the second power supply end is an open circuit.
20. The method of forming a semiconductor structure as claimed in claim 19, wherein the plurality of open cells are connected in a manner such that: in a parallel mode, the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.
21. The method of forming a semiconductor structure of claim 20, wherein a plurality of open cells are connected by a second wiring cell, the second wiring cell comprising: the fourth wiring layer is connected with the second power end, the fifth wiring layer is connected with the second grounding end, the sixth wiring layer is electrically connected with the fourth wiring layers, the seventh wiring layer is electrically connected with the fifth wiring layers, the fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and the seventh wiring layer are parallel to the second connecting layer.
22. The method of forming a semiconductor structure of claim 19, wherein the second connection layer and the third connection layer are formed simultaneously with the second metal layer.
23. The method of forming a semiconductor structure of claim 13, further comprising: forming a plurality of filling units for filling voids in the edge region, the filling units comprising: the third power supply end and the third grounding end are parallel to the first metal layer.
24. An edge monitoring circuit, comprising:
a plurality of connected edge circuit units.
25. The edge monitoring circuit of claim 24 wherein the edge circuit unit comprises a shorting unit; the mode that a plurality of short-circuit units are connected is the series connection mode.
26. The edge monitoring circuit of claim 25 wherein the shorting unit comprises a first input terminal and a first output terminal, the circuit between the first input terminal and the first output terminal being a shorting circuit; the first input end of the former short-circuit unit is connected with the first output end of the latter short-circuit unit.
27. The edge monitoring circuit of claim 25 wherein the edge circuit cells comprise open circuit cells; the open circuit units are connected in parallel.
28. The edge monitoring circuit of claim 27, wherein the open circuit unit comprises: the circuit between the second grounding end and the second power end is an open circuit; the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.
29. A method of operating an edge monitoring circuit, comprising:
Providing an edge monitoring circuit, the edge monitoring circuit comprising: a plurality of connected edge circuit units;
after the edge monitoring circuit is electrified, judging whether the edge monitoring circuit is in a short circuit or open circuit state;
judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit, and overhauling the edge monitoring circuit if the edge monitoring circuit is abnormal.
30. The method of operation of an edge monitoring circuit of claim 29, wherein the edge circuit unit comprises a shorting unit; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is required.
31. The method of operation of an edge monitoring circuit of claim 29, wherein the edge circuit cells comprise open cells; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is needed.
32. A semiconductor layout design method, comprising:
the layout comprises a middle area and edge areas positioned around the middle area;
providing an edge circuit unit;
and a plurality of connected edge circuit units are arranged in the edge area.
33. A semiconductor layout design method according to claim 32, wherein the edge circuit cells comprise short circuit cells; the mode that a plurality of short-circuit units are connected is the series connection mode.
34. A semiconductor layout design method according to claim 32, wherein the edge circuit cells comprise open circuit cells; the open circuit units are connected in parallel.
CN202211042640.XA 2022-08-29 2022-08-29 Semiconductor structure, forming method, layout design method, circuit and working method Pending CN117672888A (en)

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