CN115988863A

CN115988863A - Semiconductor power module, circuit layout method, device and storage medium thereof

Info

Publication number: CN115988863A
Application number: CN202211307751.9A
Authority: CN
Inventors: 王涛
Original assignee: Suzhou Xizhi Technology Co ltd
Current assignee: Suzhou Xizhi Technology Co ltd
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2023-04-18

Abstract

The invention relates to the technical field of electricity, in particular to a semiconductor power module, a circuit layout method, equipment and a storage medium thereof, wherein the semiconductor power module comprises the following components: the circuit comprises an element substrate, and a pin VBUS, a first switch Q1, a second switch Q2, a pin PGND, a pin PHASE and a capacitor C1 which are arranged on the element substrate; the pin VBUS, the first switch Q1, the second switch Q2 and the pin PGND form a first loop; the first switch Q1, the second switch Q2 and the capacitor C1 form a second loop; the first loop is positioned outside the second loop; under the condition that the first switch Q1 and the second switch Q2 are full-control switch tubes, the element substrate is also provided with a pin HG, a pin HS, a pin LG and a pin LS; the first switch tube Q1 is connected with a pin HG and a pin HS; the second switching tube Q2 is connected with pins LG and LS; a third loop is formed between the pin HG and the pin HS; a fourth loop is formed between the pin LG and the pin LS. The problem of poor electromagnetic compatibility of the semiconductor power module can be solved, and the electromagnetic compatibility of the semiconductor power module is improved.

Description

Semiconductor power module, circuit layout method, device and storage medium thereof

Technical Field

The present invention relates to the field of electrical technologies, and in particular, to a semiconductor power module, a method and an apparatus for circuit layout thereof, and a storage medium.

Background

High power density and high reliability are two important indexes for evaluating semiconductor power modules. The high frequency is one of the main means for realizing high power density, and the improvement of the electromagnetic compatibility is an important index of reliability. However, increasing the frequency means high dv/dt and di/dt, which increase the electromagnetic interference, resulting in poor electromagnetic compatibility, and thus, an excellent layout is required to improve the electromagnetic compatibility of the semiconductor power module.

Disclosure of Invention

The application provides a semiconductor power module, a circuit layout method, equipment and a storage medium thereof, which can solve the problem of poor electromagnetic compatibility of the semiconductor power module. The application provides the following technical scheme:

in a first aspect, the present application provides a semiconductor power module comprising: the circuit comprises an element substrate, and a pin VBUS, a first switch Q1, a second switch Q2, a pin PGND, a pin PHASE and a capacitor C1 which are arranged on the element substrate; the pin VBUS, the first switch Q1, the second switch Q2, and the pin PGND form a first loop;

the first switch Q1, the second switch Q2 and the capacitor C1 form a second loop; the first circuit is positioned outside the second circuit;

under the condition that the first switch Q1 and the second switch Q2 are fully-controlled switch tubes, the element substrate is further provided with a pin HG, a pin HS, a pin LG and a pin LS;

the first switch tube Q1 is connected with a pin HG and a pin HS; the second switching tube Q2 is connected with pins LG and LS;

a third loop is formed between the pin HG and the pin HS;

a fourth loop is formed between the pin LG and the pin LS.

Optionally, in a case that the first switch Q1 is a fully-controlled switch tube, and the second switch Q2 is a diode, the element substrate is provided with the pin HG and the pin HS; the first switch tube Q1 is connected with the pin HG and the pin HS;

the third loop is formed between the pin HG and the pin HS.

Optionally, in a case that the first switch Q1 is a diode and the second switch Q2 is a fully controlled switch, the component substrate is provided with the pin LG and the pin LS; the second switch Q2 is connected to the pin LG and the pin LS;

the fourth loop is formed between the pin LG and the pin LS.

Optionally, the pin HG, the pin HS, the pin LG and the pin LS are located on the same side of the component substrate;

the pin VBUS and the pin PGND are located on the same side of the component substrate, and are opposite to a side where the pin HG, the pin HS, the pin LG, and the pin LS are located.

Optionally, the capacitor C1 is located at one side of a central connecting line between the first switch Q1 and the second switch Q2, and the pin VBUS and the pin & VGND are located at the other side of the central connecting line between the first switch Q1 and the second switch Q2.

Optionally, the third loop and the fourth loop are located on one side of a central connecting line between the first switch Q1 and the second switch Q2, and the first loop is located on the other side of the central connecting line between the first switch Q1 and the second switch Q2.

Optionally, the capacitor C1 is located in the middle of the third loop and the fourth loop.

Optionally, the third loop and the fourth loop are located on one side of a central connection line between the first switch Q1 and the second switch Q2, and the first loop is located on the other side of the central connection line between the first switch Q1 and the second switch Q2.

Optionally, the fully-controlled switch tube comprises an insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor.

Optionally, the semiconductor power module further comprises a lead frame; the lead frame is connected to the first switch Q1 and the second switch Q2.

Optionally, the leadframe locations include the pins PHASE or pins on a housing package module (housing type power module).

In a second aspect, a circuit layout method of a semiconductor power module is provided, which includes:

mounting a first switch Q1, a second switch Q2 and a capacitor C1 on an element substrate;

under the condition that the first switch Q1 is a fully-controlled switch tube, connecting the first switch Q1 with a pin HS and a pin HG; the pin HS and the pin HG are positioned on the same side of the element substrate;

under the condition that the second switch Q2 is a fully-controlled switch tube, connecting the second switch Q2 with a pin LG and a pin LS; the pin HS, the pin HG, the pin LG, and the pin LS are located on the same side of the component substrate;

connecting the first switch Q1 with a pin VBUS;

connecting the second switch Q2 with a pin PGND; the pin VBUS and the pin PGND are located on the same side of the component substrate, and are opposite to the side where the pin HS, the pin HG, the pin LG, and the pin LS are located.

In a third aspect, an electronic device is provided, including: a memory and at least one processor, the memory having instructions stored therein; the at least one processor invokes the instructions in the memory to cause the electronic device to perform the steps of the method of layout of circuits of a semiconductor power module according to the second aspect.

In a fourth aspect, a computer-readable storage medium is provided, having instructions stored thereon, which when executed by a processor, implement the steps of the method of layout of circuits of a semiconductor power module according to the second aspect.

The beneficial effect of this application lies in: the device comprises an element substrate, a pin VBUS, a first switch Q1, a second switch Q2, a pin PGND, a pin PHASE and a capacitor C1, wherein the pin VBUS, the first switch Q1, the second switch Q2, the pin PGND, the pin PHASE and the capacitor C1 are arranged on the element substrate; the pin VBUS, the first switch Q1, the second switch Q2 and the pin PGND form a first loop; the first switch Q1, the second switch Q2 and the capacitor C1 form a second loop; the first loop is positioned outside the second loop; under the condition that the first switch Q1 and the second switch Q2 are full-control switch tubes, the element substrate is also provided with a pin HG, a pin HS, a pin LG and a pin LS; the first switch tube Q1 is connected with a pin HG and a pin HS; the second switching tube Q2 is connected with pins LG and LS; a third loop is formed between the pin HG and the pin HS; a fourth loop is formed between the pin LG and the pin LS. The problem that the electromagnetic compatibility of the semiconductor power module is poor can be solved. The pin HS, the pin HG, the pin LG and the pin LS are located on the same side of the component substrate 110, and the pin VBUS and the pin PGND are located on the other side of the component substrate, opposite to the side where the pin HS, the pin HG, the pin LG and the pin LS are located. Therefore, on one hand, the third loop and the fourth loop can be far away from the first power loop and the second power loop and are not easily subjected to electromagnetic interference of the first loop and the second loop, and on the other hand, magnetic fields formed by the first loop and the second loop when the first switch Q1 and/or the second switch Q2 perform switching actions weaken each other at the positions of the third loop and the fourth loop, so that the electromagnetic compatibility characteristic of the semiconductor power module is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a circuit topology diagram of a semiconductor power module provided by an embodiment of the present application;

fig. 2 is a circuit layout diagram of a semiconductor power module provided by an embodiment of the present application;

fig. 3 is a circuit topology diagram of another semiconductor power module provided by an embodiment of the present application;

fig. 4 is a circuit layout diagram of another semiconductor power module provided by an embodiment of the present application;

fig. 5 is a circuit topology diagram of yet another semiconductor power module provided by an embodiment of the present application;

fig. 6 is a circuit layout diagram of yet another semiconductor power module provided by an embodiment of the present application;

fig. 7 is a circuit layout diagram of a conventional semiconductor power module provided by an embodiment of the present application;

fig. 8 is a flowchart of a method for layout of a circuit of a semiconductor power module according to another embodiment of the present application;

fig. 9 is a block diagram of a circuit layout apparatus of a semiconductor power module according to another embodiment of the present application;

fig. 10 is a block diagram of an electronic device provided in accordance with yet another embodiment of the present application.

Detailed Description

The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In the application, where the contrary is not intended, directional terms such as "upper, lower, top, bottom" or the like are generally used with respect to the orientation shown in the drawings, or with respect to the component itself in the vertical, or gravitational direction; similarly, "inner and outer" refer to inner and outer relative to the profile of the components themselves for ease of understanding and description, but the above directional terms are not intended to limit the present application.

First, several terms referred to in the present application will be described.

Electromagnetic Compatibility (EMC): refers to the ability of a device or system to operate satisfactorily in its electromagnetic environment and not to generate intolerable electromagnetic disturbance to any device in its environment. Therefore, EMC includes two requirements: on one hand, the Electromagnetic Disturbance (Electromagnetic Disturbance) generated by the equipment to the environment in the normal operation process cannot exceed a certain limit value; another aspect refers to a device having a certain degree of immunity to Electromagnetic disturbances, i.e., electromagnetic Susceptibility (EMS), that exist in the environment in which it is located.

Electromagnetic Interference (EMI): the work of the electronic product can cause interference to other peripheral electronic products, and the EMC specification is associated with the interference. Is a problem often encountered by electronic and electric products. The interference types include conducted interference and radiated interference.

Insulated Gate Bipolar Transistor (IGBT): the composite fully-controlled voltage-driven power Semiconductor device consists of a (BJT) Bipolar Transistor and an insulated gate Field Effect Transistor (MOS), and has the advantages of both high input impedance of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and low on-state voltage drop of a power Transistor (Giant Transistor, GTR). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current-carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like. The IGBT is a core device for energy conversion and transmission, commonly known as the "CPU" of a power electronic device, and is used as a strategic emerging industry in the country, and has a wide application in the fields of rail transit, smart grid, aerospace, electric vehicles, new energy equipment, and the like.

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET): typically a metal-oxide-semiconductor (semiconductor) field effect transistor, or so-called metal-insulator-semiconductor (insulator). G: a gate electrode; s: a source electrode; d: drain electrode. The source and drain of the MOS transistor can be reversed, and they are both N-type regions formed in the P-type back gate. In most cases, the two regions are identical, and even if the two regions are reversed, the performance of the device is not affected. Such devices are considered symmetrical.

Inductance: inductance is a property of a closed loop and is a physical quantity. When current passes through the coil, magnetic field induction is formed in the coil, and the induced magnetic field can generate induction current to resist the current passing through the coil. It is a parameter of the circuit that describes the induced electromotive force effect induced in the present coil or in another coil due to the change in the coil current. Inductance is a generic term for self-inductance and mutual inductance.

The semiconductor power module provided by the present application is described in detail below.

As shown in fig. 1 and fig. 2, an embodiment of the present application provides a semiconductor power module, whose topology circuit is a half-bridge circuit as shown in fig. 1, and includes at least: the device includes an element substrate 110, and a pin VBUS, a first switch Q1, a second switch Q2, a pin PGND, a pin PHASE, and a capacitor C1 disposed on the element substrate 110. The terminal VBUS represents a DC + potential of the half-bridge circuit, the terminal PGND represents a DC-potential of the half-bridge circuit, and the terminal PHASE represents an AC potential.

As shown in fig. 1, a first switch Q1 and a second switch Q2 form a half-bridge circuit after passing through a bonding wire, a DBC wiring and a lead frame; one end of the capacitor C1 is between the first switch Q1 and the pin VBUS, and the other end is between the second switch Q2 and the pin PGND.

In this embodiment, the element Substrate 110 may be a Copper-clad ceramic Substrate (DBC), a Printed Circuit Board (PCB), a Direct Copper Plating (DPC) Substrate, an Insulated Metal Substrate (IMS ), or the like.

The pin VBUS, the first switch Q1, the second switch Q2, the pin PGND, the pin PHASE, and the capacitor C1 are disposed on the element substrate 110.

Specifically, as shown in fig. 2, the first switch Q1 is disposed on one side of the element substrate 110, the second switch Q2 is disposed on the opposite side of the first switch Q1, and at this time, a center connection line may be considered to exist between the first switch Q1 and the second switch Q2, the capacitor C1 is disposed on one side of the center connection line between the first switch Q1 and the second switch Q2, and the pin VBUS and the pin VGND are disposed on the other side of the center connection line between the first switch Q1 and the second switch Q2.

In this embodiment, when the device switch works, the pin VBUS, the first switch Q1, the second switch Q2, and the pin PGND form the first loop 1110.

Specifically, the first loop 1110 is formed by connecting the pin VBUS, the first switch Q1, the second switch Q2, and the pin PGND by bonding wires.

In actual implementation, each element on the element substrate 110 may be connected by using a metal block, a metal tape, a flexible circuit, or the like.

In addition, the first switch Q1, the second switch Q2, and the capacitor C1 constitute a second circuit 1120. The capacitor C1 is a high-frequency capacitor, and the first loop 1110 is located outside the second loop 1120.

In this embodiment, the first switch Q1 may be a fully controlled switch, and at this time, the second switch Q2 may be a fully controlled switch or a diode; or, the second switch Q2 is a fully controlled switch, and the first switch Q1 is a fully controlled switch tube or a diode, which specifically includes one of the following situations:

first, the first switch Q1 and the second switch Q2 are all fully-controlled switch tubes.

In the case where the first switch Q1 and the second switch Q2 are fully-controlled switching tubes, as shown in fig. 1 and 2, the component substrate 110 is further provided with a pin HG, a pin HS, a pin LG, and a pin LS.

The pin HG, the pin HS, the pin LG, and the pin LS are located on the same side of the component substrate 110; the pin VBUS and the pin PGND are located on the same side of the component substrate 110, and are opposite to the side where the pin HG, the pin HS, the pin LG, and the pin LS are located.

At the moment, the first switch tube Q1 is connected with a pin HG and a pin HS; the second switching tube Q2 is connected to the pins LG and LS.

Referring to fig. 1 and 2, a third loop 1130 is formed between pin HG and pin HS; a fourth loop 1140 is formed between the pin LG and the pin LS.

Secondly, the first switch Q1 is a full-control switch tube, and the second switch Q2 is a diode.

As shown in fig. 3 and 4, in the case where the first switch Q1 is a fully controlled switch and the second switch Q2 is a diode, the element substrate 110 is provided with a pin HG and a pin HS. At this time, the first switch tube Q1 is connected to the pin HG and the pin HS.

Accordingly, a third loop 1130 is formed between pin HG and pin HS. The third loop 1130 is a gate drive loop for the first switch Q1.

And thirdly, the first switch Q1 is a diode, and the second switch Q2 is a full-control switch tube.

As shown in fig. 5 and 6, in the case where the first switch Q1 is a diode and the second switch Q2 is a fully-controlled switch, the component substrate 110 is provided with a pin LG and a pin LS; at this time, the second switch Q2 is connected to the pin LG and the pin LS.

Accordingly, a fourth loop 1140 is formed between the pin LG and the pin LS. The fourth loop 1140 is a gate drive loop for the second switch Q2.

When the first switch Q1 is a fully controlled switch, the second switch Q2 is a diode, or the first switch Q1 is a diode and the second switch Q2 is a fully controlled switch, the third loop 1130 or the fourth loop 1140 is located on one side of a central connection line of the first switch Q1 and the second switch Q2, and accordingly, the first loop 1110 is located on the other side of the central connection line of the first switch Q1 and the second switch Q2.

Specifically, referring to fig. 5, in the case that the first switch Q1 is a fully-controlled switch and the second switch Q2 is a diode, the third circuit 1130 is located on one side of a central connecting line of the first switch Q1 and the second switch Q2, and accordingly, the first circuit 1110 is located on the other side of the central connecting line of the first switch Q1 and the second switch Q2.

In the case that the first switch Q1 is a diode and the second switch Q2 is a fully controlled switch, the fourth loop 1140 is located at one side of the central connection line of the first switch Q1 and the second switch Q2, and correspondingly, the first loop 1110 is located at the other side of the central connection line of the first switch Q1 and the second switch Q2.

Referring to fig. 1, in fig. 1, L1 and L4 are parasitic inductances due to leads of the semiconductor power module and an external carrier of the semiconductor power module, and L2 and L3 are intrinsic parasitic inductances due to internal bonding wires of the semiconductor power module and wiring on the element substrate 110. The capacitor C1 can shield the parasitic inductor L1 and the parasitic inductor L4 from interfering with the first switch Q1 and the second switch Q2.

However, in the conventional circuit layout, as shown in fig. 7, electromagnetic interference generated by the loop 710 formed by the pin VBUS, the first switch Q1, the second switch Q2, and the pin PGND, and the loop 720 formed by the first switch Q1, the second switch Q2, and the capacitor C1 may interfere with the loop 730 formed between the pin HG and the pin HS, and the loop 740 formed between the pin LG and the pin LS.

Meanwhile, when the first switch Q1 and the second switch Q2 are switched, the induced magnetic field formed by the loops 710 and 720 may strengthen the

loops

730 and 740, so that the electromagnetic compatibility characteristic of the semiconductor power module may be degraded.

Based on this, in the embodiment, referring to fig. 2, the pin HS, the pin HG, the pin LG and the pin LS are located on the same side of the component substrate 110, and the pin VBUS and the pin PGND are located on the other side of the component substrate, opposite to the side where the pin HS, the pin HG, the pin LG and the pin LS are located. Thus, on one hand, the third loop 1130 and the fourth loop 1140 can be far away from the first power loop 1110 and the second power loop 1120, and are not easily subjected to electromagnetic interference of the first power loop 1110 and the second power loop 1120, and on the other hand, magnetic fields formed by the first power loop 1110 and the second power loop 1120 when the first switch Q1 and/or the second switch Q2 perform switching actions weaken each other at the positions of the third loop 1130 and the fourth loop 1140, so that the electromagnetic compatibility characteristic of the semiconductor power module is improved.

Specifically, the third and

fourth loops

1130 and 1140 are located at one side of a central connection line of the first and second switches Q1 and Q2, and the first loop 1110 is located at the other side of the central connection line of the first and second switches Q1 and Q2.

Optionally, the capacitor C1 is located in the middle of the third loop 1130 and the fourth loop 1140.

In addition, in the present embodiment, the element substrate 110 further includes a lead frame; the lead frame is connected to the first switch Q1 and the second switch Q2.

Optionally, the lead frame site includes a pin PHASE or a pin on the case pack module.

To sum up, the power device provided in this embodiment includes: the device comprises an element substrate, and a pin VBUS, a first switch Q1, a second switch Q2, a pin PGND, a pin PHASE and a capacitor C1 which are arranged on the element substrate; the pin VBUS, the first switch Q1, the second switch Q2 and the pin PGND form a first loop; the first switch Q1, the second switch Q2 and the capacitor C1 form a second loop; the first loop is positioned outside the second loop; under the condition that the first switch Q1 and the second switch Q2 are full-control switch tubes, the element substrate is also provided with a pin HG, a pin HS, a pin LG and a pin LS; the first switch tube Q1 is connected with a pin HG and a pin HS; the second switch tube Q2 is connected with the pins LG and LS; a third loop is formed between the pin HG and the pin HS; a fourth loop is formed between the pin LG and the pin LS. The problem that the electromagnetic compatibility of the semiconductor power module is poor can be solved. The pin HS, the pin HG, the pin LG and the pin LS are located on the same side of the component substrate 110, and the pin VBUS and the pin PGND are located on the other side of the component substrate, opposite to the side where the pin HS, the pin HG, the pin LG and the pin LS are located. Therefore, on one hand, the third loop and the fourth loop can be far away from the first power loop and the second power loop and are not easily subjected to electromagnetic interference of the first loop and the second loop, and on the other hand, magnetic fields formed by the first loop and the second loop when the first switch Q1 and/or the second switch Q2 perform switching actions weaken each other at the positions of the third loop and the fourth loop, so that the electromagnetic compatibility characteristic of the semiconductor power module is improved.

Fig. 8 is a flowchart of a method for layout of a semiconductor power module according to an embodiment of the present application, the method including at least the following steps:

in step 801, the first switch Q1, the second switch Q2, and the capacitor C1 are mounted on the device substrate.

Step 802, connecting the first switch Q1 with a pin HS and a pin HG under the condition that the first switch Q1 is a full-control switch tube; pin HS and pin HG are located on the same side of the component substrate.

And step 803, connecting the second switch Q2 with the pin LG and the pin LS under the condition that the second switch Q2 is a fully-controlled switch tube.

Wherein, pin HS, pin HG, pin LG, and pin LS are located on the same side of the component substrate.

In step 804, the first switch Q1 is connected to the pin VBUS.

In step 805, the second switch Q2 is connected to the pin PGND.

In this embodiment, the pin VBUS and the pin PGND are located on the same side of the device substrate, and are opposite to the side where the pin HS, the pin HG, the pin LG, and the pin LS are located.

In summary, in the control method of the self-moving device provided in this embodiment, the first switch Q1, the second switch Q2 and the capacitor C1 are mounted on the device substrate; under the condition that the first switch Q1 is a full-control switch tube, connecting the first switch Q1 with a pin HS and a pin HG; the pin HS and the pin HG are positioned on the same side of the element substrate; under the condition that the second switch Q2 is a full-control switch tube, connecting the second switch Q2 with a pin LG and a pin LS; the pin HS, the pin HG, the pin LG and the pin LS are positioned on the same side of the component substrate; connecting a first switch Q1 with a pin VBUS; the second switch Q2 is connected to the pin PGND. The problem that the electromagnetic compatibility of the semiconductor power module is poor can be solved. The pin HS, the pin HG, the pin LG and the pin LS are located on the same side of the component substrate 110, and the pin VBUS and the pin PGND are located on the other side of the component substrate, opposite to the side where the pin HS, the pin HG, the pin LG and the pin LS are located. Therefore, on one hand, the third loop and the fourth loop can be far away from the first power loop and the second power loop and are not easily subjected to electromagnetic interference of the first loop and the second loop, and on the other hand, magnetic fields formed by the first loop and the second loop when the first switch Q1 and/or the second switch Q2 perform switching actions weaken each other at the positions of the third loop and the fourth loop, so that the electromagnetic compatibility characteristic of the semiconductor power module is improved.

Fig. 9 is a block diagram of a circuit layout device of a semiconductor power module according to another embodiment of the present application. The device at least comprises the following modules: a component mounting module 910, a first connection module 920, a second connection module 930, a third connection module 940, and a fourth connection module 950;

an element mounting module 910 for mounting the first switch Q1, the second switch Q2 and the capacitor C1 on an element substrate;

the first connection module 920 is configured to connect the first switch Q1 with the pin HS and the pin HG when the first switch Q1 is a fully controlled switch tube;

a second connection module 930, configured to connect the second switch Q2 to the pin LG and the pin LS when the second switch Q2 is a fully-controlled switch tube;

a third connection module 940, configured to connect the first switch Q1 to the pin VBUS;

a fourth connecting module 950, configured to connect the second switch Q2 to the pin PGND.

For relevant details reference is made to the above-described embodiments.

It should be noted that: in the circuit layout device of the semiconductor power module provided in the above embodiment, only the division of the above functional modules is illustrated when the circuit layout of the semiconductor power module is performed, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the circuit layout device of the semiconductor power module is divided into different functional modules, so as to perform all or part of the above described functions. In addition, the circuit layout device of the semiconductor power module and the circuit layout method of the semiconductor power module provided by the above embodiments belong to the same concept, and specific implementation processes thereof are detailed in the method embodiments and are not described herein again.

FIG. 10 is a block diagram of an electronic device provided by an embodiment of the application. The device, which may be an electronic device as described in the above method, comprises at least a processor 1001 and a memory 1002.

Processor 1001 may include one or more processing cores such as: 4 core processors, 8 core processors, etc. The processor 1001 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 10001 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 1001 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 1001 may further include an AI (Artificial Intelligence) processor for processing a computing operation related to machine learning.

Memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in the memory 1002 is used to store at least one instruction for execution by the processor 1001 to implement the method of layout of a semiconductor power module provided by the method embodiments herein.

In some embodiments, the external reference calibration apparatus may further include: a peripheral interface and at least one peripheral. The processor 1001, memory 1002 and peripheral interface may be connected by bus or signal lines. Each peripheral may be connected to the peripheral interface via a bus, signal line, or circuit board. Illustratively, peripheral devices include, but are not limited to: radio frequency circuit, touch display screen, audio circuit, power supply, etc.

Of course, the external reference calibration apparatus may also include fewer or more components, which is not limited in this embodiment.

Optionally, the present application further provides a computer-readable storage medium, in which a program is stored, and the program is loaded and executed by a processor to implement the circuit layout method of the semiconductor power module of the above method embodiment.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A semiconductor power module, characterized in that the semiconductor power module comprises: the circuit comprises an element substrate, and a pin VBUS, a first switch Q1, a second switch Q2, a pin PGND, a pin PHASE and a capacitor C1 which are arranged on the element substrate; the pin VBUS, the first switch Q1, the second switch Q2, and the pin PGND form a first loop;

the first switch tube Q1 is connected with a pin HG and a pin HS; the second switch tube Q2 is connected with pins LG and LS;

a third loop is formed between the pin HG and the pin HS;

a fourth loop is formed between the pin LG and the pin LS.

2. The semiconductor power module according to claim 1, wherein in a case where the first switch Q1 is a fully controlled switch and the second switch Q2 is a diode, the element substrate is provided with the pin HG and the pin HS; the first switch tube Q1 is connected with the pin HG and the pin HS;

the third loop is formed between the pin HG and the pin HS.

3. The semiconductor power module according to claim 1, wherein in a case where the first switch Q1 is a diode and the second switch Q2 is a fully controlled switch tube, the component substrate is provided with the pin LG and the pin LS; the second switch Q2 is connected to the pin LG and the pin LS;

the fourth loop is formed between the pin LG and the pin LS.

4. The semiconductor power module according to any one of claims 1 to 3, wherein the pin HG, the pin HS, the pin LG and the pin LS are located on the same side of the component substrate;

5. The semiconductor power module of claim 1, wherein the capacitor C1 is located at one side of a central connecting line of the first switch Q1 and the second switch Q2, and the pin VBUS and the pin VGND are located at the other side of the central connecting line of the first switch Q1 and the second switch Q2.

6. The semiconductor power module of claim 1, wherein the third loop and the fourth loop are located on one side of a central connecting line of the first switch Q1 and the second switch Q2, and the first loop is located on the other side of the central connecting line of the first switch Q1 and the second switch Q2.

7. The semiconductor power module of claim 1, wherein the capacitance C1 is located in the middle of the third loop and the fourth loop.

8. The semiconductor power module according to any one of claims 2 to 3, wherein the third loop or the fourth loop is located on one side of a central connecting line between the first switch Q1 and the second switch Q2, and the first loop is located on the other side of the central connecting line between the first switch Q1 and the second switch Q2.

9. The semiconductor power module of any of claims 1 to 3, wherein the fully controlled switch comprises an insulated gate bipolar transistor or a MOSFET.

10. The semiconductor power module according to claim 1, wherein the element substrate further comprises a lead frame; the lead frame is connected to the first switch Q1 and the second switch Q2.

11. The semiconductor power module of claim 10, wherein the lead frame site comprises the pin PHASE or a pin on a case pack module.

12. A method of circuit layout for a semiconductor power module, the method comprising:

connecting the first switch Q1 with a pin VBUS;

connecting the second switch Q2 with a pin PGND; the pin VBUS and the pin PGND are located on the same side of the component substrate, and are opposite to a side where the pin HS, the pin HG, the pin LG, and the pin LS are located.

13. An electronic device, characterized in that the electronic device comprises: a memory and at least one processor, the memory having instructions stored therein; the at least one processor invoking the instructions in the memory to cause the electronic device to perform the steps of the method of layout of circuits of a semiconductor power module of claim 8.

14. A computer readable storage medium having instructions stored thereon, wherein the instructions, when executed by a processor, implement the steps of the method of layout of circuits of a semiconductor power module of claim 8.