CN115987263B

CN115987263B - Radio frequency switch circuit and radio frequency front end module

Info

Publication number: CN115987263B
Application number: CN202211555219.9A
Authority: CN
Inventors: 陈劲业; 王欢; 奉靖皓; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Radrock Shenzhen Technology Co Ltd
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2023-11-03
Anticipated expiration: 2042-12-06
Also published as: CN115987263A

Abstract

The application discloses a radio frequency switch circuit, which comprises a first switch unit and a second switch unit which are connected in series between a first terminal and a second terminal, wherein a first end of the first switch unit is coupled to the first terminal, a second end of the first switch unit is connected with a first end of the second switch unit, and a second end of the second switch unit is coupled to the second terminal; the first bias output end is connected to the bias control end of the first switch unit, the bias control end of the second switch unit and the connection nodes of the first switch unit and the second switch unit through the first acceleration passage and the second acceleration passage, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the acceleration passage so as to switch the states of the first switch unit and the second switch unit; therefore, the switching time of the circuit can be reduced, and the switching speed of the radio frequency switch circuit is higher.

Description

Radio frequency switch circuit and radio frequency front end module

Technical Field

The present application relates to the field of radio frequency technologies, and in particular, to a radio frequency switch circuit and a radio frequency front end module.

Background

With the rapid development of mobile communication technology, on a communication terminal, wireless communication is realized through a built-in radio frequency front-end circuit. The existing radio frequency front-end circuit generally comprises a baseband module, a radio frequency transceiver module, a radio frequency front-end module and an antenna link module; when the existing radio frequency front-end circuit processes complex radio frequency signals, multiple-input multiple-output (MIMO) technology is generally adopted to use multiple antennas at a transmitting end and a receiving end, and an antenna system of multiple channels is formed between the transmitting end and the receiving end, so that the channel capacity is improved. When the multiple antennas are used for transmitting and receiving radio frequency signals, the switching speed of the multiple paths of radio frequency signals at the radio frequency switching circuit is too low, so that the performance of the radio frequency switching circuit is poor.

Content of the application

The embodiment of the application provides a radio frequency switch circuit, which aims to solve the problem that the switching speed of the radio frequency switch circuit is too slow.

A radio frequency switching circuit comprising a sequence of switching cells connected in series between a first terminal and a second terminal, the sequence of switching cells comprising a first switching cell and a second switching cell, wherein a first end of the first switching cell is coupled to the first terminal, a second end of the first switching cell is connected to a first end of the second switching cell, and a second end of the second switching cell is coupled to the second terminal;

The accelerating circuit comprises a first accelerating path and a second accelerating path, wherein a first bias output end is connected to a bias control end of a first switch unit, a bias control end of a second switch unit and a connection node of the first switch unit and the second switch unit through the first accelerating path and the second accelerating path, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the accelerating path so as to switch states of the first switch unit and the second switch unit.

Further, the switching unit sequence further comprises a third switching unit, and the second bias output terminal is connected to a bias control terminal of the third switching unit through the first gate resistor.

Further, when the bias control voltage is positive pressure, the first acceleration channel is conducted, the second acceleration channel is turned off, and the bias control voltage is loaded on bias control ends of the first switch unit and the second switch unit through the first acceleration channel so as to switch states of the first switch unit and the second switch unit;

When the bias control voltage is negative pressure, the first accelerating channel is turned off, the second accelerating channel is turned on, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the second accelerating channel so as to switch the states of the first switch unit and the second switch unit.

Further, the first acceleration path comprises a first transistor, and the second acceleration path comprises a second transistor, wherein the first transistor and the second transistor are complementary transistors;

the first end of the first transistor is connected with the first end of the second transistor and is coupled to the bias control end of the first switch unit, the second end of the first transistor is connected with the second end of the second transistor and is coupled to the bias control end of the second switch unit, and the third end of the first transistor and the third end of the second transistor are connected and are coupled to the connection nodes of the first switch unit and the second switch unit.

Further, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor, where a source of the first transistor is connected to a source of the second transistor and is coupled to a bias control terminal of the first switching unit, a drain of the first transistor is connected to a drain of the second transistor and is coupled to a bias control terminal of the second switching unit, and a gate of the first transistor is connected to a gate of the second transistor and is coupled to a connection node of the first switching unit and the second switching unit.

Further, when the bias control voltage is positive, the gate drain voltage of the first transistor is negative, the gate drain voltage of the second transistor is negative, the first transistor is turned on, the second transistor is turned off, and the bias control voltage is loaded on bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch states of the first switch unit and the second switch unit;

when the bias control voltage is negative, the gate drain voltage of the first transistor is positive, the gate drain voltage of the second transistor is positive, the first transistor is turned off, the second transistor is turned on, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch the states of the first switch unit and the second switch unit.

Further, the first transistor is a PNP transistor, and the second transistor is an NPN transistor, where an emitter of the first transistor is connected to an emitter of the second transistor and is coupled to a bias control terminal of the first switching unit, a collector of the first transistor is connected to a collector of the second transistor and is coupled to a bias control terminal of the second switching unit, and a base of the first transistor is connected to a base of the second transistor and is coupled to a connection node of the first switching unit and the second switching unit.

Further, when the bias control voltage is positive, the base-emitter voltage of the first transistor is negative, the base-emitter voltage of the second transistor is negative, the first transistor is turned on, the second transistor is turned off, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch the states of the first switch unit and the second switch unit;

when the bias control voltage is negative, the base electrode-emitting electrode of the first transistor is positive, the base electrode-emitting electrode of the second transistor is positive, the first transistor is turned off, the second transistor is turned on, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch the states of the first switch unit and the second switch unit.

Further, the first switching unit includes at least one first field effect transistor, and the second switching unit includes at least one second field effect transistor; the grid of the first switch unit is a bias control end of the first switch unit, the source of the first switch unit is a first end of the first switch unit, and the drain of the first switch unit is a second end of the first switch unit; the grid of the second switch unit is a bias control end of the second switch unit, the source electrode of the second switch unit is a first end of the second switch unit, and the drain electrode of the second switch unit is a second end of the first switch unit.

Further, when the field effect transistor is an NMOS transistor, the first switch unit and the second switch unit are switched to an on state if the bias control voltage is a positive voltage, and the first switch unit and the second switch unit are switched to an off state if the bias control voltage is a negative voltage;

when the field effect transistor is a PMOS transistor, the first switch unit and the second switch unit are switched to an off state if the bias control voltage is positive, and the first switch unit and the second switch unit are switched to an on state if the bias control voltage is negative.

Further, the radio frequency switch circuit further comprises a first isolation resistor, and after the third end of the first transistor is connected with the third end of the second transistor, the third end of the first transistor is coupled to a connection node of the first switch unit and the second switch unit through the first isolation resistor.

Further, the resistance value of the first isolation resistor is 10KΩ -100KΩ.

Further, the radio frequency switch circuit further comprises at least one second isolation resistor, and the first bias output end is connected with the first acceleration path and the second acceleration path through the second isolation resistor.

Further, the resistance value of the second isolation resistor is 5KΩ -25KΩ.

Further, a first bias output is connected to the first end of the first transistor and the first end of the second transistor, and/or the first bias output is connected to the second end of the first transistor and the second end of the second transistor.

Further, the first bias output terminal is connected to the first terminal of the first transistor and the first terminal of the second transistor through one second isolation resistor, and/or is connected to the second terminal of the first transistor and the second terminal of the second transistor through another second isolation resistor.

Further, the first terminal is connected to the rf input terminal, the second terminal is connected to the rf output terminal, or the first terminal is connected to a first node on the signal transmission link, and the second terminal is connected to ground.

A radio frequency switching circuit comprising:

a switching unit series connected between a first terminal and a second terminal, the switching unit series including N switching units, wherein a first end of a 1 st switching unit of the N switching units is connected to the first terminal, a second end of the 1 st switching unit is connected to a first end of a 2 nd switching unit, a second end of an N-1 st switching unit is connected to a first end of an N-th switching unit, a second end of the N-th switching unit is connected to the second terminal, N is a positive integer, wherein the 1 st to N-th switching units connected to the first terminal constitute a first switching network; forming a second switching network from the n+1th switching unit to the N switching unit;

The accelerating circuit comprises a first accelerating path and a second accelerating path, and a first bias output end is connected to a bias control end of a switch unit in the first switch network and a connection node of two adjacent switch units in the first switch network through the first accelerating path and the second accelerating path; the bias control voltage is loaded on the bias control end of the switch unit in the first switch network through the first bias output end and the acceleration path so as to switch the state of the switch unit in the first switch network;

the first grid resistor and the second bias output end are connected to the bias control end of the switch unit in the second switch network through the first grid resistor so as to switch the state of the switch unit in the second switch network.

Further, the number of switching units in the first switching network is equal to or greater than the number of switching units in the second switching network.

The radio frequency front end module is characterized by comprising the radio frequency switch circuit.

The radio frequency switching circuit comprises a switching unit sequence connected in series between a first terminal and a second terminal, wherein the first switching unit and the second switching unit sequence comprise a first switching unit and a second switching unit, a first end of the first switching unit is coupled to the first terminal, a second end of the first switching unit is connected with a first end of the second switching unit, and a second end of the second switching unit is coupled to the second terminal; the accelerating circuit comprises a first accelerating path and a second accelerating path, a first bias output end is connected to a bias control end of a first switch unit, a bias control end of a second switch unit and a connection node of the first switch unit and the second switch unit through the first accelerating path and the second accelerating path, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the accelerating path so as to switch the states of the first switch unit and the second switch unit; the bias control voltage can be directly loaded on the bias control ends of the first switch unit and the second switch unit through the first acceleration passage or the second acceleration passage which are conducted, and the radio frequency switch circuit can be rapidly switched between on and off, so that the switching time of the circuit can be reduced, and the switching speed of the radio frequency switch circuit is higher.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a RF switch circuit according to an embodiment of the application;

FIG. 2 is another schematic diagram of an RF switch circuit according to an embodiment of the application;

FIG. 3 is another schematic diagram of an RF switch circuit according to an embodiment of the present application;

FIG. 4 is another schematic diagram of an RF switch circuit according to an embodiment of the application;

FIG. 5 is another schematic diagram of an RF switch circuit according to an embodiment of the application;

FIG. 6 is another schematic diagram of an RF switch circuit according to an embodiment of the application;

FIG. 7 is another schematic diagram of an RF switch circuit according to an embodiment of the application;

fig. 8 is another schematic diagram of a rf switch circuit according to an embodiment of the application.

In the figure: k1, a first switch unit; k2, a second switch unit; k3, a third switch unit; k4, a fourth switch unit; k5, a fifth switching unit; 10. a first acceleration path; 20. a second acceleration path; R1/R2/R3/R4, a first isolation resistor; R10/R20, second isolation resistor; P1/P2/P3/P4, second transistor; N1/N2/N3/N4, second transistor; 100. a first switching network; 200. a second switching network; R100/R200, a first gate resistance.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.

It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purpose of providing a thorough understanding of the present application, detailed structures and steps are presented in order to illustrate the technical solution presented by the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

The present embodiment provides a radio frequency switching circuit, as shown with reference to fig. 1 below, comprising a switching unit sequence connected in series between a first terminal and a second terminal, the first switching unit and the second switching unit sequence comprising a first switching unit K1 and a second switching unit K2, wherein a first end of the first switching unit K1 is coupled to the first terminal a, a second end of the first switching unit K1 is connected with a first end of the second switching unit K2, and a second end of the second switching unit K2 is coupled to the second terminal. It should be noted that the switching unit sequence of the present embodiment is exemplified by including the first switching unit K1 and the second switching unit K2, but is not limited to include a third switching unit, a fourth switching unit, or even more switching units. The first end of the first switch unit K1 is coupled to the first terminal a, which may be that the first end of the first switch unit K1 is directly connected to the first terminal a, or may be connected to the first terminal a through other components or switch units. The second end of the second switch unit K2 is coupled to the second terminal, which may be that the second end of the second switch unit K2 is directly connected to the second terminal, or may be connected to the second terminal through another component or a switch unit.

The accelerating circuit comprises a first accelerating path 10 and a second accelerating path 20, wherein a first bias output end is connected to a bias control end of a first switch unit K1, a bias control end of a second switch unit K2 and a connection node of the first switch unit K1 and the second switch unit K2 through the first accelerating path 10 and the second accelerating path 20, and bias control voltage is loaded on the bias control ends of the first switch unit K1 and the second switch unit K2 through the first bias output end and the accelerating path so as to switch states of the first switch unit K1 and the second switch unit K2.

As another example, referring to fig. 3 below, the switching unit sequence of N switching units (K1, K2, K3, K4, and K5 shown in fig. 3) wherein a first end of a 1 st switching unit K1 of the N switching units is connected to the first terminal a, a second end of the 1 st switching unit K1 is connected to a first end of a 2 nd switching unit K2, a second end of an N-1 st switching unit is connected to a first end of an N-th switching unit, and a second end of an N-th switching unit is connected to the second terminal, wherein N is a positive integer.

In a specific embodiment, referring to fig. 7 below, the first switching unit and the second switching unit include at least one transistor. The transistor is a field effect transistor (MOS transistor). As an example, the first end of the transistor is the drain and the second end of the transistor is the source. The drain electrode of the 1 st switch unit in the N switch units is connected with the first terminal, the source electrode of the 1 st switch unit is connected with the drain electrode of the 2 nd switch unit, the source electrode of the N-1 st switch unit is connected with the drain electrode of the N switch unit, and the source electrode of the N switch unit is connected with the second terminal, wherein N is a positive integer. Alternatively, the first terminal of the transistor is the source and the second terminal of the transistor is the drain. The source electrode of the 1 st switch unit in the N switch units is connected with the first terminal, the drain electrode of the 1 st switch unit is connected with the source electrode of the 2 nd switch unit, the drain electrode of the N-1 st switch unit is connected with the source electrode of the N switch unit, and the drain electrode of the N switch unit is connected with the second terminal, wherein N is a positive integer.

The accelerating circuit comprises a first accelerating path 10 and a second accelerating path 20, wherein a first bias output end is connected to a bias control end of the first switch unit, a bias control end of the second switch unit and a connection node of the first switch unit and the second switch unit through the first accelerating path 10 and the second accelerating path 20, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the accelerating path so as to switch states of the first switch unit and the second switch unit. It should be noted that, the first bias output terminal in this embodiment is an output terminal for outputting the bias control voltage through the bias network.

Wherein the first acceleration path 10 is a path composed of one or more cascaded first transistors. The second acceleration path 20 is a path consisting of one or more cascaded second transistors. Wherein the first transistor and the second transistor are complementary transistors. For example: if the first transistor and the second transistor are field effect transistors, the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, or the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, that is, the PMOS transistor and the NMOS transistor are complementary transistors. If the first transistor and the second transistor are heterojunction bipolar transistors, the first transistor is a PNP transistor, the second transistor is an NPN transistor, or the first transistor is an NPN transistor, and the second transistor is a PNP transistor, that is, the NPN transistor and the PNP transistor are complementary transistors.

The first bias output end is connected to the bias control end of the first switch unit, the bias control end of the second switch unit and the connection nodes of the first switch unit and the second switch unit through the first acceleration path 10 and the second acceleration path 20, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the acceleration path so as to switch the states of the first switch unit and the second switch unit. In a specific embodiment, the first acceleration path 10 and the second acceleration path 20 are formed by two complementary transistor cascades. Therefore, after the bias control voltage is output to the acceleration channels through the first bias output end, one of the acceleration channels 10 and the second acceleration channel 20 is turned on, and the other acceleration channel is turned off, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the on acceleration channel, so that the states of the first switch unit and the second switch unit are switched.

As an example, the bias control voltage is positive (3V), the first transistor in the first acceleration path 10 is a PMOS transistor, the second transistor in the second acceleration path 20 is an NMOS transistor, the bias control voltage (3V) is applied to the source and drain of each PMOS transistor in the first acceleration path 10, and the source and drain of each NMOS transistor in the second acceleration path 10. Since the gate voltage of each PMOS transistor in the first acceleration path 10 is 0V, and the gate voltage of each NMOS transistor in the second acceleration path 20 is 0V, the gate-source voltage Vgd of each PMOS transistor in the first acceleration path 10 is (0-Vpos) negative pressure, and the gate-source voltage Vgd of each NMOS transistor in the second acceleration path 20 is (0-Vpos) negative pressure. Based on that the PMOS transistors are negative-voltage-on and the NMOS transistors are positive-voltage-on, each PMOS transistor in the first acceleration path 10 is turned on, each NMOS transistor in the second acceleration path 20 is turned off, the bias control voltage (3V) is loaded on the bias control ends of the first switch unit and the second switch unit through the first acceleration path 10, at this time, the gate voltages of the first switch unit and the second switch unit are positive-voltage, and the source voltages and the drain voltages of the first switch unit and the second switch unit are OV. When the first switch unit and the second switch unit are NMOS transistors, the first switch unit and the second switch unit are switched to an off state, and when the first switch unit and the second switch unit are PMOS transistors, the first switch unit and the second switch unit are switched to an on state.

It should be noted that, since the accelerating circuit in this embodiment includes the first accelerating path 10 and the second accelerating path 20, and only one of the accelerating paths is in the on state after the bias control voltage is output to the accelerating path through the first bias output terminal, and the other accelerating path is in the off state, the first switch unit and the second switch unit may be switched from the on state to the off state or from the off state to the on state in cooperation with each other, compared with the bias control voltage in the related art that the bias control voltage is loaded on the bias control terminals of the first switch unit and the second switch unit through the gate bias resistor, the bias control voltage in this embodiment does not need to be connected with the gate bias resistor.

In a specific embodiment, referring to fig. 2 below, the switching unit sequence further includes a third switching unit K3, and the second bias output terminal is connected to a bias control terminal of the third switching unit K3 through a first gate resistor R100. Alternatively, the third switching unit K3 may be connected to the first switching unit K1 or may be connected to the second switching unit K2.

Specifically, the first bias output end is connected to the bias control end of the first switch unit K1, the bias control end of the second switch unit K2 and the connection node of the first switch unit K1 and the second switch unit K2 through the first acceleration path and the second acceleration path; the second bias output terminal is connected to the bias control terminal of the fourth switching unit K4 through the gate bias resistor R100, and to the bias control terminal of the third switching unit K3 through the first gate resistor R100. It should be noted that, in this embodiment, the first bias output end is connected to the bias control ends of at least two switch units and the connection nodes of the two adjacent switch units through the first acceleration path and the second acceleration path, and compared with the bias control voltage in the related art that is loaded on the bias control end of each switch unit through the gate bias resistor, the switching time of the radio frequency switch circuit in this embodiment can be reduced, and the switching speed is faster. The second bias output end and the first bias output end can be the same output end in a bias network or two different output ends.

Preferably, as shown in fig. 3 below, when the switching unit sequence includes a plurality of switching units, the first bias output terminal is connected to the bias control terminal of each switching unit and the connection node of every two adjacent switching units through the first acceleration path and the second acceleration path, and at this time, the switching speed of the radio frequency switching circuit is faster.

In this embodiment, the radio frequency switching circuit includes a switching unit sequence sequentially connected in series between a first terminal and a second terminal, the first switching unit and the second switching unit sequence including a first switching unit and a second switching unit, wherein a first end of the first switching unit is coupled to the first terminal, a second end of the first switching unit is connected to a first end of the second switching unit, and a second end of the second switching unit is coupled to the second terminal; the accelerating circuit comprises a first accelerating path and a second accelerating path, a first bias output end is connected to a bias control end of a first switch unit, a bias control end of a second switch unit and a connection node of the first switch unit and the second switch unit through the first accelerating path and the second accelerating path, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the accelerating path so as to switch the states of the first switch unit and the second switch unit; the bias control voltage can be directly loaded on the bias control ends of the first switch unit and the second switch unit through the first acceleration passage or the second acceleration passage which are conducted, and the radio frequency switch circuit can be rapidly switched between on and off, so that the switching time of the circuit can be reduced, and the switching speed of the radio frequency switch circuit is higher.

In a specific embodiment, when the bias control voltage Vbias is positive (e.g., +3v), the first accelerating path 10 is turned on, the second accelerating path 20 is turned off, and the bias control voltage Vbias is loaded on the bias control terminals of the first switch unit and the second switch unit through the first accelerating path 10 to switch the states of the first switch unit and the second switch unit.

When the bias control voltage is negative (for example, -3V), the first accelerating path 10 is turned off, the second accelerating path 20 is turned on, and the bias control voltage Vbias is loaded on the bias control terminals of the first switch unit and the second switch unit through the second accelerating path 20 to switch the states of the first switch unit and the second switch unit.

It is understood that, regardless of whether the bias control voltage is positive or negative, one of the first and second acceleration paths is on and the other is off. Whether the first acceleration path is in an on or off state is related to the magnitude of the bias control voltage and to the type of first transistor in the first acceleration path. Likewise, whether the second acceleration path is in an on or off state is related to the magnitude of the bias control voltage and to the type of second transistor in the second acceleration path.

In this embodiment, the first transistor in the first acceleration path is a PMOS transistor, and the second transistor in the second acceleration path 20 is an NMOS transistor.

As an example, when the bias control voltage Vbias is positive (e.g., +3v), the bias control voltage (+3v) is applied to the source and drain of each PMOS transistor in the first acceleration path 10 and to the source and drain of each NMOS transistor in the second acceleration path 20. Since the gate of each PMOS in the first accelerating path 10 and the gate of each NMOS in the second accelerating path 20 are connected and then connected to the connection node of the two adjacent switching units, the voltage at the connection node of the two adjacent switching units is 0, so the gate voltage of each PMOS in the first accelerating path 10 is 0V, the gate voltage of each NMOS in the second accelerating path 20 is 0V, at this time, the gate-source voltage Vgd of each PMOS in the first accelerating path 10 is (0-Vpos) negative pressure, and the gate-source voltage Vgd of each NMOS in the second accelerating path 20 is (0-Vpos) negative pressure. Based on that the PMOS transistors are negative-voltage-on and the NMOS transistors are positive-voltage-on, each PMOS transistor in the first acceleration path 10 is turned on, each NMOS transistor in the second acceleration path 20 is turned off, the bias control voltage (3V) is loaded on the bias control ends of the first switch unit and the second switch unit through the first acceleration path 10, at this time, the gate voltages of the first switch unit and the second switch unit are positive-voltage, and the source voltages and the drain voltages of the first switch unit and the second switch unit are OV. If the first switch unit and the second switch unit are NMOS tubes, the first switch unit and the second switch unit are switched to an off state, and if the first switch unit and the second switch unit are PMOS tubes, the first switch unit and the second switch unit are switched to an on state.

As another example, when the bias control voltage Vbias is negative (e.g., -3V), the bias control voltage (-3V) is applied to the source and drain of each PMOS transistor in the first accelerating path 10 and to the source and drain of each NMOS transistor in the second accelerating path 20. Since the gate voltage of each PMOS in the first acceleration path 10 is 0V, and the gate voltage of each NMOS in the second acceleration path 20 is 0V, the gate-source voltage Vgd of each PMOS in the first acceleration path 10 is a positive (0-Vneg) voltage, and the gate-source voltage Vgd of each NMOS in the second acceleration path 20 is a positive (0-Vneg) voltage. Based on that the PMOS transistors are negative-voltage on and the NMOS transistors are positive-voltage on, each PMOS transistor in the first accelerating path 10 is turned off, each NMOS transistor in the second accelerating path 20 is turned on, the bias control voltage (-3V) is loaded on the bias control ends of the first switch unit and the second switch unit through the first accelerating path 10, at this time, the gate voltages of the first switch unit and the second switch unit are negative-voltage, and the source voltages and the drain voltages of the first switch unit and the second switch unit are OV. If the first switch unit and the second switch unit are NMOS tubes, the first switch unit and the second switch unit are switched to an on state, and if the first switch unit and the second switch unit are PMOS tubes, the first switch unit and the second switch unit are switched to an off state.

In this embodiment, when the bias control voltage is positive, the first acceleration path is turned on, and the second acceleration path is turned off, and the bias control voltage is loaded on bias control ends of the first switch unit and the second switch unit through the first acceleration path, so as to switch states of the first switch unit and the second switch unit; when the bias control voltage is negative pressure, the first accelerating channel is turned off, the second accelerating channel is turned on, and the bias control voltage is loaded on bias control ends of the first switch unit and the second switch unit through the second accelerating channel so as to switch states of the first switch unit and the second switch unit; in this embodiment, the bias control signals are loaded on the bias control ends of the first switch unit and the second switch unit through the first acceleration path and the second acceleration path, and gate resistors are not required to be additionally connected to the bias control ends of the first switch unit and the second switch unit, so that the switching time of the circuit can be reduced, and the switching speed of the radio frequency switch circuit is faster.

In a specific embodiment, the first acceleration path includes a first transistor and the second acceleration path includes a second transistor, wherein the first transistor and the second transistor are complementary transistors.

As an example, if the first transistor and the second transistor are field effect transistors, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, or the first transistor is an NMOS transistor and the second transistor is a PMOS transistor, that is, the PMOS transistor and the NMOS transistor are complementary transistors. If the first transistor and the second transistor are heterojunction bipolar transistors, the first transistor is a PNP transistor, the second transistor is an NPN transistor, or the first transistor is an NPN transistor, and the second transistor is a PNP transistor, that is, the NPN transistor and the PNP transistor are complementary transistors.

As an example, referring to fig. 1 below, when the first acceleration path includes a first transistor, the second acceleration path includes a second transistor. The first end of the first transistor is connected with the first end of the second transistor and is coupled to the bias control end of the first switch unit, the second end of the first transistor is connected with the second end of the second transistor and is coupled to the bias control end of the second switch unit, and the third end of the first transistor and the third end of the second transistor are connected and are coupled to the connection nodes of the first switch unit and the second switch unit.

As another example, referring to fig. 3 below, when the first acceleration path includes a plurality of first transistors, the second acceleration path includes a plurality of second transistors. The first end of each first transistor is connected with the first end of a corresponding second transistor and is coupled to the bias control end of a corresponding switch unit, the second end of each first transistor is connected with the second end of a corresponding second transistor and is coupled to the bias control end of a corresponding switch unit, the third end of each first transistor is connected with the third end of a corresponding second transistor and is coupled to the connecting node of two adjacent corresponding switch units, the first end of a previous first transistor in M first transistors is connected with the second end of a next first transistor, and the first end of a previous second transistor in M second transistors is connected with the second end of a next second transistor.

As an example, if the first transistor and the second transistor are field effect transistors, the first end of the first transistor and the first end of the second transistor may be sources, the second end of the first transistor and the second end of the second transistor are drains, and the third end of the first transistor and the third end of the second transistor are gates; alternatively, the first end of the first transistor and the first end of the second transistor may be drains, the second end of the first transistor and the second end of the second transistor may be sources, and the third end of the first transistor and the third end of the second transistor may be gates.

As an example, if the first transistor and the second transistor are heterojunction bipolar transistors, the first end of the first transistor and the first end of the second transistor may be collectors, the second end of the first transistor and the second end of the second transistor are emitters, and the third end of the first transistor and the third end of the second transistor are bases; alternatively, the first end of the first transistor and the first end of the second transistor may be emitters, the second end of the first transistor and the second end of the second transistor may be collectors, and the third end of the first transistor and the third end of the second transistor may be bases.

Wherein the areas of the first transistor and the second transistor may be the same or different. Preferably, the first transistor and the second transistor have the same area. Further, the areas of the first transistor and the second transistor in the present embodiment are much smaller than the area of each of the first switching unit and the second switching unit.

In the present embodiment, the number M of the first transistors and the number M of the second transistors are smaller than the number N of the switching units included in the switching unit sequence. Preferably, the number M of the first transistors and the number M of the second transistors are smaller than the number N of the switching units included in the switching unit sequence by 1. For example: the number N of switching units included in the switching unit sequence is 5, and the number M of the first transistors and the number M of the second transistors are 4; thus, the first end of each first transistor is connected with the first end of the corresponding second transistor and then coupled to the bias control end of the corresponding one of the switch units, the second end of each first transistor is connected with the second end of the corresponding one of the second transistors and then coupled to the bias control end of the corresponding one of the switch units, and the third end of each first transistor and the third end of the corresponding one of the second transistors are connected and then coupled to the connection node of each two adjacent switch units.

It is understood that, in this embodiment, the voltage of the third terminal of the first transistor and the voltage of the third terminal of the second transistor, and the voltage on the connection node of the first switching unit and the second switching unit are both 0. The voltages of the first terminal of the first transistor and the first terminal of the second transistor, the voltages of the second terminal of the first transistor and the second terminal of the second transistor, and the voltages of the bias control terminals of the first switching unit and the second switching unit are all related to the bias control voltage. If the bias control voltage is positive, the voltages of the first end of the first transistor and the first end of the second transistor, the voltages of the second end of the first transistor and the second end of the second transistor, and the voltages of the bias control ends of the first switch unit and the second switch unit are positive, and the voltages on the connection nodes of the first switch unit and the second switch unit are zero. If the bias control voltage is negative, the voltages of the first end of the first transistor and the first end of the second transistor, the voltages of the second end of the first transistor and the second end of the second transistor, and the voltages of the bias control ends of the first switch unit and the second switch unit are also negative,

As an example, for the first acceleration path, M first transistors are connected in cascade, a second terminal of a first transistor is coupled to a bias control terminal of a first switching unit, a first terminal of a last first transistor is coupled to a bias control terminal of a last switching unit, and a first terminal of a previous first transistor of the M first transistors is connected to a second terminal of a subsequent first transistor and is coupled to a bias control terminal of a corresponding one of the switching units. For the second acceleration path, M second transistors are connected in cascade, a second end of a first second transistor is coupled to the bias control end of the first switching unit, a first end of a last second transistor is coupled to the bias control end of the last switching unit, and a first end of a previous first transistor of the M second transistors is connected to a second end of a subsequent second transistor and is coupled to the bias control end of a corresponding one of the switching units.

Referring to fig. 3 below, the second terminal of the first transistor P1 is connected to the second terminal of the first second transistor N1 and coupled to the bias control terminal of the first switching unit K1, the first terminal of the first transistor P1 is connected to the first terminal of the first second transistor N1 and coupled to the bias control terminal of the second switching unit K2, and the third terminal of the first transistor P1 is connected to the third terminal of the first second transistor N1 and coupled to the connection node of the first switching unit K1 and the second switching unit K2. The first terminal of the second first transistor P2 is connected to the first terminal of the second transistor N2 and coupled to the bias control terminal of the third switching unit K3, and the third terminal of the second first transistor P2 is connected to the third terminal of the second transistor N2 and coupled to the connection node of the second switching unit K2 and the third switching unit K3. The first terminal of the third first transistor P3 is connected to the first terminal of the third second transistor N3 and coupled to the bias control terminal of the fourth switching unit K4, and the third terminal of the third first transistor P3 is connected to the third terminal of the third second transistor N3 and coupled to the connection node of the third switching unit K3 and the fourth switching unit K4. The first terminal of the fourth first transistor P4 is connected to the first terminal of the fourth second transistor N4 and coupled to the bias control terminal of the fifth switching unit K5, and the third terminal of the fourth first transistor P4 is connected to the third terminal of the fourth second transistor N4 and coupled to the connection node of the fourth switching unit K4 and the fifth switching unit K5.

In a specific embodiment, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor, where a source of the first transistor is connected to a source of the second transistor and is coupled to a bias control terminal of the first switching unit, a drain of the first transistor is connected to a drain of the second transistor and is coupled to a bias control terminal of the second switching unit, and a gate of the first transistor is connected to a gate of the second transistor and is coupled to a connection node of the first switching unit and the second switching unit.

If the first acceleration path includes M first transistors, and the second acceleration path includes M second transistors, a source of a preceding first transistor is connected to a drain of a succeeding first transistor among the M first transistors, and a source of a preceding second transistor is connected to a drain of a succeeding second transistor among the M second transistors.

As another example, since the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, and the NMOS transistor is positive voltage on based on the PMOS transistor being negative voltage on. Therefore, when the bias control voltage is positive, the gate drain voltage Vgd of the first transistor is (0-Vpos) negative voltage, the gate drain voltage Vgd of the second transistor is (0-Vpos) negative voltage, at this time, the first transistor is turned on, the second transistor is turned off, the bias control voltage is loaded on the bias control terminals of the first switch unit and the second switch unit through the first transistor, the voltage of the bias control terminals of the first switch unit and the second switch unit is equal to the bias control voltage, and the voltage on the connection node of the first switch unit and the second switch unit is zero, so as to realize the state switching of the first switch unit and the second switch unit.

As another example, since the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, and the NMOS transistor is positive voltage on based on the PMOS transistor being negative voltage on. Therefore, when the bias control voltage is negative, the gate drain voltage Vgd of the first transistor is positive (0-Vneg), the gate drain voltage Vgd of the second transistor is positive (0-Vneg), the first transistor is turned off, the second transistor is turned on, the bias control voltage is loaded on the bias control terminals of the first switching unit and the second switching unit through the first transistor, the voltage of the bias control terminals of the first switching unit and the second switching unit is equal to the bias control voltage, and the voltage on the connection node of the first switching unit and the second switching unit is zero, so as to realize switching of the states of the first switching unit and the second switching unit.

In a specific embodiment, the first transistor is a PNP transistor, and the second transistor is an NPN transistor, wherein an emitter of the first transistor is connected to an emitter of the second transistor and is coupled to a bias control terminal of the first switching unit, a collector of the first transistor is connected to a collector of the second transistor and is coupled to a bias control terminal of the second switching unit, and a base of the first transistor is connected to a base of the second transistor and is coupled to a connection node of the first switching unit and the second switching unit.

If the first acceleration path includes M first transistors and the second acceleration path includes M second transistors, a collector of a preceding first transistor is connected to a drain emitter of a succeeding first transistor among the M first transistors, and a collector of a preceding second transistor is connected to an emitter of a succeeding second transistor among the M second transistors.

As an example, since the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the NPN transistor is positive-voltage-on based on the PNP transistor being negative-voltage-on. Therefore, when the bias control voltage is positive, the base-emitter voltage of the first transistor is (0-Vpos) negative voltage, the base-emitter voltage of the second transistor is (0-Vpos) negative voltage, the first transistor is turned on, the second transistor is turned off, the bias control voltage is loaded on the bias control terminals of the first switch unit and the second switch unit through the first transistor, the voltage of the bias control terminals of the first switch unit and the second switch unit is equal to the bias control voltage, and the voltage on the connection node of the first switch unit and the second switch unit is zero, so that the state of the first switch unit and the second switch unit is switched.

As another example, since the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the NPN transistor is positive voltage on based on the PNP transistor being negative voltage on. Therefore, when the bias control voltage is negative, the base-emitter of the first transistor is positive (0-Vneg), the base-emitter of the second transistor is positive (0-Vneg), the first transistor is turned off, the second transistor is turned on, the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first transistor, the voltage of the bias control ends of the first switch unit and the second switch unit is equal to the bias control voltage, and the voltage on the connection node of the first switch unit and the second switch unit is zero, so that the state of the first switch unit and the second switch unit is switched.

In a specific embodiment, the first switching unit comprises at least one first field effect transistor, and the second switching unit comprises at least one second field effect transistor; the grid of the first switch unit is a bias control end of the first switch unit, the source of the first switch unit is a first end of the first switch unit, and the drain of the first switch unit is a second end of the first switch unit; the grid of the second switch unit is a bias control end of the second switch unit, the source electrode of the second switch unit is a first end of the second switch unit, and the drain electrode of the second switch unit is a second end of the first switch unit.

It should be noted that, if the switching unit needs to include N switching units, the drain electrode of the previous switching unit is connected to the source electrode of the next switching unit among the N switching units. As an example, the source of a first switch unit of the N switch units is connected to the first terminal, the drain of the first switch unit is connected to the source of a second switch unit, the drain of the N-1 th switch unit is connected to the source of the N-th switch unit, and the drain of the N-th switch unit is connected to the second terminal, where N is a positive integer. Because the drain electrode of the previous switch unit is directly connected with the source electrode of the next switch unit in the N switch units, the connecting nodes of the two adjacent first switch units and the second switch unit are the drain electrode of the previous switch unit or the source electrode of the next switch unit. Since the connection nodes of the adjacent two first switch units and the second switch units are connected with the third end of the first transistor in the first acceleration path and the third end of the second transistor in the second acceleration path, the voltage on the connection nodes of the adjacent two first switch units and the second switch units is zero, that is, the drain voltage of the previous switch unit and the source voltage of the next switch unit in the adjacent two first switch units and the second switch unit are also zero.

The gates of the first switch unit and the second switch unit are bias control ends of the first switch unit and the second switch unit, namely bias control voltages output by the bias control ends are loaded on the gates of the first switch unit and the second switch unit. In one embodiment, when the field effect transistor is an NMOS transistor, the first switch unit and the second switch unit are switched to an on state if the bias control voltage is a positive voltage, and the first switch unit and the second switch unit are switched to an off state if the bias control voltage is a negative voltage.

It can be appreciated that when the field effect transistor is an NMOS transistor, the first switch unit and the second switch unit are positive voltage on. Therefore, if the bias control voltage is positive, the gate voltages applied to the first and second switching elements through the first acceleration path 10 are also positive, and the source voltages and the drain voltages of the first and second switching elements are zero, so that the gate-source voltages Vgd of the first and second switching elements are positive (0-Vneg), and the first and second switching elements are switched to the on state. If the bias control voltage is negative, the gate voltages applied to the first and second switching units through the second acceleration path 20 are also negative, and since the source voltages and drain voltages of the first and second switching units are zero, the gate-source voltages Vgd of the first and second switching units are (0-Vpos) negative voltages, and the first and second switching units are switched to an off state.

When the field effect transistor is a PMOS tube, the first switch unit and the second switch unit are conducted under negative voltage. Therefore, if the bias control voltage is positive, the gate voltages applied to the first and second switching elements through the first acceleration path 10 are also positive, and the source voltages and the drain voltages of the first and second switching elements are zero, so that the gate-source voltages Vgd of the first and second switching elements are positive (0-Vneg), and the first and second switching elements are switched to the off state. If the bias control voltage is negative, the gate voltages applied to the first and second switching units through the second acceleration path 20 are also negative, and since the source voltages and drain voltages of the first and second switching units are zero, the gate-source voltages Vgd of the first and second switching units are (0-Vpos) negative voltages, and the first and second switching units are switched to an on state.

In a specific embodiment, the radio frequency switch circuit further includes a first isolation resistor, and after the third terminal of the first transistor is connected to the third terminal of the second transistor, the radio frequency switch circuit is coupled to a connection node of the first switch unit and the second switch unit through the first isolation resistor.

As an example, referring to fig. 4 below, the radio frequency switch circuit further includes a plurality of first isolation resistors (R1/R2/R3/R4 shown in fig. 4), and after the third terminal of the first transistor is connected to the third terminal of a corresponding second transistor, the third terminal of the first transistor is coupled to the connection node of two adjacent switch units through one first isolation resistor.

As an example, after the third terminal of the first transistor P1 in the first acceleration path and the third terminal of the first second transistor N1 in the second acceleration path are connected, the first transistor P1 is coupled to the connection node of the corresponding adjacent first switch unit K1 and second switch unit K2 through one of the first isolation resistors R1; after the third end of the second first transistor P2 in the first accelerating path is connected with the third end of the second transistor N2 in the second accelerating path, the second accelerating path is coupled to the connection node of the second switching unit K2 and the second switching unit K3 which are adjacent correspondingly through one first isolation resistor R2; after the third end of the third first transistor P3 in the first accelerating path and the third end of the third second transistor N3 in the second accelerating path are connected, the third end of the third first transistor P3 and the third end of the third second transistor N3 in the second accelerating path are coupled to the connection nodes of the corresponding adjacent third switch unit K3 and fourth switch unit K4 through one first isolation resistor R3; after the third end of the fourth first transistor P4 in the first acceleration path and the third end of the fourth second transistor N4 in the second acceleration path are connected, the third end of the fourth first transistor P4 is coupled to the connection node of the corresponding adjacent fourth switching unit K4 and fifth switching unit K5 through one of the first isolation resistors R4.

In this embodiment, after the third end of each first transistor is connected to the third end of a corresponding second transistor, the third end of each first transistor is coupled to the connection node of two adjacent corresponding switch units through one first isolation resistor, and the isolation resistor can block the radio frequency signals passing through the switch unit sequence from flowing backwards to the bias control end through the acceleration channel, so that generation of harmonic signals is avoided, and stability and linearity of the radio frequency switch circuit are improved.

In a specific embodiment, the resistance value of the first isolation resistor is preferably 10kΩ -100kΩ. It can be understood that the larger the resistance value of the first isolation resistor, the better the capability of blocking the reverse flow of the radio frequency signal, but the switching speed of the switch unit in the radio frequency switch circuit is also affected. Therefore, a suitable resistance value can be selected according to the actual application.

In a specific embodiment, referring to fig. 5 below, the radio frequency switch circuit further includes at least one second isolation resistor R10, and the first bias output terminal is connected to the first acceleration path and the second acceleration path through the second isolation resistor R10. The second isolation resistor R10 is used for blocking the radio frequency signal passing through the switching unit sequence from flowing back to the first bias output end through the acceleration path. The second isolation resistor R10 is arranged between the first bias output end and the accelerating path; therefore, the backflow of the radio frequency signal passing through the switching unit sequence to the first bias output end through the acceleration channel can be further prevented, generation of harmonic signals is avoided, and stability and linearity of the radio frequency switching circuit are further improved.

In a specific embodiment, a first bias output is connected to the first end of the first transistor and the first end of the second transistor, and/or the first bias output is connected to the second end of the first transistor and the second end of the second transistor.

In this embodiment, when the first acceleration path includes a plurality of first transistors, the second acceleration path includes a plurality of second transistors. Since each of the first transistors in the first acceleration path is connected to each other, each of the second transistors in the second acceleration path is connected to each other, and each of the first transistors in the first acceleration path and each of the second transistors in the second acceleration path are also connected to each other, the first bias output terminal may be connected to the first end or the second end of any one of the first transistors in the first acceleration path, and/or may be connected to the first end or the second end of any one of the second transistors in the second acceleration path, so that the bias control voltage may be applied to each of the first transistors in the first acceleration path and each of the second transistors in the second acceleration path.

Preferably, in this embodiment, the first bias output is connected to and/or connected to the first terminal of the first transistor and the first terminal of the first second transistor, and/or the first bias output is connected to and/or connected to the second terminal of the last first transistor and the second terminal of the last second transistor.

In this embodiment, the first bias output terminal is connected to and/or connected to the first terminal of the first transistor and the first terminal of the first second transistor, and/or the first bias output terminal is connected to the second terminal of the last first transistor and the second terminal of the last second transistor, so that uniformity of bias control voltages distributed over each first transistor and each second transistor can be ensured, and uniformity of bias control voltages distributed over bias control terminals of the switching unit can be ensured.

In a specific embodiment, the first bias output terminal is connected to the first terminal of the first transistor and the first terminal of the second transistor through a second isolation resistor, and/or is connected to the second terminal of the first transistor and the second terminal of the second transistor through another second isolation resistor.

As an example, referring to fig. 5 and 6 below, when the first acceleration path includes a plurality of first transistors, the second acceleration path includes a plurality of second transistors. The first bias output end of the embodiment is connected with the first end of the first transistor and the first end of the first second transistor through one second isolation resistor 10, and/or is connected with the second end of the last first transistor and the second end of the last second transistor through another second isolation resistor 20, so that uniformity of bias control voltages distributed on each first transistor and each second transistor can be ensured, and on the premise of ensuring uniformity of bias control voltages distributed on bias control ends of the switch units, radio frequency signals passing through the switch unit sequence are further blocked from flowing back to the first bias output end through the acceleration channel, so that generation of harmonic signals is avoided, and stability and linearity of the radio frequency switch circuit are improved.

In a specific embodiment, the resistance value of the second isolation resistor is 5kΩ -25kΩ. It can be understood that the larger the resistance value of the second isolation resistor, the better the capability of blocking the reverse flow of the radio frequency signal, but the switching speed of the switch unit in the radio frequency switch circuit is also affected. Therefore, a suitable resistance value can be selected according to the actual application.

In a specific embodiment, the first terminal a is connected to the radio frequency input terminal RFIN, and the second terminal is connected to the radio frequency output terminal RFOUT. Alternatively, the first terminal is connected to a first node on a signal transmission link and the second terminal is connected to ground.

In an example, when the first terminal a is connected to the rf input terminal RFIN and the second terminal is connected to the rf output terminal RFOUT, the switch unit in the rf switch circuit transmits the rf signal input from the rf input terminal RFIN to the rf output terminal when in the on state. At this time, the radio frequency switch circuit is a series arm circuit provided between the radio frequency input terminal RFIN and the radio frequency output terminal RFOUT.

In one example, when the first terminal is connected to a first node on a signal transmission link, the second terminal is connected to ground, the signal transmission link is a series arm circuit disposed between the radio frequency input terminal RFIN and the radio frequency output terminal RFOUT. The signal transmission link includes a plurality of cascaded transistors. Illustratively, the signal transmission link comprises a plurality of cascaded transistors, wherein the drain electrode of a first transistor in the signal transmission link is connected with the signal input end RFIN, the source electrode of the first transistor is connected with the drain electrode of a second transistor, the source electrode of an a-1 th transistor is connected with the drain electrode of an a-th transistor, and the source electrode of the a-th transistor is connected with the signal output end RFOUT, wherein M is more than or equal to 2, and 2 is more than or equal to a is less than or equal to M. The first end of the radio frequency switch circuit is connected to the first node of the signal transmission link, and the second end of the radio frequency switch circuit is connected to the ground. The first node may be a connection node of any two adjacent transistors in the signal transmission link. At this time, the radio frequency switching circuit is a parallel arm circuit provided between the signal transmission link and ground.

The present application also provides a radio frequency switch circuit, as shown in fig. 8 below, comprising: a switching unit series connected between a first terminal and a second terminal, the switching unit series including N switching units, wherein a first end of a 1 st switching unit of the N switching units is connected to the first terminal, a second end of the 1 st switching unit is connected to a first end of a 2 nd switching unit, a second end of an N-1 st switching unit is connected to a first end of an N-th switching unit, a second end of the N-th switching unit is connected to the second terminal, N is a positive integer, wherein 1 st to N-th switching units connected to the first terminal constitute a first switching network 100; the second switching network 200 is formed from the n+1th switching unit to the nth switching unit.

As an example, the switching unit includes at least one transistor. The transistor is a field effect transistor (MOS transistor). The first end of the transistor is a drain electrode, and the second end of the transistor is a source electrode. The drain electrode of the 1 st switch unit in the N switch units is connected with the first terminal, the source electrode of the 1 st switch unit is connected with the drain electrode of the 2 nd switch unit, the source electrode of the N-1 st switch unit is connected with the drain electrode of the N switch unit, and the source electrode of the N switch unit is connected with the second terminal, wherein N is a positive integer. Alternatively, the first terminal of the transistor is the source and the second terminal of the transistor is the drain. The source electrode of the 1 st switch unit in the N switch units is connected with the first terminal, the drain electrode of the 1 st switch unit is connected with the source electrode of the 2 nd switch unit, the drain electrode of the N-1 st switch unit is connected with the source electrode of the N switch unit, and the drain electrode of the N switch unit is connected with the second terminal, wherein N is a positive integer.

The accelerating circuit comprises a first accelerating path and a second accelerating path, and a first bias output end is connected to a bias control end of a switch unit in the first switch network and a connection node of two adjacent switch units in the first switch network through the first accelerating path and the second accelerating path; the bias control voltage is loaded on the bias control end of the switch unit in the first switch network through the first bias output end and the acceleration path so as to switch the state of the switch unit in the first switch network.

The first bias output end is connected to the bias control end of the switch unit in the first switch network and the connection node of two adjacent switch units in the first switch network through the first acceleration path 10 and the second acceleration path 20, and bias control voltage is loaded on the bias control end of the switch unit in the first switch network through the first bias output end and the acceleration path so as to switch the state of the switch unit in the first switch network. In a specific embodiment, the first acceleration path 10 and the second acceleration path 20 are formed by two complementary transistor cascades. Therefore, after the bias control voltage is output to the acceleration path through the first bias output end, one of the acceleration paths 10 and 20 is turned on, and the other acceleration path is turned off, and the bias control voltage is loaded on the bias control end of the switch unit in the first switch network through one of the turned-on acceleration paths, so that the state of the switch unit in the first switch network is switched.

Specifically, a first bias output end is connected to a bias control end of a switch unit in the first switch network and a connection node of two adjacent switch units in the first switch network through the first acceleration path and the second acceleration path; the second bias output terminal is connected to a bias control terminal of a switching unit in the second switching network through a gate bias resistor (e.g., R100/R200) to switch the state of the switching unit in the second switching network. It should be noted that, in this embodiment, the first bias output end is connected to the bias control ends of at least two switch units and the connection nodes of the two adjacent switch units through the first acceleration path and the second acceleration path, and compared with the bias control voltage in the related art that is loaded on the bias control end of each switch unit through the gate bias resistor, the switching time of the radio frequency switch circuit in this embodiment can be reduced, and the switching speed is faster. The second bias output end and the first bias output end can be the same output end in a bias network or two different output ends.

Further, in a specific embodiment, the number of switching units in the first switching network is greater than or equal to the number of switching units in the second switching network. For example: the number of the switch units in the first switch network is 3 (K1/K2/K3), and the number of the switch units in the second switch network is 2 (K4/K5), so that the switching time of the radio frequency switch circuit can be obviously reduced.

The embodiment also provides a radio frequency front end module, which is characterized by comprising the radio frequency switch circuit in the embodiment.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A radio frequency switching circuit, comprising:

a switching cell sequence connected in series between a first terminal and a second terminal, the switching cell sequence comprising a first switching cell and a second switching cell, wherein a first end of the first switching cell is coupled to the first terminal, a second end of the first switching cell is connected to a first end of the second switching cell, and a second end of the second switching cell is coupled to the second terminal;

The accelerating circuit comprises a first accelerating path and a second accelerating path, a first bias output end is connected to a bias control end of a first switch unit, a bias control end of a second switch unit and a connection node of the first switch unit and the second switch unit through the first accelerating path and the second accelerating path, and bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first bias output end and the accelerating path so as to switch the states of the first switch unit and the second switch unit;

the first acceleration path comprises a first transistor, and the second acceleration path comprises a second transistor, wherein the first transistor and the second transistor are complementary transistors;

2. The radio frequency switching circuit of claim 1, further comprising, the sequence of switching cells further comprising a third switching cell, the second bias output connected to a bias control terminal of the third switching cell through a first gate resistor.

3. The radio frequency switching circuit according to claim 1, wherein,

when the bias control voltage is positive pressure, the first acceleration channel is conducted, the second acceleration channel is turned off, and the bias control voltage is loaded on bias control ends of the first switch unit and the second switch unit through the first acceleration channel so as to switch states of the first switch unit and the second switch unit;

4. The radio frequency switching circuit of claim 1, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, wherein a source of the first transistor is connected to a source of the second transistor and coupled to a bias control terminal of the first switching unit, a drain of the first transistor is connected to a drain of the second transistor and coupled to a bias control terminal of the second switching unit, and a gate of the first transistor and a gate of the second transistor are connected and coupled to a connection node of the first switching unit and the second switching unit.

5. The radio frequency switching circuit according to claim 4, wherein,

when the bias control voltage is positive voltage, the gate drain voltage of the first transistor is negative voltage, the gate drain voltage of the second transistor is negative voltage, the first transistor is turned on, the second transistor is turned off, and the bias control voltage is loaded on bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch states of the first switch unit and the second switch unit;

6. The radio frequency switching circuit of claim 1, wherein the first transistor is a PNP transistor and the second transistor is an NPN transistor, wherein an emitter of the first transistor is connected to an emitter of the second transistor and coupled to a bias control terminal of the first switching element, a collector of the first transistor is connected to a collector of the second transistor and coupled to a bias control terminal of the second switching element, and a base of the first transistor and a base of the second transistor are connected and coupled to a connection node of the first switching element and the second switching element.

7. The radio frequency switching circuit according to claim 6, wherein,

when the bias control voltage is positive, the base-emitter voltage of the first transistor is negative, the base-emitter voltage of the second transistor is negative, the first transistor is on, the second transistor is off, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch the states of the first switch unit and the second switch unit;

when the bias control voltage is negative, the base-emitter voltage of the first transistor is positive, the base-emitter voltage of the second transistor is positive, the first transistor is turned off, the second transistor is turned on, and the bias control voltage is loaded on the bias control ends of the first switch unit and the second switch unit through the first transistor so as to switch the states of the first switch unit and the second switch unit.

8. The radio frequency switching circuit according to claim 3, wherein the first switching unit comprises at least one first field effect transistor and the second switching unit comprises at least one second field effect transistor; the grid of the first switch unit is a bias control end of the first switch unit, the source of the first switch unit is a first end of the first switch unit, and the drain of the first switch unit is a second end of the first switch unit; the grid of the second switch unit is a bias control end of the second switch unit, the source electrode of the second switch unit is a first end of the second switch unit, and the drain electrode of the second switch unit is a second end of the first switch unit.

9. The radio frequency switching circuit according to claim 8, wherein,

when the field effect transistor is an NMOS tube, the first switch unit and the second switch unit are switched to an on state if the bias control voltage is positive, and the first switch unit and the second switch unit are switched to an off state if the bias control voltage is negative;

10. The radio frequency switching circuit of claim 1, further comprising a first isolation resistor, wherein the third terminal of the first transistor and the third terminal of the second transistor are coupled to a connection node of the first switching unit and the second switching unit through the first isolation resistor after being connected.

11. The radio frequency switching circuit according to claim 10, wherein the first isolation resistor has a resistance value of 10kΩ -100kΩ.

12. The radio frequency switching circuit of claim 1, further comprising at least one second isolation resistor, wherein the first bias output is coupled to the first and second acceleration paths through the second isolation resistor.

13. The radio frequency switching circuit according to claim 12, wherein the second isolation resistor has a resistance value of 5kΩ -25kΩ.

14. The radio frequency switching circuit according to claim 12, wherein a first bias output is connected to a first terminal of the first transistor and a first terminal of the second transistor, and/or wherein the first bias output is connected to a second terminal of the first transistor and a second terminal of the second transistor.

15. The radio frequency switching circuit according to claim 14, wherein the first bias output is connected to the first terminal of the first transistor and the first terminal of the second transistor through a second isolation resistor and/or to the second terminal of the first transistor and the second terminal of the second transistor through another second isolation resistor.

16. The radio frequency switching circuit of claim 1, wherein the first terminal is connected to a radio frequency input and the second terminal is connected to a radio frequency output, or wherein the first terminal is connected to a first node on a signal transmission link and the second terminal is connected to ground.

17. A radio frequency switching circuit, comprising:

A first gate resistor, a second bias output terminal connected to a bias control terminal of a switching unit in the second switching network through the first gate resistor to switch a state of the switching unit in the second switching network;

18. The radio frequency switching circuit of claim 17, wherein a number of switching units in the first switching network is greater than or equal to a number of switching units in the second switching network.

19. A radio frequency front end module comprising a radio frequency switching circuit as claimed in any one of claims 1 to 18.