CN115985771B - Preparation method of IGBT chip structure with composite function - Google Patents
Preparation method of IGBT chip structure with composite function Download PDFInfo
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- CN115985771B CN115985771B CN202310272160.0A CN202310272160A CN115985771B CN 115985771 B CN115985771 B CN 115985771B CN 202310272160 A CN202310272160 A CN 202310272160A CN 115985771 B CN115985771 B CN 115985771B
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Abstract
The invention provides a preparation method of an IGBT chip structure with a composite function, and relates to the field of semiconductor device manufacturing. Forming a groove in a semiconductor substrate, forming a separate gate polysilicon layer which is independently segmented in the groove, depositing and etching a metal layer on the separate gate polysilicon layer, and connecting the separate gate polysilicon layer with the metal layer to form a thermistor structure; that is, an independently segmented split gate polysilicon layer may be formed inside the trench and can be used as a built-in temperature sensor for the IGBT chip. Therefore, the invention solves the problems of low accuracy and poor sensitivity existing in the prior scheme of integrating the temperature sensor on the IGBT chip; meanwhile, the Miller capacitance in the IGBT chip can be reduced to a certain extent, so that the performance of the chip can be effectively improved, and the normal operation of the chip can be ensured.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a preparation method of an IGBT chip structure with a composite function.
Background
The insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a compound full-control voltage-driven power semiconductor device consisting of a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) and a bipolar junction transistor (Bipolar Junction Transistor, BJT), and integrates the advantages of simple gate voltage driving of the MOSFET and low on-resistance of the BJT; the IGBT has been widely used in the fields of communication, traffic, home appliances, industry, new energy, and the like by virtue of its advantages of high blocking voltage, large current capacity, small driving power, and the like. In order to ensure that the IGBT chip can work normally, it is necessary to integrate a temperature sensor on the chip to monitor the temperature of the IGBT chip in real time, thereby preventing the occurrence of chip damage or shortened life due to excessive temperature.
Currently, there are two main ways to integrate a temperature sensor on an IGBT chip: firstly, the temperature sensor (such as a thermistor) and the IGBT chip are packaged together, in this way, a certain distance is needed between the temperature sensor and the IGBT chip, so that the heat of the IGBT chip can only be partially conducted to the temperature sensor, the response speed of temperature detection is slower, and certain hysteresis is provided, thereby the accuracy of temperature monitoring is lower; secondly, a temperature sensor is built in the IGBT chip, and the specific implementation method is that a polycrystalline silicon layer of the temperature sensor is generally arranged above grid polycrystalline silicon, however, the sensitivity of the temperature sensor prepared by the method is poor in practical use, and the contact hole shape of the polycrystalline silicon layer is poor due to the step height difference between the polycrystalline silicon layer of the temperature sensor and the grid polycrystalline silicon, so that the temperature sensor can only measure the temperature of the surface of the IGBT chip.
In addition, the Miller capacitance also exists in the IGBT chip, and the Miller effect can enable the chip to form a platform voltage in the grid driving process, so that the problems of long switching time, increased switching loss and the like are caused, and negative influence is brought to the normal operation of the IGBT chip; therefore, how to reduce the miller capacitance in the chip as much as possible is also a worthy of research and discussion.
Disclosure of Invention
The invention aims to provide a preparation method of an IGBT chip structure with a composite function, which solves the problems of low accuracy and poor sensitivity in the prior scheme of integrating a temperature sensor on an IGBT chip; meanwhile, the invention can reduce the Miller capacitance in the IGBT chip to a certain extent, thereby effectively improving the performance of the chip and ensuring the normal operation of the chip.
The invention is realized by adopting the following technical scheme:
a preparation method of IGBT chip structure with composite function comprises forming a trench in a semiconductor substrate, forming a separate gate polysilicon layer in the trench, depositing and etching a metal layer on the separate gate polysilicon layer to connect the separate gate polysilicon layer with the metal layer.
On the basis of the IGBT separation gate preparation principle, the method forms a separation gate polysilicon layer which is independently segmented in the groove and is used as a built-in temperature sensor of an IGBT chip. Compared with a conventional integration scheme, the method has the advantages that no space exists between the IGBT chip and the temperature sensor, so that the one-sided performance and the hysteresis of temperature monitoring are avoided; the polysilicon layer of the temperature sensor is not required to be arranged above the grid polysilicon, so that the situation that the polysilicon layer of the temperature sensor (namely the separated grid polysilicon layer) is isolated from the semiconductor substrate by the grid polysilicon layer is avoided, namely the detection precision of the temperature sensor is improved, and the monitoring of the temperature sensor is not easily influenced by the external environment of the chip; therefore, the method and the device can effectively improve the position accuracy and the numerical accuracy of temperature monitoring in the IGBT chip, thereby ensuring the normal operation of the IGBT chip. Meanwhile, the separated gate polysilicon layer is connected with the ultrathin metal layer to form a thermistor structure, the temperature of the IGBT chip can be reflected through the resistance characteristic of the separated gate polysilicon layer, and the transmission efficiency of charges in the gate source oxide layer can be greatly improved due to the existence of the metal layer, so that the Miller capacitance in the chip can be reduced to the greatest extent, and the performance of the IGBT chip is effectively improved.
Further, the method comprises the steps of 1, forming a groove in the semiconductor substrate, forming a first oxide layer in the groove and on the upper surface of the semiconductor substrate, and depositing a first polysilicon layer in the groove and on the upper surface of the first oxide layer. In the step, the specific positions for forming the grooves can be flexibly selected according to actual requirements in the preparation process, namely, the grooves can be arranged in different positions of the IGBT chips, a plurality of grooves can be formed on one IGBT chip, and a plurality of temperature sensors are formed on the basis, so that the comprehensiveness and the accuracy of temperature monitoring are realized. It should be noted that the shape of the groove in the method is not limited to a bar shape, and may be other shapes such as square, regular hexagon, etc.; meanwhile, the material is not limited to silicon materials, and can be applied to semiconductor materials such as silicon carbide and gallium nitride.
Further, step 2 is performed on the basis of step 1, a pattern of the first polysilicon layer is defined, the first polysilicon layer is etched to enable the first oxide layer to leak out, and the first polysilicon layer is reserved in the groove for a certain length to form the split gate polysilicon layer.
Further, step 3 is performed on the basis of step 2, and an ultra-thin metal layer is deposited in the trench and on the upper surface of the first oxide layer.
Further, step 4 is performed on the basis of step 3, a pattern of the metal layer is defined, and the metal layer is etched so that the bottom of the metal layer is in contact with the split gate polysilicon layer.
Further, step 5 is performed on the basis of step 4, a second oxide layer is formed in the trench and on the upper surface of the first oxide layer, and a second polysilicon layer is deposited in the trench and on the upper surface of the second oxide layer.
Further, step 6 is performed on the basis of step 5, and the second polysilicon layer is etched and etched back to be flush with the upper surface of the second oxide layer, so as to form a polysilicon gate. The process flow is the same as the conventional IGBT separation gate manufacturing process, and does not belong to the improvement point of the invention, so that the description is omitted.
Further, the first oxide layer is made of silicon dioxide, and is formed through a thermal oxidation process or a chemical vapor deposition process.
Further, in the step 2, a pattern of the first polysilicon layer is defined by using photoresist, and the first polysilicon layer is etched by using an anisotropic dry etching process.
Further, in the step 4, the pattern of the metal layer is defined by using photoresist, and the metal layer is etched by adopting two oblique directional etching processes.
The beneficial effects achieved by the invention are as follows:
a preparation method of IGBT chip structure with composite function, regard separate gate polycrystalline silicon layer of the independent section in the ditch groove as the built-in temperature sensor of IGBT chip, wherein make separate gate polycrystalline silicon layer connect with metal layer, make up the thermistor structure. Compared with the conventional integration scheme, the method can avoid one-sided performance and hysteresis of temperature monitoring, improves the detection precision of the temperature sensor, and ensures that the monitoring of the temperature sensor is not easily influenced by the external environment of the chip; therefore, the position accuracy and the numerical accuracy of temperature monitoring in the IGBT chip can be effectively improved, so that the working stability and the reliability of the IGBT chip are ensured, and great convenience is provided for the application and failure analysis of the IGBT chip. In addition, the existence of the metal layer can reduce the Miller capacitance in the chip to the greatest extent, so that the performance of the IGBT chip is effectively improved.
Drawings
FIG. 1 is a schematic cross-sectional view of the step 1 according to the embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of the step 2 according to the embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of the step 3 according to the embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure formed during and after the step 4 in the embodiment of the present invention, where (a) is a schematic cross-sectional structure during the first diagonal directional etching process, (b) is a schematic cross-sectional structure after the first diagonal directional etching process, (c) is a schematic cross-sectional structure during the second diagonal directional etching process, and (d) is a schematic cross-sectional structure after the second diagonal directional etching process;
FIG. 5 is a schematic cross-sectional view of the embodiment of the present invention after the step 5 is performed;
FIG. 6 is a schematic cross-sectional view of the embodiment of the present invention after the step 6 is performed;
fig. 7 is a schematic diagram of a position distribution of a structure of a built-in temperature sensor on an IGBT chip according to an embodiment of the invention;
in the figure: 1. a substrate; 2. a groove; 3. a first oxide layer; 4. a first polysilicon layer; 5. a split gate polysilicon layer; 6. a metal layer; 7. a second oxide layer; 8. a second polysilicon layer; 9. a polysilicon gate.
Detailed Description
For clarity of explanation of the solution of the present invention, the following will be further explained with reference to the accompanying drawings:
referring to fig. 1 to 7, a method for fabricating an IGBT chip structure with a complex function includes forming a trench 2 in a semiconductor substrate 1, forming a separate gate polysilicon layer 5 in the trench 2, and depositing and etching an ultra-thin metal layer 6 on the separate gate polysilicon layer 5 to connect the separate gate polysilicon layer 5 with the metal layer 6 to form a thermistor structure. Specifically, the method comprises the following steps:
step 1: as shown in fig. 1, a stripe-shaped trench 2 is formed in a semiconductor substrate 1, a first oxide layer 3 is formed at the bottom, side walls, and upper surface of the trench 2 and a first polysilicon layer 4 is deposited in the trench 2 and on the upper surface of the first oxide layer 3; the material of the first oxide layer 3 is silicon dioxide, and is formed by a thermal oxidation process or a chemical vapor deposition process.
Step 2: as shown in fig. 2, a pattern of the first polysilicon layer 4 is defined by using photoresist, and then the first polysilicon layer 4 is etched by using an anisotropic dry etching process, so that the first oxide layer 3 leaks out, and the first polysilicon layer 4 is kept within the trench 2 for a certain length, so as to form a split gate polysilicon layer 5.
Step 3: as shown in fig. 3, an ultra-thin metal layer 6 is deposited into the trench 2 and onto the upper surface of the first oxide layer 3.
Step 4: as shown in fig. 4, a pattern of the metal layer 6 is defined by using photoresist, and then the redundant metal layer 6 on the upper surface of the first oxide layer 3, the side wall of the trench 2 and the surface of the split gate polysilicon layer 5 is etched by adopting a twice oblique directional etching process; the operation process of performing the first oblique directional etching process and the structure obtained after the process are shown in fig. 4 (a) and fig. 4 (b), and the operation process of performing the second oblique directional etching process and the structure obtained after the process are shown in fig. 4 (c) and fig. 4 (d), respectively.
Step 5: as shown in fig. 5, a second oxide layer 7 is formed in the trench 2 and on the upper surface of the first oxide layer 3 by a thermal oxidation process or a chemical vapor deposition process, and then a second polysilicon layer 8 is deposited in the trench 2 and on the upper surface of the second oxide layer 7.
Step 6: as shown in fig. 6, the excess portion of the second polysilicon layer 8 is etched away by an etching process and dry etched back to a level position on the upper surface of the second oxide layer 7, thereby forming a polysilicon gate 9. The process flow is the same as the conventional IGBT separation gate manufacturing process, and will not be repeated.
As shown in fig. 7, the plurality of trenches 2 can be uniformly distributed in the IGBT chip, on the basis of which a plurality of temperature sensor structures can be formed inside the IGBT chip. Thus, by the method described in the present embodiment, the separate gate polysilicon layer 5 of independent segments can be formed inside the trench 2 and can be used as a built-in temperature sensor structure of the IGBT chip.
Compared with a conventional integration scheme, the method has the advantages that no space exists between the IGBT chip and the temperature sensor, so that the one-sided performance and the hysteresis of temperature monitoring are avoided; the polysilicon layer of the temperature sensor is not required to be arranged above the grid polysilicon, so that the situation that the polysilicon layer of the temperature sensor (namely the separation grid polysilicon layer 5) is isolated from the semiconductor substrate 1 by the grid polysilicon layer is avoided, namely the detection precision of the temperature sensor is improved, and the monitoring of the temperature sensor is not easily influenced by the external environment of the chip; therefore, the method and the device can effectively improve the position accuracy and the numerical accuracy of temperature monitoring in the IGBT chip, thereby ensuring the normal operation of the IGBT chip. Meanwhile, the existence of the metal layer 6 can also greatly improve the transmission efficiency of charges in the gate-source oxide layer, so that the Miller capacitance in the chip can be reduced to the greatest extent, and the performance of the IGBT chip is effectively improved.
Of course, the foregoing is merely preferred embodiments of the present invention and is not to be construed as limiting the scope of the embodiments of the present invention. The present invention is not limited to the above examples, and those skilled in the art will appreciate that the present invention is capable of equally varying and improving within the spirit and scope of the present invention.
Claims (4)
1. A preparation method of an IGBT chip structure with a composite function is characterized by comprising the following steps: forming a groove (2) in a semiconductor substrate (1), forming a separate gate polysilicon layer (5) in the groove (2), depositing and etching a metal layer (6) on the separate gate polysilicon layer (5), and connecting the separate gate polysilicon layer (5) with the metal layer (6);
the method specifically comprises the following steps:
step 1, forming a groove (2) in a semiconductor substrate (1), forming a first oxide layer (3) in the groove (2) and on the upper surface of the semiconductor substrate (1), and depositing a first polysilicon layer (4) in the groove (2) and on the upper surface of the first oxide layer (3);
step 2 is executed on the basis of the step 1, a graph of a first polycrystalline silicon layer (4) is defined, the first polycrystalline silicon layer (4) is etched, the first oxide layer (3) leaks out, and the first polycrystalline silicon layer (4) is reserved for a certain length in the first polycrystalline silicon layer (4) in the groove (2) so as to form a separation gate polycrystalline silicon layer (5);
step 3 is carried out on the basis of the step 2, and an ultrathin metal layer (6) is deposited in the groove (2) and on the upper surface of the first oxide layer (3);
step 4 is executed on the basis of the step 3, a pattern of the metal layer (6) is defined, and the metal layer (6) is etched, so that the bottom of the metal layer (6) is contacted with the separation gate polysilicon layer (5);
step 5 is carried out on the basis of the step 4, a second oxide layer (7) is formed in the groove (2) and on the upper surface of the first oxide layer (3), and a second polysilicon layer (8) is deposited in the groove (2) and on the upper surface of the second oxide layer (7);
and (3) executing a step 6 on the basis of the step 5, etching the second polycrystalline silicon layer (8) and etching the second polycrystalline silicon layer back to be flush with the upper surface of the second oxide layer (7) so as to form a polycrystalline silicon grid electrode (9).
2. The method for manufacturing the IGBT chip structure with composite functions according to claim 1, characterized in that: the first oxide layer (3) is made of silicon dioxide and is formed through a thermal oxidation process or a chemical vapor deposition process.
3. The method for manufacturing the IGBT chip structure with composite functions according to claim 1, characterized in that: in the step 2, a pattern of the first polysilicon layer (4) is defined by using photoresist, and the first polysilicon layer (4) is etched by using an anisotropic dry etching process.
4. The method for manufacturing the IGBT chip structure with composite functions according to claim 1, characterized in that: in the step 4, a pattern of the metal layer (6) is defined by using photoresist, and the metal layer (6) is etched by adopting a twice oblique directional etching process.
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| WO2009141336A2 (en) * | 2008-05-19 | 2009-11-26 | X-Fab Semiconductor Foundries Ag | Method for controlling the operating temperature of a semiconductor power component, and component for carrying out said method |
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| US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| US8907418B2 (en) * | 2013-05-07 | 2014-12-09 | Infineon Technologies Austria Ag | Semiconductor device |
| US9450082B2 (en) * | 2014-06-09 | 2016-09-20 | Texas Instruments Incorporated | Integrated termination for multiple trench field plate |
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| US11251297B2 (en) * | 2018-03-01 | 2022-02-15 | Ipower Semiconductor | Shielded gate trench MOSFET devices |
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| CN114122112A (en) * | 2022-01-26 | 2022-03-01 | 深圳尚阳通科技有限公司 | Groove type power device and manufacturing method thereof |
| CN114496995B (en) * | 2022-04-18 | 2022-06-17 | 深圳市威兆半导体有限公司 | Shielding gate device with temperature sampling function |
| CN114783999B (en) * | 2022-06-20 | 2022-09-30 | 深圳芯能半导体技术有限公司 | IGBT device with built-in temperature sensor and preparation method thereof |
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| WO2009141336A2 (en) * | 2008-05-19 | 2009-11-26 | X-Fab Semiconductor Foundries Ag | Method for controlling the operating temperature of a semiconductor power component, and component for carrying out said method |
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