CN115985222B - Frequency control circuit, source driver, frequency control method and display panel - Google Patents
Frequency control circuit, source driver, frequency control method and display panel Download PDFInfo
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- CN115985222B CN115985222B CN202310273705.XA CN202310273705A CN115985222B CN 115985222 B CN115985222 B CN 115985222B CN 202310273705 A CN202310273705 A CN 202310273705A CN 115985222 B CN115985222 B CN 115985222B
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Abstract
The utility model relates to a frequency control circuit, source driver, frequency control method and display panel, this frequency control circuit is applied to source driver, source driver includes clock recovery circuit and frequency discrimination circuit, clock recovery circuit includes phase detector that connects gradually electrically, charge pump and voltage-controlled oscillator, the first input of frequency discrimination circuit and phase detector's input electric connection, frequency discrimination circuit's second input and voltage-controlled oscillator's output electric connection, frequency control circuit's control end is used for with frequency discrimination circuit's output electric connection, frequency control circuit's input is used for with charge pump's output electric connection, frequency control circuit's output is used for with voltage-controlled oscillator electric connection, the noise influence in the input data signal has been reduced to above-mentioned frequency control circuit, and then make every source driver carry out the accuracy of analysis to the input data signal greatly improved, also make every source driver's efficiency tend to be consistent simultaneously.
Description
Technical Field
The present disclosure relates to the field of display, and in particular, to a frequency control circuit, a source driver, a frequency control method, and a display panel.
Background
In conventional display panel driving, it is common that a source driver receives timing control (Timing Controller, TCON) data transmitted from a timing controller, parses the data through an internal clock recovery circuit, and outputs a driving voltage to a TFT display panel.
When each source driver receives the timing control data to analyze, the accuracy of each source driver in analyzing the data is affected because the timing control data may contain noise.
Disclosure of Invention
In view of the above, the present application provides a frequency control circuit, a source driver, a frequency control method, and a display panel, which can improve accuracy of the source driver in analyzing data.
The utility model provides a frequency control circuit, be applied to the source driver, the source driver includes clock recovery circuit and frequency discrimination circuit, clock recovery circuit includes phase detector, charge pump and the voltage-controlled oscillator of electric connection in proper order, frequency discrimination circuit's first input and phase detector's input electric connection, frequency discrimination circuit's second input and voltage-controlled oscillator's output electric connection, frequency control circuit's control end is used for with frequency discrimination circuit's output electric connection, frequency control circuit's input is used for with the output electric connection of charge pump, frequency control circuit's output is used for with voltage-controlled oscillator electric connection.
The phase detector is used for receiving the input data signal, detecting the phase difference between the input data signal and the clock signal and sending the phase difference to the charge pump.
The charge pump is used for outputting corresponding voltage control signals to the frequency control circuit and the voltage-controlled oscillator according to the phase difference.
The frequency control circuit is used for receiving a first preset level signal sent by the frequency discrimination circuit, controlling the frequency control circuit to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator.
The voltage-controlled oscillator is used for adjusting the output of the voltage-controlled oscillator according to the voltage adjustment control signal so as to output an adjusted clock frequency signal and sending the adjusted clock frequency signal to the second input end of the frequency discrimination circuit.
The frequency discrimination circuit is used for comparing whether the input data signal is consistent with the clock frequency signal or not so as to perform frequency locking, and when the input data signal is consistent with the clock frequency signal, a second preset level signal is generated and sent to the frequency control circuit;
the frequency control circuit is used for controlling the frequency control circuit to be in a stop working state according to the second preset level signal.
In one embodiment, the voltage regulation control signal includes a first regulation control signal, the frequency control circuit includes a voltage comparing unit and an adjusting judging unit that are electrically connected, an input end of the voltage comparing unit is electrically connected with an output end of the charge pump, a control end of the comparing unit is electrically connected with an output end of the frequency discriminating circuit, an output end of the adjusting judging unit is electrically connected with the voltage-controlled oscillator, an input-output curve of the voltage-controlled oscillator includes a first input-output curve and a second input-output curve, and an output value of the first input-output curve corresponding to the same voltage control signal is smaller than an output value of the second input-output curve.
The voltage comparison unit is used for comparing the voltage control signal with a first preset voltage threshold value and a second preset voltage threshold value respectively, wherein the first preset voltage threshold value is larger than the second preset voltage threshold value.
After the source driver is started, the input-output curve of the voltage-controlled oscillator changes according to the first input-output curve.
When the voltage control signal is smaller than or equal to a first preset voltage threshold, the voltage-controlled oscillator is used for outputting a first clock frequency signal in a first preset bandwidth area according to the voltage control signal, and the first preset bandwidth area corresponds to the first input-output curve.
The frequency discrimination circuit is used for comparing whether the frequencies of the first clock frequency signal and the input data signal are consistent or not so as to discriminate the frequency.
When the voltage control signal is greater than a first preset voltage threshold, the frequency control circuit is further configured to generate a first adjustment control signal to the voltage-controlled oscillator.
The voltage-controlled oscillator is used for outputting a second clock frequency signal in a second preset bandwidth area according to the first adjusting control signal and the voltage control signal so that an input-output curve of the voltage-controlled oscillator changes according to the second input-output curve, and the second preset bandwidth area corresponds to the second input-output curve.
The frequency discrimination circuit is also used for comparing whether the frequencies of the second clock frequency signal and the input data signal are consistent or not so as to carry out frequency discrimination.
In one embodiment, the voltage regulation control signal further comprises a second regulation control signal.
After the input-output curve of the voltage-controlled oscillator jumps from the first input-output curve to the second input-output curve, when the voltage control signal is greater than or equal to a second preset voltage threshold value, the input-output curve of the voltage-controlled oscillator always changes according to the second input-output curve.
When the voltage control signal is smaller than a second preset voltage threshold, the frequency control circuit is further used for generating a corresponding second adjusting control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is used for outputting a first clock frequency signal in a first preset bandwidth area according to the second adjusting control signal and the voltage control signal so that an input-output curve of the voltage-controlled oscillator changes according to the first input-output curve.
The frequency discrimination circuit is also used for comparing whether the frequencies of the corresponding first clock frequency signal and the input data signal are consistent or not so as to discriminate the frequency.
In one embodiment, after the input/output curve of the voltage controlled oscillator changes from the second input/output curve to the first input/output curve, when the voltage control signal is less than or equal to the first preset voltage threshold, the input/output curve of the voltage controlled oscillator always changes according to the first input/output curve.
In one embodiment, the voltage-controlled oscillator includes a voltage-to-current unit and a current-controlled oscillator that are electrically connected, wherein a first input terminal of the voltage-to-current unit is electrically connected to an output terminal of the charge pump, and a second input terminal of the voltage-to-current unit is electrically connected to an output terminal of the adjustment determination unit.
The voltage-to-current unit is used for converting the voltage control signal into a corresponding current control signal.
The current control oscillator is used for converting the current control signal into a corresponding clock frequency signal.
The voltage-to-current unit is also used for receiving the voltage regulation control signal sent by the regulation judging unit and regulating the magnitude of the current control signal according to the voltage regulation control signal.
In one embodiment, the voltage comparing unit includes a first comparator and a second comparator, wherein the control ends of the first comparator and the second comparator are electrically connected with the output end of the frequency discrimination circuit, the first comparator is used for comparing the voltage control signal with a first preset voltage threshold value, and the second comparator is used for comparing the voltage control signal with a second preset voltage threshold value.
In one embodiment, the adjusting and judging unit includes an inverter, a first nand gate and a second nand gate, wherein an input end of the inverter is electrically connected with an output end of the second comparator, an output end of the inverter is electrically connected with a first input end of the first nand gate, a second input end of the first nand gate is electrically connected with an output end of the second nand gate, an output end of the first nand gate is electrically connected with a first input end of the second nand gate, and a second input end of the second nand gate is electrically connected with an output end of the first comparator.
In addition, a source driver is provided, which includes the frequency control circuit.
In addition, a frequency control method is provided, the frequency control method is applied to the source driver, and the frequency control method comprises the following steps:
receiving a first preset level signal sent by a frequency discrimination circuit;
receiving a voltage control signal sent by a charge pump;
controlling the voltage-controlled oscillator to be in a working state according to a first preset level signal, generating a voltage regulation control signal according to a voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator so that the voltage-controlled oscillator regulates the output of the voltage-controlled oscillator according to the voltage regulation control signal to output a regulated clock frequency signal;
receiving a second preset level signal sent by the frequency discrimination circuit;
and controlling the self to be in a stop working state according to the second preset level signal.
In addition, a display panel is provided, and the display panel comprises the source driver.
The frequency control circuit is applied to a source driver, the source driver comprises a clock recovery circuit and a frequency discrimination circuit, the clock recovery circuit comprises a phase detector, a charge pump and a voltage-controlled oscillator which are electrically connected in sequence, a first input end of the frequency discrimination circuit is electrically connected with an input end of the phase detector, a second input end of the frequency discrimination circuit is electrically connected with an output end of the voltage-controlled oscillator, a control end of the frequency control circuit is electrically connected with an output end of the frequency discrimination circuit, an input end of the frequency control circuit is electrically connected with an output end of the charge pump, an output end of the frequency control circuit is electrically connected with the voltage-controlled oscillator, the phase detector is used for receiving an input data signal, detecting a phase difference between the input data signal and the clock signal and sending the phase difference to the charge pump, the charge pump is used for outputting a corresponding voltage control signal to the frequency control circuit and the voltage-controlled oscillator according to the phase difference, the frequency control circuit is used for receiving a first preset level signal sent by the frequency discrimination circuit, controlling the frequency discrimination circuit to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator, the voltage-controlled oscillator is used for regulating the output of the frequency discrimination circuit according to the voltage regulation control signal so as to output a regulated clock frequency signal, and sending the regulated clock frequency signal to a second input end of the frequency discrimination circuit, the frequency discrimination circuit is used for comparing whether an input data signal is consistent with the clock frequency signal so as to carry out frequency locking, when the input data signal is consistent with the clock frequency signal, the second preset level signal is generated and sent to the frequency control circuit so as to stop the working of the frequency control circuit, the output of the voltage-controlled oscillator can be regulated by setting the frequency control circuit, the voltage-controlled oscillator outputs the regulated clock frequency signal, so that the frequency discrimination circuit finishes frequency locking, the noise influence in the input data signal is reduced, the accuracy of analyzing the input data signal by each source driver is greatly improved, and the efficiency of each source driver tends to be consistent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a frequency control circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a variation of an input-output curve of a voltage-controlled oscillator according to an embodiment of the present disclosure;
fig. 3 is a block diagram of a voltage-controlled oscillator according to an embodiment of the present application;
fig. 4 is a schematic circuit diagram of an adjustment determining unit according to an embodiment of the present application;
fig. 5 is a flow chart of a frequency control method according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. Based on the examples in the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
As shown in fig. 1, a frequency control circuit 100 is provided, the frequency control circuit 100 is applied to a source driver 10, the source driver 10 includes a clock recovery circuit 110 and a frequency discrimination circuit 120, the clock recovery circuit 110 includes a phase detector 111, a charge pump 112 and a voltage-controlled oscillator 113 electrically connected in sequence, a first input terminal of the frequency discrimination circuit 120 is electrically connected with an input terminal of the phase detector 111, a second input terminal of the frequency discrimination circuit 120 is electrically connected with an output terminal of the voltage-controlled oscillator, a control terminal of the frequency control circuit 100 is electrically connected with an output terminal of the frequency discrimination circuit 120, an input terminal of the frequency control circuit 100 is electrically connected with an output terminal of the charge pump 112, and an output terminal of the frequency control circuit 100 is electrically connected with the voltage-controlled oscillator.
The phase detector 111 is configured to receive the input data signal, detect a phase difference between the input data signal and the clock signal, and send the detected phase difference to the charge pump 112.
The charge pump 112 is configured to output a corresponding voltage control signal to the frequency control circuit 100 and the voltage controlled oscillator 113 according to the phase difference.
The frequency control circuit 100 is configured to receive a first preset level signal sent by the frequency discrimination circuit 120, control itself to be in a working state according to the first preset level signal, generate a voltage regulation control signal according to the voltage control signal, and send the voltage regulation control signal to the voltage-controlled oscillator 113.
The voltage-controlled oscillator 113 is configured to adjust its output according to the voltage adjustment control signal, so as to output an adjusted clock frequency signal, and send the adjusted clock frequency signal to the second input terminal of the frequency discriminator 120.
The frequency discrimination circuit 120 is configured to compare whether the input data signal is consistent with the clock frequency signal to perform frequency locking, and when the input data signal is consistent with the clock frequency signal, generate a second preset level signal and send the second preset level signal to the frequency control circuit 100, where the frequency control circuit 100 controls itself to be in a stop working state according to the second preset level signal.
In this embodiment, by setting the frequency control circuit 100, the output of the voltage-controlled oscillator 113 can be adjusted, so that the voltage-controlled oscillator 113 outputs an adjusted clock frequency signal, so that the frequency discriminator 120 completes frequency locking, the noise influence in the input data signal is reduced, the accuracy of analyzing the input data signal by each source driver 10 is greatly improved, and the efficiency of each source driver 10 tends to be consistent.
In one embodiment, the voltage adjustment control signal includes a first adjustment control signal, as shown in fig. 1, the frequency control circuit 100 includes a voltage comparing unit 130 and an adjustment judging unit 140 that are electrically connected, an input end of the voltage comparing unit 130 is electrically connected to an output end of the charge pump 112, a control end of the comparing unit is electrically connected to an output end of the frequency discriminating circuit 120, and an output end of the adjustment judging unit 140 is electrically connected to the voltage-controlled oscillator 113.
The input/output curves of the voltage-controlled oscillator 113 include a first input/output curve and a second input/output curve, and the output value of the first input/output curve corresponding to the same voltage control signal is smaller than the output value of the second input/output curve.
The voltage comparing unit 130 is configured to compare the voltage control signal with a first preset voltage threshold and a second preset voltage threshold, where the first preset voltage threshold is greater than the second preset voltage threshold.
After the source driver 10 is started, the input-output curve of the voltage-controlled oscillator 113 changes according to the first input-output curve.
When the voltage control signal is less than or equal to the first preset voltage threshold, the voltage-controlled oscillator 113 is configured to output a first clock frequency signal in a first preset bandwidth area according to the voltage control signal, where the first preset bandwidth area corresponds to the first input-output curve.
The frequency discrimination circuit 120 is used for comparing whether the frequencies of the first clock frequency signal and the input data signal are consistent for frequency discrimination.
When the voltage control signal is greater than the first preset voltage threshold, the frequency control circuit 100 is further configured to generate a first adjustment control signal to the voltage-controlled oscillator 113.
The voltage-controlled oscillator 113 is configured to output a second clock frequency signal in a second preset bandwidth area according to the first adjustment control signal and the voltage control signal, so that an input-output curve of the voltage-controlled oscillator 113 changes according to the second input-output curve, and the second preset bandwidth area corresponds to the second input-output curve.
The frequency discrimination circuit 120 is further configured to compare whether frequencies of the second clock frequency signal and the input data signal coincide for frequency discrimination.
As shown in fig. 2, the abscissa Vin is an input signal (i.e., a voltage control signal) of the voltage-controlled oscillator 113, the unit is volts, the ordinate f is an output value (unit is Hz) of the voltage-controlled oscillator 113, V1 is a first preset voltage threshold, V2 is a second preset voltage threshold, V2 is smaller than V1, the curve B1 is a first input-output curve of the voltage-controlled oscillator, the curve B2 is a second input-output curve of the voltage-controlled oscillator, the curve B1 corresponds to a low-frequency output curve (corresponding to a first preset bandwidth region) of the voltage-controlled oscillator, and the curve B2 corresponds to a high-frequency output curve (corresponding to a second preset bandwidth region) of the voltage-controlled oscillator.
In one embodiment, the first predetermined bandwidth region corresponds to a low frequency output region of the voltage controlled oscillator 113, and the second predetermined bandwidth region corresponds to a high frequency output region of the voltage controlled oscillator 113.
After the source driver 10 is turned on, the input data signal is generally searched from a low frequency, and frequency discrimination is performed by the frequency discrimination circuit 120, that is, the input/output curve of the voltage controlled oscillator 113 changes according to the curve B1 in fig. 2, and the output of the voltage controlled oscillator 113 changes in the inner area near both sides of the curve B1.
When the voltage control signal is greater than the first preset voltage threshold V1, the frequency control circuit 100 generates a first adjustment control signal to the voltage-controlled oscillator 113, and the voltage-controlled oscillator 113 is configured to output a second clock frequency signal in a second preset bandwidth area according to the first adjustment control signal and the voltage control signal, so that the input/output curve of the voltage-controlled oscillator 113 changes according to the second input/output curve, and the second preset bandwidth area corresponds to the second input/output curve, at this time, the input/output curve of the voltage-controlled oscillator 113 changes from the curve B1 to the curve B2, which is equivalent to optimizing the output performance of the first input/output curve of the voltage-controlled oscillator 113 when the voltage control signal is greater than the first preset voltage threshold V1, reducing the noise influence in the input data signal, and further greatly improving the accuracy of analyzing the input data signal by each source driver 10, and meanwhile, making the performance of each source driver 10 tend to be consistent.
In one embodiment, the voltage regulation control signal further comprises a second regulation control signal.
As shown in fig. 2, that is, the input/output curve of the voltage-controlled oscillator 113 changes according to the curve B2 in fig. 2, the output of the voltage-controlled oscillator 113 changes in an internal area near two sides of the curve B2, when the voltage control signal is smaller than the second preset voltage threshold V2, the frequency control circuit 100 is further configured to generate a corresponding second adjustment control signal to the voltage-controlled oscillator 113, and the voltage-controlled oscillator 113 is configured to output a second clock frequency signal in a second preset bandwidth area according to the second adjustment control signal, at this time, the output of the voltage-controlled oscillator 113 changes from the curve B2 to the curve B1, and outputting the second clock frequency signal corresponding to the voltage control signal in the curve B1 is equivalent to optimizing the output performance of the second input/output curve of the voltage-controlled oscillator 113 when the voltage control signal is smaller than the second preset voltage threshold V2, so that the noise influence in the input data signal is reduced, and the accuracy of each source driver 10 in analyzing the input data signal is greatly improved, and the efficiency of each source driver 10 tends to be consistent.
In one embodiment, the voltage regulation control signal further comprises a second regulation control signal.
After the input/output curve of the voltage-controlled oscillator 113 jumps from the first input/output curve to the second input/output curve, when the voltage control signal is greater than or equal to the second preset voltage threshold, the input/output curve of the voltage-controlled oscillator 113 always changes according to the second input/output curve.
When the voltage control signal is smaller than the second preset voltage threshold, the frequency control circuit 100 is further configured to generate a corresponding second adjustment control signal to the voltage-controlled oscillator 113.
The voltage-controlled oscillator 113 is configured to output a first clock frequency signal in a first preset bandwidth area according to the second adjustment control signal and the voltage control signal, so that an input-output curve of the voltage-controlled oscillator 113 changes according to the first input-output curve.
The frequency discrimination circuit 120 is further configured to compare whether frequencies of the corresponding first clock frequency signal and the input data signal are identical to each other for frequency discrimination.
In this embodiment, after the input/output curve of the voltage controlled oscillator 113 jumps from the first input/output curve to the second input/output curve, when the voltage control signal is greater than or equal to the second preset voltage threshold, the input/output curve of the voltage controlled oscillator 113 always changes according to the second input/output curve, the output of the voltage controlled oscillator 113 changes in the internal area near two sides of the curve B2, when the voltage control signal is smaller than the second preset voltage threshold V2, the frequency control circuit 100 is further configured to generate a corresponding second adjustment control signal to the voltage controlled oscillator 113, and the voltage controlled oscillator 113 is configured to output a first clock frequency signal in the first preset bandwidth area according to the second adjustment control signal and the voltage control signal so that the input/output curve of the voltage controlled oscillator 113 changes according to the first input/output curve, at this time, the input/output curve of the voltage controlled oscillator 113 jumps from the curve B2 to the curve B1, which is equivalent to optimizing the output performance of the second input/output curve of the voltage controlled oscillator 113 when the voltage control signal is smaller than the second preset voltage threshold V2, reducing the noise influence in the input data signal, and further driving the accuracy of each source 10 is greatly improved, and the source driver efficiency is greatly improved.
In one embodiment, after the input/output curve of the voltage controlled oscillator 113 changes from the second input/output curve to the first input/output curve, when the voltage control signal is less than or equal to the first preset voltage threshold, the input/output curve of the voltage controlled oscillator 113 always changes according to the first input/output curve. In one embodiment, as shown in fig. 3, the voltage-controlled oscillator 113 includes a voltage-to-current unit 114 and a current-controlled oscillator 115 that are electrically connected, wherein a first input terminal of the voltage-to-current unit 114 is electrically connected to an output terminal of the charge pump 112, and a second input terminal of the voltage-to-current unit 114 is electrically connected to an output terminal of the adjustment determination unit 140.
The voltage-to-current unit 114 is used for converting the voltage control signal into a corresponding current control signal.
The current controlled oscillator 115 is used to convert the current control signal into a corresponding clock frequency signal.
The voltage-to-current unit 114 is further configured to receive the voltage adjustment control signal sent by the adjustment determining unit 140, and adjust the magnitude of the current control signal according to the voltage adjustment control signal.
The second input end of the voltage-to-current unit 114 is electrically connected to the output end of the adjustment judging unit 140, and the voltage control signal sent by the adjustment judging unit 140 is received to control the voltage control signal to be converted into the corresponding current control signal, so that the overall output of the voltage-controlled oscillator 113 is adjusted.
In one embodiment, the voltage comparing unit 130 includes a first comparator a and a second comparator B, wherein the control ends of the first comparator a and the second comparator B are electrically connected to the output end of the frequency discriminator 120, the first comparator a is used for comparing the voltage control signal with a first preset voltage threshold, and the second comparator B is used for comparing the voltage control signal with a second preset voltage threshold.
In one embodiment, as shown in fig. 4, the adjustment determining unit 140 includes an inverter 141, a first nand gate C and a second nand gate D, wherein an input end of the inverter 141 is electrically connected to an output end of the second comparator B, an output end of the inverter 141 is electrically connected to a first input end of the first nand gate C, a second input end of the first nand gate C is electrically connected to an output end of the second nand gate D, an output end of the first nand gate C is electrically connected to a first input end of the second nand gate D, and a second input end of the second nand gate D is electrically connected to an output end of the first comparator a.
In this embodiment, through the cooperation of the inverter 141, the first nand gate C and the second nand gate D, overall control of the comparison results of the first comparator a and the second comparator B is achieved, so that the adjustment judging unit 140 can generate corresponding adjustment control signals and send the corresponding adjustment control signals to the voltage-controlled oscillator 113.
Further, a source driver 10 is provided, the source driver 10 including the frequency control circuit 100 described above.
In one embodiment, if there is power/ground noise or input noise interference during the frequency locking of the frequency discriminator 120, if the frequency control circuit 100 is not provided, when the power/ground noise or input noise first enters the phase detector 111, the characteristic of the vco 113 changes according to the second input/output curve, and when the actual low frequency data input signal enters the phase detector 111, the characteristic of the vco 113 still changes according to the second input/output curve, in other words, the clock frequency signal of the output of the vco 113 is a high frequency clock signal in the second preset bandwidth area, so that the low frequency data input signal actually output in the first preset bandwidth area is distorted.
Further, by providing the frequency control circuit 100, when the power/ground noise or the input noise first enters the phase detector 111, the characteristic of the voltage-controlled oscillator 113 changes according to the second input/output curve, but when the actual low frequency data input signal enters the phase detector 111, the voltage Vin corresponding to the low frequency data input signal is less than or equal to V2, and at this time, the voltage Vin jumps from the second input/output curve (curve B2) to the first input/output curve (curve B1), and the first input/output curve is superior to the second input/output curve in terms of low frequency data efficiency, and by the control circuit 100, the effect of optimizing the low frequency efficiency can be achieved while the advantage of the high frequency at the second input/output curve can be maintained.
Further, there is provided a frequency control method applied to the source driver 10 described above, as shown in fig. 5, the frequency control method including:
step S200, a first preset level signal sent by a frequency discrimination circuit is received.
Step S210, receiving a voltage control signal sent by the charge pump.
Step S220, controlling the voltage-controlled oscillator to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator so that the voltage-controlled oscillator regulates the output of the voltage-controlled oscillator according to the voltage regulation control signal to output a regulated clock frequency signal.
Step S230, receiving the second preset level signal sent by the frequency discrimination circuit.
Step S240, controlling the state of the device to be in a stop working state according to the second preset level signal.
Further, a display panel including the above-described source driver 10 is provided.
That is, the foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, such as combining technical features of the embodiments, or directly or indirectly using the embodiments in other related technical fields, are included in the scope of the patent protection of the present application.
In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, the term "for example" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (8)
1. The frequency control circuit is characterized by being applied to a source driver, wherein the source driver comprises a clock recovery circuit and a frequency discrimination circuit, the clock recovery circuit comprises a phase detector, a charge pump and a voltage-controlled oscillator which are electrically connected in sequence, a first input end of the frequency discrimination circuit is electrically connected with an input end of the phase detector, a second input end of the frequency discrimination circuit is electrically connected with an output end of the voltage-controlled oscillator, a control end of the frequency discrimination circuit is electrically connected with an output end of the frequency discrimination circuit, an input end of the frequency discrimination circuit is electrically connected with an output end of the charge pump, and an output end of the frequency discrimination circuit is electrically connected with the voltage-controlled oscillator;
the phase detector is used for receiving an input data signal, detecting a phase difference between the input data signal and a clock signal and sending the phase difference to the charge pump;
the charge pump is used for outputting corresponding voltage control signals to the frequency control circuit and the voltage-controlled oscillator according to the phase difference;
the frequency control circuit is used for receiving a first preset level signal sent by the frequency discrimination circuit, controlling the frequency control circuit to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator;
the voltage-controlled oscillator is used for adjusting the output of the voltage-controlled oscillator according to the voltage adjustment control signal so as to output an adjusted clock frequency signal, and sending the adjusted clock frequency signal to the second input end of the frequency discrimination circuit;
the frequency discrimination circuit is used for comparing whether the input data signal is consistent with the clock frequency signal or not so as to perform frequency locking, and when the input data signal is consistent with the clock frequency signal, a second preset level signal is generated and sent to the frequency control circuit;
the frequency control circuit is used for controlling the frequency control circuit to be in a stop working state according to the second preset level signal;
the voltage regulation control signal comprises a first regulation control signal, the frequency control circuit comprises a voltage comparison unit and an adjustment judging unit which are electrically connected, the input end of the voltage comparison unit is electrically connected with the output end of the charge pump, the control end of the comparison unit is electrically connected with the output end of the frequency discrimination circuit, the output end of the adjustment judging unit is electrically connected with the voltage-controlled oscillator, the input-output curve of the voltage-controlled oscillator comprises a first input-output curve and a second input-output curve, and the output value of the first input-output curve corresponding to the same voltage control signal is smaller than the output value of the second input-output curve;
the voltage comparison unit is used for comparing the voltage control signal with a first preset voltage threshold value and a second preset voltage threshold value respectively, and the first preset voltage threshold value is larger than the second preset voltage threshold value;
after the source driver is started, the input-output curve of the voltage-controlled oscillator changes according to the first input-output curve;
when the voltage control signal is smaller than or equal to the first preset voltage threshold, the voltage-controlled oscillator is used for outputting a first clock frequency signal in a first preset bandwidth area according to the voltage control signal, and the first preset bandwidth area corresponds to the first input-output curve;
the frequency discrimination circuit is used for comparing whether the frequencies of the first clock frequency signal and the input data signal are consistent or not so as to discriminate the frequency;
when the voltage control signal is greater than the first preset voltage threshold, the frequency control circuit is further configured to generate the first adjustment control signal to the voltage-controlled oscillator;
the voltage-controlled oscillator is configured to output a second clock frequency signal in a second preset bandwidth area according to the first adjustment control signal and the voltage control signal, so that an input-output curve of the voltage-controlled oscillator changes according to the second input-output curve, and the second preset bandwidth area corresponds to the second input-output curve;
the frequency discrimination circuit is further used for comparing whether the frequencies of the second clock frequency signal and the input data signal are consistent or not so as to discriminate the frequency.
2. The frequency control circuit of claim 1, wherein the voltage regulation control signal further comprises a second regulation control signal;
after the input-output curve of the voltage-controlled oscillator jumps from the first input-output curve to the second input-output curve, when the voltage control signal is greater than or equal to the second preset voltage threshold value, the input-output curve of the voltage-controlled oscillator always changes according to the second input-output curve;
when the voltage control signal is smaller than the second preset voltage threshold, the frequency control circuit is further configured to generate a corresponding second adjustment control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is configured to output a first clock frequency signal in the first preset bandwidth area according to the second adjustment control signal and the voltage control signal, so that an input-output curve of the voltage-controlled oscillator changes according to the first input-output curve;
the frequency discrimination circuit is also used for comparing whether the frequencies of the corresponding first clock frequency signal and the input data signal are consistent or not so as to discriminate the frequency.
3. The frequency control circuit of claim 2, wherein after the voltage control signal changes when the voltage control signal is less than or equal to the first preset voltage threshold value after the input-output curve of the voltage controlled oscillator transitions from the second input-output curve to the first input-output curve, the input-output curve of the voltage controlled oscillator always changes according to the first input-output curve.
4. The frequency control circuit of claim 1, wherein the voltage controlled oscillator comprises a voltage-to-current unit and a current controlled oscillator electrically connected, a first input terminal of the voltage-to-current unit is electrically connected with an output terminal of the charge pump, and a second input terminal of the voltage-to-current unit is electrically connected with an output terminal of the adjustment judging unit;
the voltage-to-current unit is used for converting the voltage control signal into a corresponding current control signal;
the current control oscillator is used for converting the current control signal into a corresponding clock frequency signal;
the voltage-to-current unit is also used for receiving the voltage regulation control signal sent by the regulation judging unit and regulating the magnitude of the current control signal according to the voltage regulation control signal.
5. The frequency control circuit of claim 1, wherein the voltage comparison unit comprises a first comparator and a second comparator, the control ends of the first comparator and the second comparator are electrically connected with the output end of the frequency discrimination circuit, the first comparator is used for comparing the voltage control signal with the first preset voltage threshold, and the second comparator is used for comparing the voltage control signal with the second preset voltage threshold.
6. The frequency control circuit of claim 5, wherein the adjustment determination unit comprises an inverter, a first nand gate, and a second nand gate, wherein an input terminal of the inverter is electrically connected to an output terminal of the second comparator, an output terminal of the inverter is electrically connected to a first input terminal of the first nand gate, a second input terminal of the first nand gate is electrically connected to an output terminal of the second nand gate, an output terminal of the first nand gate is electrically connected to a first input terminal of the second nand gate, and a second input terminal of the second nand gate is electrically connected to an output terminal of the first comparator.
7. A source driver comprising the frequency control circuit of any one of claims 1 to 6.
8. A display panel comprising the source driver of claim 7.
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| CN202310273705.XA CN115985222B (en) | 2023-03-21 | 2023-03-21 | Frequency control circuit, source driver, frequency control method and display panel |
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| JP5363967B2 (en) * | 2009-12-22 | 2013-12-11 | ルネサスエレクトロニクス株式会社 | CLOCK DATA RECOVERY CIRCUIT, DISPLAY DEVICE DATA TRANSFER DEVICE, AND DISPLAY DEVICE DATA TRANSFER METHOD |
| CN103684439B (en) * | 2012-08-29 | 2016-12-21 | 群联电子股份有限公司 | Frequency produces system, voltage-controlled oscillator module and signal frequency method of adjustment |
| US9344097B2 (en) * | 2014-06-02 | 2016-05-17 | Texas Instruments Incorporated | Fast acquisition frequency detector |
| US9898561B2 (en) * | 2015-05-27 | 2018-02-20 | Altera Corporation | Behavioral simulation model for clock-data recovery phase-locked loop |
| CN113114225A (en) * | 2020-01-13 | 2021-07-13 | 光程研创股份有限公司 | Clock data recovery circuit and method of operating the same |
| CN114400889A (en) * | 2022-01-25 | 2022-04-26 | 上海感与执技术有限公司 | Output voltage control circuit and method for charge pump |
| CN115714596B (en) * | 2022-10-25 | 2023-06-02 | 北京显芯科技有限公司 | Clock data recovery circuit, display chip and display device |
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