CN115985222A - Frequency control circuit, source driver, frequency control method and display panel - Google Patents
Frequency control circuit, source driver, frequency control method and display panel Download PDFInfo
- Publication number
- CN115985222A CN115985222A CN202310273705.XA CN202310273705A CN115985222A CN 115985222 A CN115985222 A CN 115985222A CN 202310273705 A CN202310273705 A CN 202310273705A CN 115985222 A CN115985222 A CN 115985222A
- Authority
- CN
- China
- Prior art keywords
- voltage
- frequency
- input
- output
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model relates to a frequency control circuit, source driver, frequency control method and display panel, this frequency control circuit is applied to source driver, source driver includes clock recovery circuit and frequency discrimination circuit, clock recovery circuit includes phase detector, charge pump and the voltage controlled oscillator of electric connection in proper order, the first input of frequency discrimination circuit and the input electric connection of phase detector, the second input of frequency discrimination circuit and the output electric connection of voltage controlled oscillator, the control end of frequency control circuit is used for with the output electric connection of frequency discrimination circuit, the input of frequency control circuit is used for with the output electric connection of charge pump, the output of frequency control circuit is used for with voltage controlled oscillator electric connection, above-mentioned frequency control circuit has reduced the noise influence in the input data signal, and then make every source driver carry out analytic degree of accuracy greatly to the input data signal, also make the efficiency of every source driver tend to unanimity simultaneously.
Description
Technical Field
The present application relates to the field of display, and in particular, to a frequency control circuit, a source driver, a frequency control method, and a display panel.
Background
In a conventional display panel driver, a source driver generally receives Timing Control (TCON) data transmitted from a Timing Controller, analyzes the data by an internal clock recovery circuit, and outputs a driving voltage to a TFT display panel.
When each source driver receives and analyzes the timing control data, the accuracy of each source driver in analyzing the data is affected due to the fact that the timing control data may contain noise.
Disclosure of Invention
In view of the above, the present application provides a frequency control circuit, a source driver, a frequency control method and a display panel, which can improve the accuracy of the source driver in analyzing data.
A frequency control circuit is applied to a source driver, the source driver comprises a clock recovery circuit and a frequency discrimination circuit, the clock recovery circuit comprises a phase detector, a charge pump and a voltage-controlled oscillator which are electrically connected in sequence, a first input end of the frequency discrimination circuit is electrically connected with an input end of the phase detector, a second input end of the frequency discrimination circuit is electrically connected with an output end of the voltage-controlled oscillator, a control end of the frequency control circuit is electrically connected with an output end of the frequency discrimination circuit, an input end of the frequency control circuit is electrically connected with an output end of the charge pump, and an output end of the frequency control circuit is electrically connected with the voltage-controlled oscillator.
The phase detector is used for receiving an input data signal, detecting a phase difference between the input data signal and a clock signal and sending the phase difference to the charge pump.
The charge pump is used for outputting a corresponding voltage control signal to the frequency control circuit and the voltage-controlled oscillator according to the phase difference.
The frequency control circuit is used for receiving a first preset level signal sent by the frequency discrimination circuit, controlling the frequency discrimination circuit to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator.
The voltage-controlled oscillator is used for adjusting the output of the voltage-controlled oscillator according to the voltage adjusting control signal so as to output an adjusted clock frequency signal, and sending the adjusted clock frequency signal to the second input end of the frequency discrimination circuit.
The frequency discrimination circuit is used for comparing whether the input data signal is consistent with the clock frequency signal or not so as to carry out frequency locking, and when the input data signal is consistent with the clock frequency signal, a second preset level signal is generated and sent to the frequency control circuit;
and the frequency control circuit is used for controlling the frequency control circuit to be in a stop working state according to the second preset level signal.
In one embodiment, the voltage regulation control signal includes a first regulation control signal, the frequency control circuit includes a voltage comparison unit and an adjustment determination unit, the voltage comparison unit has an input terminal electrically connected to the output terminal of the charge pump, the comparison unit has a control terminal electrically connected to the output terminal of the frequency discrimination circuit, the adjustment determination unit has an output terminal electrically connected to the voltage controlled oscillator, the input/output curve of the voltage controlled oscillator includes a first input/output curve and a second input/output curve, and an output value of the first input/output curve corresponding to the same voltage control signal is smaller than an output value of the second input/output curve.
The voltage comparison unit is used for comparing the voltage control signal with a first preset voltage threshold and a second preset voltage threshold respectively, wherein the first preset voltage threshold is larger than the second preset voltage threshold.
After the source driver is started, the input-output curve of the voltage-controlled oscillator changes according to the first input-output curve.
When the voltage control signal is smaller than or equal to a first preset voltage threshold, the voltage-controlled oscillator is used for outputting a first clock frequency signal located in a first preset frequency width area according to the voltage control signal, and the first preset frequency width area corresponds to the first input-output curve.
The frequency discrimination circuit is used for comparing whether the frequency of the first clock frequency signal and the frequency of the input data signal are consistent or not so as to carry out frequency discrimination.
When the voltage control signal is greater than the first preset voltage threshold, the frequency control circuit is further configured to generate a first adjustment control signal to the voltage-controlled oscillator.
The voltage-controlled oscillator is used for outputting a second clock frequency signal in a second preset frequency width area according to the first adjusting control signal and the voltage control signal so as to enable an input-output curve of the voltage-controlled oscillator to change according to a second input-output curve, and the second preset frequency width area corresponds to the second input-output curve.
The frequency discrimination circuit is further used for comparing whether the frequency of the second clock frequency signal is consistent with that of the input data signal or not so as to perform frequency discrimination.
In one embodiment, the voltage regulation control signal further comprises a second regulation control signal.
After the input-output curve of the voltage-controlled oscillator jumps from the first input-output curve to the second input-output curve, when the voltage control signal is greater than or equal to a second preset voltage threshold, the input-output curve of the voltage-controlled oscillator always changes according to the second input-output curve.
When the voltage control signal is smaller than a second preset voltage threshold, the frequency control circuit is further used for generating a corresponding second adjusting control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is used for outputting a first clock frequency signal in a first preset frequency width area according to the second regulation control signal and the voltage control signal so as to enable an input-output curve of the voltage-controlled oscillator to change according to a first input-output curve.
The frequency discrimination circuit is further configured to compare whether the frequencies of the corresponding first clock frequency signal and the input data signal are consistent to perform frequency discrimination.
In one embodiment, after the input-output curve of the voltage-controlled oscillator changes from the second input-output curve to the first input-output curve, when the voltage control signal is smaller than or equal to the first preset voltage threshold, the input-output curve of the voltage-controlled oscillator always changes according to the first input-output curve.
In one embodiment, the voltage-controlled oscillator includes a voltage-to-current unit and a current-controlled oscillator electrically connected to each other, a first input of the voltage-to-current unit is electrically connected to an output of the charge pump, and a second input of the voltage-to-current unit is electrically connected to an output of the adjustment determination unit.
The voltage-to-current unit is used for converting the voltage control signal into a corresponding current control signal.
The current control oscillator is used for converting the current control signal into a corresponding clock frequency signal.
The voltage-to-current unit is also used for receiving the voltage regulation control signal sent by the regulation and judgment unit and regulating the magnitude of the current control signal according to the voltage regulation control signal.
In one embodiment, the voltage comparing unit includes a first comparator and a second comparator, wherein respective control terminals of the first comparator and the second comparator are electrically connected to the output terminal of the frequency discriminator circuit, the first comparator is configured to compare the voltage control signal with a first predetermined voltage threshold, and the second comparator is configured to compare the voltage control signal with a second predetermined voltage threshold.
In one embodiment, the adjustment determining unit includes an inverter, a first nand gate and a second nand gate, an input of the inverter is electrically connected to an output of the second comparator, an output of the inverter is electrically connected to a first input of the first nand gate, a second input of the first nand gate is electrically connected to an output of the second nand gate, an output of the first nand gate is electrically connected to a first input of the second nand gate, and a second input of the second nand gate is electrically connected to an output of the first comparator.
In addition, a source driver is provided, which includes the above frequency control circuit.
Further, there is provided a frequency control method applied to the source driver, the frequency control method including:
receiving a first preset level signal sent by a frequency discrimination circuit;
receiving a voltage control signal sent by a charge pump;
controlling the voltage-controlled oscillator to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator so that the voltage-controlled oscillator regulates the output of the voltage-controlled oscillator according to the voltage regulation control signal to output a regulated clock frequency signal;
receiving a second preset level signal sent by the frequency discrimination circuit;
and controlling the self to be in a stop working state according to the second preset level signal.
In addition, a display panel is provided, which includes the source driver.
The frequency control circuit is applied to a source driver, the source driver comprises a clock recovery circuit and a frequency discrimination circuit, the clock recovery circuit comprises a phase detector, a charge pump and a voltage-controlled oscillator which are electrically connected in sequence, a first input end of the frequency discrimination circuit is electrically connected with an input end of the phase detector, a second input end of the frequency discrimination circuit is electrically connected with an output end of the voltage-controlled oscillator, a control end of the frequency control circuit is electrically connected with an output end of the frequency discrimination circuit, an input end of the frequency control circuit is electrically connected with an output end of the charge pump, an output end of the frequency control circuit is electrically connected with the voltage-controlled oscillator, the phase detector is used for receiving an input data signal, detecting a phase difference between the input data signal and a clock signal and sending the phase difference to the charge pump, and the charge pump is used for outputting a corresponding voltage control signal to the frequency control circuit and the voltage-controlled oscillator according to the phase difference, the frequency control circuit is used for receiving a first preset level signal sent by the frequency discrimination circuit, controlling the frequency control circuit to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator, the voltage-controlled oscillator is used for regulating the output of the voltage-controlled oscillator according to the voltage regulation control signal so as to output a regulated clock frequency signal and sending the regulated clock frequency signal to a second input end of the frequency discrimination circuit, the frequency discrimination circuit is used for comparing whether an input data signal is consistent with the clock frequency signal so as to carry out frequency locking, when the input data signal is consistent with the clock frequency signal, a second preset level signal is generated and sent to the frequency control circuit so as to stop the frequency control circuit from working, and the output of the voltage-controlled oscillator can be regulated by setting the frequency control circuit, the voltage-controlled oscillator outputs the adjusted clock frequency signal, so that the frequency discrimination circuit finishes frequency locking, the noise influence in the input data signal is reduced, the accuracy of analyzing the input data signal by each source driver is greatly improved, and the efficiency of each source driver tends to be consistent.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram of a frequency control circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a variation of an input/output curve of a voltage-controlled oscillator according to an embodiment of the present application;
fig. 3 is a block diagram of a voltage-controlled oscillator according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of an adjustment determining unit according to an embodiment of the present disclosure;
fig. 5 is a flowchart illustrating a frequency control method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. Based on the embodiments in the present application. The following embodiments and their technical features may be combined with each other without conflict.
As shown in fig. 1, a frequency control circuit 100 is provided, the frequency control circuit 100 is applied to a source driver 10, the source driver 10 includes a clock recovery circuit 110 and a frequency discrimination circuit 120, the clock recovery circuit 110 includes a phase detector 111, a charge pump 112 and a voltage controlled oscillator 113 electrically connected in sequence, a first input terminal of the frequency discrimination circuit 120 is electrically connected to an input terminal of the phase detector 111, a second input terminal of the frequency discrimination circuit 120 is electrically connected to an output terminal of the voltage controlled oscillator, a control terminal of the frequency control circuit 100 is electrically connected to an output terminal of the frequency discrimination circuit 120, an input terminal of the frequency control circuit 100 is electrically connected to an output terminal of the charge pump 112, and an output terminal of the frequency control circuit 100 is electrically connected to the voltage controlled oscillator.
The phase detector 111 is configured to receive an input data signal, detect a phase difference between the input data signal and a clock signal, and send the phase difference to the charge pump 112.
The charge pump 112 is configured to output a corresponding voltage control signal to the frequency control circuit 100 and the voltage controlled oscillator 113 according to the phase difference.
The frequency control circuit 100 is configured to receive the first preset level signal sent by the frequency discriminator circuit 120, control itself to be in a working state according to the first preset level signal, generate a voltage adjustment control signal according to the voltage control signal, and send the voltage adjustment control signal to the voltage-controlled oscillator 113.
The voltage controlled oscillator 113 is configured to adjust its output according to the voltage adjustment control signal to output an adjusted clock frequency signal, and send the adjusted clock frequency signal to the second input terminal of the frequency discriminator circuit 120.
The frequency discriminator circuit 120 is configured to compare whether the input data signal is consistent with the clock frequency signal to perform frequency locking, generate a second preset level signal and send the second preset level signal to the frequency control circuit 100 when the input data signal is consistent with the clock frequency signal, and the frequency control circuit 100 controls itself to be in a stop state according to the second preset level signal.
In this embodiment, by setting the frequency control circuit 100, the output of the voltage controlled oscillator 113 can be adjusted, so that the voltage controlled oscillator 113 outputs the adjusted clock frequency signal, so that the frequency discrimination circuit 120 completes frequency locking, and reduces noise influence in the input data signal, thereby greatly improving the accuracy of analyzing the input data signal by each source driver 10, and simultaneously making the performance of each source driver 10 approach to uniformity.
In one embodiment, the voltage adjustment control signal comprises a first adjustment control signal, as shown in fig. 1, the frequency control circuit 100 comprises a voltage comparison unit 130 and an adjustment determination unit 140 electrically connected to each other, an input terminal of the voltage comparison unit 130 is electrically connected to an output terminal of the charge pump 112, a control terminal of the comparison unit is electrically connected to an output terminal of the frequency discrimination circuit 120, and an output terminal of the adjustment determination unit 140 is electrically connected to the vco 113.
The input/output curves of the vco 113 include a first input/output curve and a second input/output curve, and an output value of the first input/output curve corresponding to the same voltage control signal is smaller than an output value of the second input/output curve.
The voltage comparing unit 130 is configured to compare the voltage control signal with a first preset voltage threshold and a second preset voltage threshold, where the first preset voltage threshold is greater than the second preset voltage threshold.
After the source driver 10 is started, the input/output curve of the vco 113 changes according to the first input/output curve.
When the voltage control signal is less than or equal to the first preset voltage threshold, the vco 113 is configured to output a first clock frequency signal in a first preset bandwidth region according to the voltage control signal, where the first preset bandwidth region corresponds to the first input/output curve.
The frequency discrimination circuit 120 is used to compare whether the frequencies of the first clock frequency signal and the input data signal are consistent for frequency discrimination.
The frequency control circuit 100 is further configured to generate a first adjustment control signal to the voltage controlled oscillator 113 when the voltage control signal is greater than a first preset voltage threshold.
The voltage-controlled oscillator 113 is configured to output a second clock frequency signal located in a second predetermined bandwidth region according to the first adjustment control signal and the voltage control signal, so that an input/output curve of the voltage-controlled oscillator 113 changes according to a second input/output curve, and the second predetermined bandwidth region corresponds to the second input/output curve.
The frequency discrimination circuit 120 is further configured to compare whether the frequencies of the second clock frequency signal and the input data signal are consistent for frequency discrimination.
As shown in fig. 2, an abscissa Vin is an input signal (i.e., a voltage control signal) of the vco 113 and has a unit of volt, an ordinate f is an output value (in Hz) of the vco 113, V1 is a first preset voltage threshold, V2 is a second preset voltage threshold, V2 is smaller than V1, a curve B1 is a first input/output curve of the vco, a curve B2 is a second input/output curve of the vco, the curve B1 corresponds to a low-frequency output curve (corresponding to a first preset bandwidth region) of the vco, and the curve B2 corresponds to a high-frequency output curve (corresponding to a second preset bandwidth region) of the vco.
In one embodiment, the first predefined bandwidth region corresponds to a low frequency output region of the vco 113, and the second predefined bandwidth region corresponds to a high frequency output region of the vco 113.
After the source driver 10 is turned on, the input data signal is usually searched from a low frequency, and frequency discrimination is performed by the frequency discrimination circuit 113, that is, the input/output curve of the voltage controlled oscillator 113 changes according to the curve B1 in fig. 2, and the output of the voltage controlled oscillator 113 changes in the inner region near both sides of the curve B1.
When the voltage control signal is greater than the first preset voltage threshold V1, the frequency control circuit 100 generates a first adjustment control signal to the voltage-controlled oscillator 113, where the voltage-controlled oscillator 113 is configured to output a second clock frequency signal located in a second preset frequency bandwidth region according to the first adjustment control signal and the voltage control signal, so as to change an input/output curve of the voltage-controlled oscillator 113 according to a second input/output curve, and the second preset frequency bandwidth region corresponds to the second input/output curve, at this time, the input/output curve of the voltage-controlled oscillator 113 jumps from the curve B1 to the curve B2 to change, which is equivalent to optimizing the output performance of the first input/output curve of the voltage-controlled oscillator 113 when the voltage control signal is greater than the first preset voltage threshold V1, thereby reducing the noise influence in the input data signal, further greatly improving the accuracy of analyzing the input data signal by each source driver 10, and making the performance of each source driver 10 tend to be consistent.
In one embodiment, the voltage regulation control signal further comprises a second regulation control signal.
As shown in fig. 2, that is, the input/output curve of the voltage controlled oscillator 113 changes according to the curve B2 in fig. 2, the output of the voltage controlled oscillator 113 changes in the inner area near the two sides of the curve B2, when the voltage control signal is smaller than the second preset voltage threshold V2, the frequency control circuit 100 is further configured to generate a corresponding second adjustment control signal to the voltage controlled oscillator 113, the voltage controlled oscillator 113 is configured to output a second clock frequency signal located in the second preset bandwidth area according to the second adjustment control signal, at this time, the output of the voltage controlled oscillator 113 jumps from the curve B2 to the curve B1 to change, the second clock frequency signal corresponding to the voltage control signal in the output curve B1 is equivalent to optimizing the output performance of the second input/output curve of the voltage controlled oscillator 113 when the voltage control signal is smaller than the second preset voltage threshold V2, noise influence in the input data signal is reduced, and the accuracy of analyzing the input data signal by each source driver 10 is greatly improved, and the performance of each source driver 10 tends to be consistent.
In one embodiment, the voltage regulation control signal further comprises a second regulation control signal.
After the input/output curve of the voltage-controlled oscillator 113 is changed from the first input/output curve to the second input/output curve, when the voltage control signal is greater than or equal to the second preset voltage threshold, the input/output curve of the voltage-controlled oscillator 113 always changes according to the second input/output curve.
When the voltage control signal is smaller than the second preset voltage threshold, the frequency control circuit 100 is further configured to generate a corresponding second adjustment control signal to the voltage controlled oscillator 113.
The voltage-controlled oscillator 113 is configured to output a first clock frequency signal in a first predetermined bandwidth region according to the second adjustment control signal and the voltage control signal, so that an input/output curve of the voltage-controlled oscillator 113 changes according to the first input/output curve.
The frequency discrimination circuit 100 is further configured to compare whether the frequencies of the corresponding first clock frequency signal and the input data signal are consistent for frequency discrimination.
In this embodiment, after the input/output curve of the voltage-controlled oscillator 113 is changed from the first input/output curve to the second input/output curve, when the voltage control signal is greater than or equal to the second preset voltage threshold, the input/output curve of the voltage-controlled oscillator 113 always changes according to the second input/output curve, the output of the voltage-controlled oscillator 113 changes in the inner area near the two sides of the curve B2, when the voltage control signal is less than the second preset voltage threshold V2, the frequency control circuit 100 is further configured to generate a corresponding second adjustment control signal to the voltage-controlled oscillator 113, the voltage-controlled oscillator 113 is further configured to output the first clock frequency signal located in the first preset area according to the second adjustment control signal and the voltage control signal, so that the input/output curve of the voltage-controlled oscillator 113 changes according to the first input/output curve, at this time, the input/output curve of the voltage-controlled oscillator 113 jumps from the curve B2 to the curve B1, which is equivalent to optimize the output performance of the second input/output curve of the voltage-controlled oscillator 113 when the voltage control signal is less than the second preset voltage threshold V2, thereby reducing the influence of the input data signal, and greatly improving the accuracy of each source driver 10, so that the source driver also tends to greatly improve the source performance.
In one embodiment, after the input/output curve of the voltage controlled oscillator 113 changes from the second input/output curve to the first input/output curve, when the voltage control signal is less than or equal to the first preset voltage threshold, the input/output curve of the voltage controlled oscillator 113 always changes according to the first input/output curve. In one embodiment, as shown in fig. 3, the vco 113 includes a voltage-to-current unit 114 and a current-controlled oscillator 115 electrically connected to each other, a first input terminal of the voltage-to-current unit 114 is electrically connected to the output terminal of the charge pump 112, and a second input terminal of the voltage-to-current unit 114 is electrically connected to the output terminal of the adjustment determining unit 140.
The voltage-to-current unit 114 is used for converting the voltage control signal into a corresponding current control signal.
The current controlled oscillator 115 is used to convert the current control signal to a corresponding clock frequency signal.
The voltage-to-current unit 114 is further configured to receive the voltage adjustment control signal sent by the adjustment determining unit 140, and adjust the magnitude of the current control signal according to the voltage adjustment control signal.
The second input terminal of the voltage-to-current conversion unit 114 is electrically connected to the output terminal of the adjustment determination unit 140, and the voltage control signal sent by the adjustment determination unit 140 is received to control the voltage control signal to be converted into a corresponding current control signal, so that the overall output of the voltage-controlled oscillator 113 is adjusted.
In one embodiment, the voltage comparing unit 130 includes a first comparator a and a second comparator B, wherein respective control terminals of the first comparator a and the second comparator B are electrically connected to the output terminal of the frequency discriminator circuit 120, the first comparator a is configured to compare the voltage control signal with a first predetermined voltage threshold, and the second comparator B is configured to compare the voltage control signal with a second predetermined voltage threshold.
In one embodiment, as shown in fig. 4, the adjustment determining unit 140 includes an inverter 141, a first nand gate C and a second nand gate D, an input of the inverter 141 is electrically connected to an output of the second comparator B, an output of the inverter 141 is electrically connected to a first input of the first nand gate C, a second input of the first nand gate C is electrically connected to an output of the second nand gate D, an output of the first nand gate C is electrically connected to a first input of the second nand gate D, and a second input of the second nand gate D is electrically connected to an output of the first comparator a.
In this embodiment, by matching the inverter 141, the first nand gate C, and the second nand gate D, overall control of the comparison result of the first comparator a and the comparison result of the second comparator B are achieved, and the adjustment determining unit 140 can generate a corresponding adjustment control signal and send the adjustment control signal to the voltage-controlled oscillator 113.
In addition, a source driver 10 is provided, and the source driver 10 includes the frequency control circuit 100.
In an embodiment, assuming that an actual input data signal is a low frequency signal, if there is power/ground noise or input noise interference during the frequency locking process of the frequency discrimination circuit 100, if the frequency control circuit 100 is not provided, when the power/ground noise or input noise enters the phase detector 111 first, the characteristic of the voltage controlled oscillator 113 changes according to the second input/output curve, and further when the actual low frequency data input signal enters the phase detector 111, the characteristic of the voltage controlled oscillator 113 still changes according to the second input/output curve, in other words, the output clock frequency signal of the voltage controlled oscillator 113 is a high frequency clock signal in the second preset bandwidth region, so that the actual output low frequency data input signal in the first preset bandwidth region is distorted.
Further, by providing the frequency control circuit 100, when the power/ground noise or the input noise first enters the phase detector 111, although the characteristic of the voltage controlled oscillator 113 changes according to the second input/output curve, when the actual low-frequency data input signal enters the phase detector 111, since the voltage Vin corresponding to the low-frequency data input signal is less than or equal to V2, the low-frequency data input signal jumps from the second input/output curve (curve B2) to the first input/output curve (curve B1), and the first input/output curve is better than the second input/output curve in terms of low-frequency data performance, the control circuit 100 can achieve the effect of optimizing the low-frequency performance while maintaining the advantage of the high-frequency input/output curve.
Further, there is provided a frequency control method applied to the source driver 10 described above, as shown in fig. 5, the frequency control method including:
step S200, receiving a first preset level signal sent by the frequency discriminator circuit.
Step S210, receiving a voltage control signal sent by the charge pump.
And step S220, controlling the voltage-controlled oscillator to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal, and sending the voltage regulation control signal to the voltage-controlled oscillator so that the voltage-controlled oscillator regulates the output of the voltage-controlled oscillator according to the voltage regulation control signal to output a regulated clock frequency signal.
In step S230, the second preset level signal sent by the frequency discriminator circuit is received.
And step S240, controlling the self state to be in a work stop state according to the second preset level signal.
In addition, a display panel is provided, which includes the source driver 10 described above.
That is, the above are only embodiments of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings of the present application, such as the combination of technical features between various embodiments, or the direct or indirect application to other related technical fields, are all included in the scope of the present application.
In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "for example" is used to mean "serving as an example, instance, or illustration". Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (10)
1. A frequency control circuit is applied to a source driver, the source driver comprises a clock recovery circuit and a frequency discrimination circuit, the clock recovery circuit comprises a phase detector, a charge pump and a voltage-controlled oscillator which are electrically connected in sequence, a first input end of the frequency discrimination circuit is electrically connected with an input end of the phase detector, a second input end of the frequency discrimination circuit is electrically connected with an output end of the voltage-controlled oscillator, a control end of the frequency control circuit is electrically connected with an output end of the frequency discrimination circuit, an input end of the frequency control circuit is electrically connected with an output end of the charge pump, and an output end of the frequency control circuit is electrically connected with the voltage-controlled oscillator;
the phase detector is used for receiving an input data signal, detecting a phase difference between the input data signal and a clock signal and sending the phase difference to the charge pump;
the charge pump is used for outputting a corresponding voltage control signal to the frequency control circuit and the voltage-controlled oscillator according to the phase difference;
the frequency control circuit is used for receiving a first preset level signal sent by the frequency discrimination circuit, controlling the frequency discrimination circuit to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal and sending the voltage regulation control signal to the voltage-controlled oscillator;
the voltage-controlled oscillator is used for adjusting the output of the voltage-controlled oscillator according to the voltage adjustment control signal so as to output an adjusted clock frequency signal and sending the adjusted clock frequency signal to the second input end of the frequency discrimination circuit;
the frequency discrimination circuit is used for comparing whether the input data signal is consistent with the clock frequency signal or not so as to carry out frequency locking, and when the input data signal is consistent with the clock frequency signal, a second preset level signal is generated and sent to the frequency control circuit;
and the frequency control circuit is used for controlling the frequency control circuit to be in a work stop state according to the second preset level signal.
2. The frequency control circuit according to claim 1, wherein the voltage regulation control signal comprises a first regulation control signal, the frequency control circuit comprises an electrically connected voltage comparison unit and an adjustment judgment unit, an input terminal of the voltage comparison unit is electrically connected to an output terminal of the charge pump, a control terminal of the comparison unit is electrically connected to an output terminal of the frequency discrimination circuit, an output terminal of the adjustment judgment unit is electrically connected to the voltage-controlled oscillator, an input-output curve of the voltage-controlled oscillator comprises a first input-output curve and a second input-output curve, and an output value of the first input-output curve corresponding to a same voltage control signal is smaller than an output value of the second input-output curve;
the voltage comparison unit is used for comparing the voltage control signal with a first preset voltage threshold and a second preset voltage threshold respectively, wherein the first preset voltage threshold is larger than the second preset voltage threshold;
after the source driver is started, the input-output curve of the voltage-controlled oscillator changes according to the first input-output curve;
when the voltage control signal is less than or equal to the first preset voltage threshold, the voltage-controlled oscillator is configured to output a first clock frequency signal located in a first preset frequency bandwidth region according to the voltage control signal, where the first preset frequency bandwidth region corresponds to the first input/output curve;
the frequency discrimination circuit is used for comparing whether the frequencies of the first clock frequency signal and the input data signal are consistent or not so as to carry out frequency discrimination;
when the voltage control signal is greater than the first preset voltage threshold, the frequency control circuit is further configured to generate the first adjustment control signal to the voltage-controlled oscillator;
the voltage-controlled oscillator is used for outputting a second clock frequency signal in a second preset frequency width area according to the first adjusting control signal and the voltage control signal so as to enable an input-output curve of the voltage-controlled oscillator to change according to the second input-output curve, and the second preset frequency width area corresponds to the second input-output curve;
the frequency discrimination circuit is further used for comparing whether the frequencies of the second clock frequency signal and the input data signal are consistent or not so as to perform frequency discrimination.
3. The frequency control circuit of claim 2, wherein the voltage regulation control signal further comprises a second regulation control signal;
after the input/output curve of the voltage-controlled oscillator jumps from the first input/output curve to the second input/output curve, when the voltage control signal is greater than or equal to the second preset voltage threshold, the input/output curve of the voltage-controlled oscillator always changes according to the second input/output curve;
when the voltage control signal is smaller than the second preset voltage threshold, the frequency control circuit is further configured to generate a corresponding second adjustment control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is used for outputting a first clock frequency signal in the first preset frequency width area according to the second regulation control signal and the voltage control signal so as to enable an input-output curve of the voltage-controlled oscillator to change according to the first input-output curve;
the frequency discrimination circuit is further used for comparing whether the frequencies of the corresponding first clock frequency signal and the input data signal are consistent or not so as to perform frequency discrimination.
4. The frequency control circuit of claim 3, wherein after the input-output curve of the voltage-controlled oscillator changes from the second input-output curve to the first input-output curve, when the voltage control signal is less than or equal to the first preset voltage threshold, the input-output curve of the voltage-controlled oscillator always changes according to the first input-output curve.
5. The frequency control circuit of claim 2, wherein the voltage controlled oscillator comprises a voltage-to-current unit and a current controlled oscillator electrically connected to each other, a first input of the voltage-to-current unit is electrically connected to the output of the charge pump, and a second input of the voltage-to-current unit is electrically connected to the output of the adjustment determination unit;
the voltage-to-current unit is used for converting the voltage control signal into a corresponding current control signal;
the current control oscillator is used for converting the current control signal into a corresponding clock frequency signal;
the voltage-to-current unit is further configured to receive a voltage adjustment control signal sent by the adjustment determining unit, and adjust the magnitude of the current control signal according to the voltage adjustment control signal.
6. The frequency control circuit according to claim 2, wherein the voltage comparing unit comprises a first comparator and a second comparator, respective control terminals of the first comparator and the second comparator are electrically connected to the output terminal of the frequency discriminator, the first comparator is configured to compare the voltage control signal with the first preset voltage threshold, and the second comparator is configured to compare the voltage control signal with the second preset voltage threshold.
7. The frequency control circuit of claim 6, wherein the adjustment determining unit comprises an inverter, a first NAND gate and a second NAND gate, an input of the inverter is electrically connected to an output of the second comparator, an output of the inverter is electrically connected to a first input of the first NAND gate, a second input of the first NAND gate is electrically connected to an output of the second NAND gate, an output of the first NAND gate is electrically connected to a first input of the second NAND gate, and a second input of the second NAND gate is electrically connected to an output of the first comparator.
8. A source driver comprising the frequency control circuit of any one of claims 1 to 7.
9. A frequency control method applied to the source driver of claim 8, the frequency control method comprising:
receiving a first preset level signal sent by the frequency discrimination circuit;
receiving a voltage control signal sent by the charge pump;
controlling the voltage-controlled oscillator to be in a working state according to the first preset level signal, generating a voltage regulation control signal according to the voltage control signal, and sending the voltage regulation control signal to the voltage-controlled oscillator so that the voltage-controlled oscillator regulates the output of the voltage-controlled oscillator according to the voltage regulation control signal to output a regulated clock frequency signal;
receiving a second preset level signal sent by the frequency discrimination circuit;
and controlling the self to be in a stop working state according to the second preset level signal.
10. A display panel comprising the source driver of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310273705.XA CN115985222B (en) | 2023-03-21 | 2023-03-21 | Frequency control circuit, source driver, frequency control method and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310273705.XA CN115985222B (en) | 2023-03-21 | 2023-03-21 | Frequency control circuit, source driver, frequency control method and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115985222A true CN115985222A (en) | 2023-04-18 |
| CN115985222B CN115985222B (en) | 2023-06-16 |
Family
ID=85970541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310273705.XA Active CN115985222B (en) | 2023-03-21 | 2023-03-21 | Frequency control circuit, source driver, frequency control method and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115985222B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103847A (en) * | 2009-12-22 | 2011-06-22 | 瑞萨电子株式会社 | Clock data recovery circuit, data transfer device for display device, and data transfer method for display device |
| CN103684439A (en) * | 2012-08-29 | 2014-03-26 | 群联电子股份有限公司 | Frequency generation system, voltage-controlled oscillator module and signal frequency adjustment method |
| US20150349785A1 (en) * | 2014-06-02 | 2015-12-03 | Texas Instruments Incorporated | Fast acquisition frequency detector |
| US20160350455A1 (en) * | 2015-05-27 | 2016-12-01 | Altera Corporation | Behavioral simulation model for clock-data recovery phase-locked loop |
| CN113114225A (en) * | 2020-01-13 | 2021-07-13 | 光程研创股份有限公司 | Clock data recovery circuit and method of operating the same |
| CN114400889A (en) * | 2022-01-25 | 2022-04-26 | 上海感与执技术有限公司 | Output voltage control circuit and method for charge pump |
| CN115714596A (en) * | 2022-10-25 | 2023-02-24 | 北京显芯科技有限公司 | Clock data recovery circuit, display chip and display device |
-
2023
- 2023-03-21 CN CN202310273705.XA patent/CN115985222B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103847A (en) * | 2009-12-22 | 2011-06-22 | 瑞萨电子株式会社 | Clock data recovery circuit, data transfer device for display device, and data transfer method for display device |
| CN103684439A (en) * | 2012-08-29 | 2014-03-26 | 群联电子股份有限公司 | Frequency generation system, voltage-controlled oscillator module and signal frequency adjustment method |
| US20150349785A1 (en) * | 2014-06-02 | 2015-12-03 | Texas Instruments Incorporated | Fast acquisition frequency detector |
| US20160350455A1 (en) * | 2015-05-27 | 2016-12-01 | Altera Corporation | Behavioral simulation model for clock-data recovery phase-locked loop |
| CN113114225A (en) * | 2020-01-13 | 2021-07-13 | 光程研创股份有限公司 | Clock data recovery circuit and method of operating the same |
| CN114400889A (en) * | 2022-01-25 | 2022-04-26 | 上海感与执技术有限公司 | Output voltage control circuit and method for charge pump |
| CN115714596A (en) * | 2022-10-25 | 2023-02-24 | 北京显芯科技有限公司 | Clock data recovery circuit, display chip and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115985222B (en) | 2023-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102868399B (en) | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method | |
| US5854543A (en) | Inverter circuit for lighting a cold cathode tube by the use of a piezoelectric transformer | |
| US7208988B2 (en) | Clock generator | |
| US20130162229A1 (en) | Charge pump feedback control device and method using the same | |
| EP0777333A1 (en) | Power saving PLL circuit | |
| US11385297B2 (en) | Electrical leakage determination system | |
| KR20020050374A (en) | Method for controling a host bus clock in portable computer | |
| JP2003517757A (en) | Slip detector and detection method for improving lock time of phase locked loop | |
| US20100073093A1 (en) | Automatic Frequency Compensation for Pulse Width Modulated RF Level Control | |
| US6992516B2 (en) | Pulse duty cycle automatic correction device and method thereof | |
| EP4080770A1 (en) | Phase locked loop generating adaptive driving voltage and related operating method | |
| US8368320B2 (en) | Cold cathode fluorescent lamp driving circuits and associated methods of control | |
| US6788028B2 (en) | Charging a battery using constant voltage and pulse | |
| CN115985222A (en) | Frequency control circuit, source driver, frequency control method and display panel | |
| US20090079480A1 (en) | Oscillating apparatus | |
| CN115985221B (en) | Source driver, bandwidth adjusting method and display panel | |
| CN1866746B (en) | System and method for optimizing phase locked loop damping coefficient | |
| CN104836571A (en) | Clock pulse adjusting device and clock pulse adjusting method | |
| CN109712591B (en) | Time sequence control method, time sequence control chip and display device | |
| EP3809594A1 (en) | Reference clock duty ratio calibration circuit | |
| US20070201594A1 (en) | Phase Locked Loop (Pll) Circuit, Its Phasing Method And Operation Analyzing Method | |
| US10938379B2 (en) | Automatic frequency modulation circuit and automatic frequency modulation method applied to pulse-width modulation system | |
| US20070153949A1 (en) | PLL apparatus with power saving mode and method for implementing the same | |
| CN109818614B (en) | Time sequence control method, time sequence control chip and display device | |
| CN110121043B (en) | Display power supply device and display system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |