CN115966469A - Low-temperature low-cost homogeneous double-semiconductor-layer thin film transistor and preparation method thereof - Google Patents
Low-temperature low-cost homogeneous double-semiconductor-layer thin film transistor and preparation method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of thin film transistors, in particular to a low-temperature and low-cost homogeneous double-semiconductor-layer thin film transistor and a preparation method thereof. The invention is based on that a target material is deposited under different oxygen partial pressure environments to form a double semiconductor layer, a polymethyl methacrylate material is used as an insulating layer, aluminum is used as a source electrode, a drain electrode and a gate electrode, and a thin film transistor with a top gate coplanar structure is prepared on a common glass substrate. According to the invention, the homogeneous double semiconductor layers are prepared at room temperature by adopting a radio frequency magnetron sputtering method, and the first semiconductor layer in contact with the glass substrate is prepared under a lower oxygen partial pressure, so that the first semiconductor layer has high carrier concentration, and high on-state current and high mobility of the device are ensured; the second semiconductor layer which covers the first semiconductor layer and is in contact with the source electrode and the drain electrode is prepared under higher oxygen partial pressure, so that the second semiconductor layer has low carrier concentration, low off-state current of the device is realized, and low energy consumption of the device is ensured.
Description
Technical Field
The invention relates to the technical field of thin film transistors, in particular to a low-temperature and low-cost homogeneous double-semiconductor-layer thin film transistor and a preparation method thereof.
Background
A Thin Film Transistor (TFT) is used as a core component in an Active Matrix organic Light-Emitting Diode (AMOLED) technology, and includes several important components, such as a substrate, a semiconductor layer, an insulating layer, a gate electrode, a source electrode, and a drain electrode. At present, amorphous oxide thin film transistors (AOS TFTs) are expected to be the most potential substitute for conventional amorphous silicon or polysilicon TFTs due to their high visible light transmittance, good uniformity and good environmental stability, and are potentially applied to novel display fields such as flexible display and transparent display. Since indium gallium zinc oxide (In-Ga-Zn-O) Thin Film Transistors (TFTs) have been reported, amorphous Oxide Semiconductor (AOS) based oxide TFTs have been extensively studied. However, with the progress of research, ga as a rare element greatly increases the research cost.
Indium aluminum zinc oxide In-Al-Zn-O (IAZO) because Al-O has higher binding energy and higher carrier mobility than Ga-O, a stable amorphous structure is considered as a material that can be used as a semiconductor layer instead of IGZO. However, studies have shown that the control of carrier concentration in IAZO thin films directly affects their applicability in TFTs. The current research reports show that the carrier concentration of the IAZO semiconductor layer can be regulated and controlled by carrying out high-temperature annealing on the IAZO semiconductor layer or adjusting the In-Al-Zn ratio and coating process parameters (such as oxygen partial pressure and sputtering power), but the IAZO semiconductor layer is difficult to be compatible with a flexible substrate due to the fact that higher processing temperature (not less than 150 ℃) is involved In the high-temperature annealing process; and the corresponding device is reduced based on the optimization of In-Al-Zn material composition or semiconductor film forming process conditionsThe off-state current often needs to sacrifice the mobility of the device. In addition, the semiconductor layer and the conventional inorganic insulating layer (SiO) are considered in terms of device structure 2 、Al 2 O 3 、Si 3 N 4 Etc.), the current TFT often adopts a bottom gate structure in which the semiconductor layer is exposed to the atmosphere, and oxygen and moisture in the atmosphere can be adsorbed on the surface of the semiconductor layer to affect the stability of the device, even though the passivation layer is introduced for protection, the cost is sacrificed.
In addition, there are many disadvantages in the current manufacturing of thin film transistors, such as: the bottom gate structure is mostly adopted, the semiconductor layer is exposed in the atmosphere, and the moisture and oxygen in the atmosphere can degrade the performance of the semiconductor layer; the preparation difficulty and the preparation cost are higher when the preparation is carried out by adopting technical means such as a photoresist process and the like; when the carrier concentration of the semiconductor layer is regulated and controlled based on other additional low-temperature process methods, key electrical parameters (such as mobility and off-state current) which affect the performance of the device cannot be independently regulated and controlled, and even the method is not environment-friendly; the magnetron sputtering method or the pulse enhanced gas deposition method is adopted to prepare the dielectric layer, so that the cost is increased. The current technical scheme can not solve the problems well at the same time, such as: patent application CN202111561524.4 (an indium tin oxide-based fully transparent thin film transistor and a preparation method thereof) adopts a photoresist process, which is difficult to prepare and has high cost; patent application CN201910601920.1 (an indium aluminum zinc oxide thin film transistor based on dual active layers and a preparation method thereof), the insulating layer preparation temperature is high, and the insulating layer is not suitable for a flexible substrate; in patent application CN201910602774.4 (a method for preparing an indium-aluminum-zinc oxide thin film transistor in a low-temperature environment), the carrier concentration of a semiconductor layer cannot be independently regulated and controlled, and ultraviolet ozone treatment is additionally utilized to regulate and control the carrier concentration of the semiconductor layer, so that when the carrier concentration of the semiconductor layer is regulated and controlled based on the additional scheme, key electrical parameters (such as mobility and off-state current) affecting the performance of a device cannot be independently regulated and controlled, and the operating environment is not environment-friendly; in patent application CN201910601922.0 (an indium aluminum zinc oxide thin film transistor based on a high-dielectric-constant gate dielectric layer and a full-room-temperature preparation method thereof), an insulating layer of the transistor is also prepared by a magnetron sputtering method, and the cost is high.
Therefore, it is important to develop a thin film transistor that has low temperature, low cost, low off-state current (without sacrificing device mobility), and can better solve the existing problems.
Disclosure of Invention
In order to solve the technical problems in the prior art. The invention provides a thin film transistor with a homogeneous double semiconductor layer and a preparation method thereof, wherein the thin film transistor is low in temperature (100 ℃), low in cost and capable of effectively reducing off-state current of a device without sacrificing mobility.
A method for preparing a low-temperature low-cost homogeneous double-semiconductor-layer thin film transistor comprises the following steps:
(1) Based on an indium aluminum zinc oxide target, in the range of (0-3.5X 10) -2 Pa) oxygen partial pressure and (0.5-1.0 Pa) argon working pressure are subjected to sputtering film formation on a cleaned glass substrate by a radio frequency magnetron sputtering method to obtain a first semiconductor layer;
(2) Based on an indium aluminum zinc oxide target at (5.5X 10) -2 ～12×10 -2 Pa) oxygen partial pressure and argon working pressure of (0.5-1.0 Pa) are adopted to sputter a film on the first semiconductor layer obtained in the step (1) by a radio frequency magnetron sputtering method to obtain a second semiconductor layer and form a double semiconductor layer structure;
(3) Combining a mask, and preparing a source electrode and a drain electrode on the double-semiconductor layer obtained in the step (2) by using a vacuum thermal evaporation method;
(4) Preparing a PMMA insulating layer on the double semiconductor layer comprising the source electrode and the drain electrode by using an organic solution dissolved with polymethyl methacrylate by adopting a dip-coating process;
(5) And combining the mask, and preparing a gate electrode on the PMMA insulating layer by using a vacuum thermal evaporation method to obtain the thin film transistor with the double semiconductor layers.
Further, in the step (1), the purity of the target indium aluminum zinc oxide used in the step is more than 99.99%.
Further, the step (1), wherein the indium aluminum zinc oxide target used has an indium aluminum zinc molar ratio of indium: aluminum: zinc = 1.
Further, the sputtering film formation in the steps (1) and (2) may be performed at room temperature for 4 to 40 minutes.
Further, the method using vacuum thermal evaporation in the step (3) comprises the following specific operation steps: and preparing a source electrode and a drain electrode by taking aluminum oxide as a mask, controlling the thermal evaporation current to be 40-50A and the thermal evaporation voltage to be 2.5-5.5V, and finally obtaining the source electrode and the drain electrode of the thin film transistor which are both metal aluminum electrodes.
Further, the organic solution dissolved with polymethyl methacrylate in the step (4) is prepared by dissolving polymethyl methacrylate in acetone, wherein the concentration of polymethyl methacrylate is 35-65 mg/mL; in the dipping and pulling process, the pulling speed is controlled to be 0.5-1.5 mm/s, the dipping and pulling are carried out for 3-4 times, and the mixture is baked for 40 minutes at 100 ℃ after the dipping and pulling.
Further, in the step (5), a gate electrode is prepared on the PMMA insulating layer by using a vacuum thermal evaporation method, specifically, the gate electrode is prepared by using alumina as a mask, and the thermal evaporation current is controlled to be 40-50A, the thermal evaporation voltage is controlled to be 2.5-5.5V, and the gate electrode of the prepared thin film transistor is a metal aluminum electrode.
Further, controlling the finally obtained double semiconductor layers of the thin film transistor to be indium aluminum zinc oxide thin films with the thickness of 40-70 nm; the insulating layer is a polymethyl methacrylate film with the thickness of 200-260 nm; the source electrode, the drain electrode and the gate electrode are metal aluminum films with the thickness of 70-90 nm.
The thin film transistor with the double semiconductor layers is prepared by the preparation method of the homogeneous double semiconductor layer thin film transistor with low temperature and low cost.
Compared with the prior art, the technical effects created by the invention are as follows:
(1) The invention takes a homogeneous double-layer film material formed by indium-aluminum-zinc oxide as a semiconductor layer, takes an organic polymethyl methacrylate (PMMA) film material as an insulating layer, takes an aluminum film as a source electrode, a drain electrode and a gate electrode, and prepares a Thin Film Transistor (TFT) with a top gate coplanar structure on a common glass substrate.
(2) In the invention, the homogeneous double semiconductor layer is prepared at low temperature (room temperature) by means of radio frequency magnetron sputtering, first of all, the first layer (directly in contact with the glass substrate) constituting the homogeneous double semiconductor layer is prepared, which involves a lower partial pressure of oxygen (0-3.5X 10) during the deposition process -2 Pa), the first semiconductor layer has high carrier concentration, so that the high on-state current and the high (more than or equal to 1 cm) of the device are ensured 2 Vs); subsequently, a second layer (overlying the first semiconductor layer and in contact with the source and drain electrodes) is prepared, constituting a homosemiconductor layer, which involves a higher partial pressure of oxygen (5.5-12X 10) during deposition -2 Pa), the second semiconductor layer has low carrier concentration, and low off-state current of the device can be realized, so that low energy consumption of the device is ensured.
(3) The preparation method based on the current homogeneous double-semiconductor-layer device has the following advantages:
(1) the invention can realize the accurate regulation and control of the carrier concentration in the semiconductor layer, reduce off-state current on the premise of not sacrificing mobility, does not need extra process to regulate and control the carrier concentration, simplify the step, reduce the cost;
(2) in the preparation process, the development of a double-semiconductor layer device can be realized by changing the oxygen partial pressure in the sputtering process on the basis of one target, and compared with a device for preparing a plurality of semiconductor layers based on a plurality of targets, the cost is further reduced;
(3) according to the invention, the homogeneous double semiconductor layer is prepared at room temperature, high-temperature annealing or high-temperature treatment similar to solution film forming is not needed in the preparation process, the development requirement of flexible display is met, the technical scheme for preparing the insulating layer at low temperature by using the solution method can be suitable for the flexible substrate, and the problem that the flexible substrate is difficult to be compatible due to the fact that higher processing temperature (more than or equal to 150 ℃) is involved in the high-temperature annealing process at present is solved.
(4) The insulating layer is prepared at low temperature (100 ℃) by adopting a dip-coating process of a low-cost sol-gel method, and because the insulating layer covers the semiconductor layer and the source and drain electrodes (a top gate structure different from a bottom gate structure which is commonly used at present is adopted), the contact between the semiconductor layer and the atmosphere is prevented, extra passivation treatment is not needed to be carried out on a device, the cost is further reduced, and the problems that the performance of the semiconductor layer is deteriorated due to moisture and oxygen in the atmosphere when the bottom gate structure is usually adopted at present and the semiconductor layer is exposed in the atmosphere are solved; compared with the method for preparing the insulating layer by the magnetron sputtering method, the technical scheme of the dip-coating process low-temperature (100 ℃) preparation by the low-cost sol-gel method greatly reduces the cost.
(5) The electrode has the advantages of low resistivity, good flatness, proper work function and the like, is beneficial to reducing RC signal delay between the gate electrode and the source electrode and between the gate electrode and the drain electrode, and can form good ohmic contact with a semiconductor layer. The invention finally obtains higher mobility (more than or equal to 1 cm) 2 Vs), and lower off-state current (< 10) -9 A) The top gate structure of the double-semiconductor-layer thin film transistor is homogeneous.
(6) The method has the advantages of simple operation, environment-friendly steps, low material price and easy storage of device samples (difficult influence by the environment).
(4) The invention provides a feasible scheme for preparing the oxide thin film transistor with low off-state current and high mobility at low temperature and low cost.
Drawings
FIG. 1 is a schematic diagram of a thin film transistor structure with dual semiconductor layers
FIG. 2 is a schematic diagram of a thin film transistor structure having a single semiconductor layer
Fig. 3 is a graph showing transfer characteristics of the thin film transistor based on the indium aluminum zinc oxide dual semiconductor layer obtained in example 1.
Fig. 4 is a graph showing transfer characteristics of the thin film transistor based on the indium aluminum zinc oxide dual semiconductor layer obtained in example 2.
Fig. 5 is a graph showing transfer characteristics of the thin film transistor based on the double semiconductor layer of indium aluminum zinc oxide obtained in example 3.
Detailed Description
The technical solution of the present invention is further defined below with reference to the specific embodiments, but the scope of the claims is not limited to the description.
Example 1
A low-temperature low-cost double-semiconductor layer thin film transistor is shown in figure 1. A TFT with a top gate coplanar structure is prepared by using glass as a substrate, an indium aluminum zinc oxide film as a semiconductor layer, an organic PMMA film as an insulating layer and an aluminum film as a source electrode, a drain electrode and a gate electrode, and is prepared by the following method:
(1) Sputtering on a cleaned glass substrate for 16 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of 0Pa and the argon working gas pressure of 0.5Pa based on an indium aluminum zinc oxide target to obtain a first layer semiconductor layer, wherein the purity of the indium aluminum zinc oxide target is 99.99%, and the molar ratio of indium to aluminum to zinc is indium: aluminum: zinc = 1;
(2) Based on an indium aluminum zinc oxide target at 7.5X 10 -2 Sputtering the first semiconductor layer obtained in the step (1) for 4 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of Pa and the argon working pressure of 0.5Pa to obtain a second semiconductor layer and obtain an indium-aluminum-zinc oxide double semiconductor layer;
(3) Preparing a metal aluminum thin film with the thickness of 64nm as a source electrode and a drain electrode on the semiconductor layer by using an alumina mask with the width-length ratio of 500 mu m/100 mu m, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.8V, and enabling the source electrode and the drain electrode of the finally obtained thin film transistor to be metal aluminum electrodes;
(4) Immersing the semiconductor layer containing the source electrode layer and the drain electrode layer obtained in the step (3) into a PMMA acetone precursor solution, placing the semiconductor layer in an oven at the temperature of 100 ℃ for baking for 40min after the semiconductor layer is subjected to pull coating at the speed of 1.0mm/s, and repeating the pull coating to bake for 3 times to form an organic PMMA film with the thickness of 240nm as an insulating layer; the PMMA acetone precursor solution is prepared by dissolving PMMA powder of Sigma-Aldrich company in an acetone solvent and stirring to obtain a PMMA acetone precursor solution with the concentration of 50 mg/mL;
(5) And (3) preparing a 70nm thick metal aluminum film serving as a gate electrode by using an alumina mask and alumina as a mask on the insulating layer obtained in the step (4) by adopting a vacuum thermal evaporation method, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.8V, and using the gate electrode of the prepared thin film transistor as a metal aluminum electrode to obtain the thin film transistor with the indium-aluminum-zinc oxide double semiconductor layer.
In this example, the transfer curve of a TFT device based on an indium aluminum zinc oxide dual semiconductor layer is shown in fig. 3. It can be shown that the device has a high saturation mobility of 2.06cm 2 Vs and lower off-state current (10) -9 A)。
Example 2
A low-temperature low-cost double-semiconductor layer thin film transistor is shown in figure 1. A TFT with a top gate coplanar structure is prepared by using glass as a substrate, an indium aluminum zinc oxide film as a semiconductor layer, an organic PMMA film as an insulating layer and an aluminum film as a source electrode, a drain electrode and a gate electrode, and is prepared by the following method:
(1) Based on an indium aluminum zinc oxide target, sputtering the cleaned glass substrate for 20 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of 0Pa and the argon working gas pressure of 0.5Pa to obtain a first layer semiconductor layer, wherein the purity of the indium aluminum zinc oxide target is 99.99%, and the molar ratio of indium to aluminum to zinc is indium: aluminum: zinc = 1;
(2) Based on an indium aluminum zinc oxide target at 5.5X 10 -2 Sputtering the first semiconductor layer obtained in the step (1) for 20 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of Pa and the argon working pressure of 0.5Pa to obtain a second semiconductor layer and obtain an indium-aluminum-zinc oxide double semiconductor layer;
(3) Preparing a 75 nm-thick metal aluminum film on the semiconductor layer by using an alumina mask as a source electrode and a drain electrode, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.7V, and enabling the source electrode and the drain electrode of the finally obtained thin film transistor to be metal aluminum electrodes;
(4) Immersing the semiconductor layer containing the source electrode layer and the drain electrode layer obtained in the step (3) into a PMMA acetone precursor solution, placing the semiconductor layer in an oven at the temperature of 100 ℃ for baking for 40min after the semiconductor layer is subjected to pull coating at the speed of 1.0mm/s, and repeating the pull coating to bake for 3 times to form an organic PMMA film with the thickness of 240nm as an insulating layer; the PMMA acetone precursor solution is prepared by dissolving PMMA powder of Sigma-Aldrich company in an acetone solvent and stirring to obtain a PMMA acetone precursor solution with the concentration of 50 mg/mL;
(5) And (5) preparing a 75 nm-thick metal aluminum film serving as a gate electrode by using an alumina mask and alumina as a mask on the insulating layer obtained in the step (4) by adopting a vacuum thermal evaporation method, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.7V, and preparing a metal aluminum electrode serving as the gate electrode of the prepared thin film transistor to obtain the thin film transistor with the indium-aluminum-zinc oxide double semiconductor layer.
In this example, the transfer curve of the TFT device based on the double semiconductor layer of indium aluminum zinc oxide is shown in fig. 4. It can be shown that the device has a high saturation mobility of 1.63cm 2 Vs, lower off-state current (<10 -9 A)。
Example 3
A low-temperature low-cost double-semiconductor layer thin film transistor is shown in figure 1. The TFT with the top gate coplanar structure is prepared by using glass as a substrate, an indium aluminum zinc oxide film as a semiconductor layer, an organic PMMA film as an insulating layer and an aluminum film as a source electrode, a drain electrode and a gate electrode, and is prepared by the following method:
(1) Based on an indium aluminum zinc oxide target at 3.5X 10 -2 Sputtering the cleaned glass substrate for 40 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of Pa and the argon working pressure of 0.5Pa to obtain a first layer of semiconductor layer, wherein the purity of the indium aluminum zinc oxide target is 99.99 percent, and the molar ratio of indium aluminum zinc is indium: aluminum: zinc = 1;
(2) Based on an indium-aluminium-zinc oxide target at 12X 10 -2 Sputtering the first semiconductor layer obtained in the step (1) for 12 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of Pa and the argon working pressure of 0.5Pa to obtain a second semiconductor layer and obtain an indium-aluminum-zinc oxide double semiconductor layer;
(3) Preparing a 75 nm-thick metal aluminum film on the semiconductor layer by using an alumina mask as a source electrode and a drain electrode, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.7V, and enabling the source electrode and the drain electrode of the finally obtained thin film transistor to be metal aluminum electrodes;
(4) Immersing the semiconductor layer containing the source electrode layer and the drain electrode layer obtained in the step (3) into a PMMA acetone precursor solution, placing the semiconductor layer in an oven at the temperature of 100 ℃ for baking for 40min after the semiconductor layer is subjected to pull coating at the speed of 1.0mm/s, and repeating the pull coating to bake for 3 times to form an organic PMMA film with the thickness of 240nm as an insulating layer; the PMMA acetone precursor solution is prepared by dissolving PMMA powder of Sigma-Aldrich company in an acetone solvent and stirring to obtain a PMMA acetone precursor solution with the concentration of 50 mg/mL;
(5) And (3) preparing a 75 nm-thick metal aluminum film serving as a gate electrode by using an aluminum oxide mask as an auxiliary material and aluminum oxide as a mask to prepare the gate electrode on the insulating layer obtained in the step (4) by adopting a vacuum thermal evaporation method, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.7V, and using the gate electrode of the prepared thin film transistor as a metal aluminum electrode to obtain the thin film transistor with the indium-aluminum-zinc oxide double semiconductor layer.
In this example, the transfer curve of the TFT device based on the double semiconductor layer of indium aluminum zinc oxide is shown in fig. 5. It can be concluded that the device has a width of 1.86cm 2 Saturated mobility of/Vs and<10 -9 off-state current of a.
Comparative example 1
A single semiconductor layer thin film transistor is shown in figure 2. A TFT with a top gate coplanar structure is prepared by using glass as a substrate, an indium aluminum zinc oxide film as a semiconductor layer, an organic PMMA film as an insulating layer and an aluminum film as a source electrode, a drain electrode and a gate electrode, and is prepared by the following method:
(1) Sputtering on a cleaned glass substrate for 20 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of 0Pa and the argon working gas pressure of 0.5Pa based on an indium aluminum zinc oxide target to obtain an indium aluminum zinc oxide semiconductor layer, wherein the purity of the indium aluminum zinc oxide target is 99.99%, the indium aluminum zinc molar ratio is indium: aluminum: zinc = 1;
(2) Preparing a 76 nm-thick metal aluminum film on the semiconductor layer by using an aluminum oxide mask with the width-length ratio of 500 mu m/100 mu m as a source electrode and a drain electrode, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 4.7V, and enabling the source electrode and the drain electrode of the finally obtained thin film transistor to be metal aluminum electrodes;
(3) Immersing the semiconductor layer containing the source electrode layer and the drain electrode layer obtained in the step (2) into a PMMA acetone precursor solution, carrying out lifting coating at the speed of 1.0mm/s, then placing the semiconductor layer in a drying oven at the temperature of 100 ℃ for baking for 40min, and repeating the lifting coating to carry out baking operation for 3 times to form an organic PMMA film with the thickness of 240nm to serve as an insulating layer; the PMMA acetone precursor solution is prepared by dissolving PMMA powder of Sigma-Aldrich company in an acetone solvent and stirring to obtain a PMMA acetone precursor solution with the concentration of 50 mg/mL;
(4) And (4) preparing a 75 nm-thick metal aluminum film serving as a gate electrode by using an alumina mask and alumina as a mask on the insulating layer obtained in the step (3) by adopting a vacuum thermal evaporation method, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 5.1V, and taking the gate electrode of the prepared thin film transistor as a metal aluminum electrode to obtain the thin film transistor with the indium-aluminum-zinc oxide double semiconductor layer.
In this comparative example, the thin film transistor device of the indium aluminum zinc oxide single semiconductor layer to which oxygen partial pressure was not applied during sputtering did not show the electrical properties of the device.
Comparative example 2
A single semiconductor layer thin film transistor is shown in figure 2. A TFT with a top gate coplanar structure is prepared by using glass as a substrate, an indium aluminum zinc oxide film as a semiconductor layer, an organic PMMA film as an insulating layer and an aluminum film as a source electrode, a drain electrode and a gate electrode, and is prepared by the following method:
(1) Based on an indium aluminum zinc oxide target at 5.5X 10 -2 And (2) sputtering the cleaned glass substrate for 20 minutes by a radio frequency magnetron sputtering method under the oxygen partial pressure of Pa and the argon working pressure of 0.5Pa to obtain the indium-aluminum-zinc oxide semiconductor layer, wherein the purity of the indium-aluminum-zinc oxide target is 99.99%, and the molar ratio of indium to aluminum to zinc is indium: aluminum: zinc = 1;
(2) Preparing a 79.5nm thick metal aluminum film on the semiconductor layer by using an aluminum oxide mask with the width-length ratio of 500 mu m/100 mu m as a source electrode and a drain electrode, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 5.5V, and finally obtaining the metal aluminum electrode of both the source electrode and the drain electrode of the thin film transistor;
(3) Immersing the semiconductor layer containing the source electrode layer and the drain electrode layer obtained in the step (2) into a PMMA acetone precursor solution, placing the semiconductor layer in an oven at the temperature of 100 ℃ for baking for 40min after the semiconductor layer is subjected to pull coating at the speed of 1.0mm/s, and repeating the pull coating to bake for 3 times to form an organic PMMA film with the thickness of 240nm as an insulating layer; the PMMA acetone precursor solution is prepared by dissolving PMMA powder of Sigma-Aldrich company in an acetone solvent and stirring to obtain a PMMA acetone precursor solution with the concentration of 50 mg/mL;
(4) And (4) preparing a 70 nm-thick metal aluminum film serving as a gate electrode by using an alumina mask and alumina as a mask on the insulating layer obtained in the step (3) by adopting a vacuum thermal evaporation method, controlling the thermal evaporation current to be 50A and the thermal evaporation voltage to be 3.9V, and taking the gate electrode of the prepared thin film transistor as a metal aluminum electrode to obtain the thin film transistor with the indium-aluminum-zinc oxide double semiconductor layer.
In this comparative example, the saturation mobility of the thin film transistor device having an indium aluminum zinc oxide single semiconductor layer was 6.87 × 10 -3 cm 2 Vs off-state current<10 -9 A, shows that the mobility of the conventional single semiconductor layer is greatly sacrificed while the off-state current is reduced.
The saturation mobility and off-state current of the thin film transistors having the two semiconductor layers obtained in examples 1 and 2 were compared with those of the thin film transistors having the single semiconductor layer obtained in comparative examples 1 and 2:
the tabulated data shows that the conventional single semiconductor layer structure (comparative example 2) has a reduced off-state current and a reduced mobility, examples 1, 2, and 3 employ a dual semiconductor layer structure,the mobility is not sacrificed while low off-state current can be ensured by the double semiconductor layer structure. The data comparison shows that under the condition of ensuring that the oxygen partial pressure of a certain layer is consistent, the examples have obvious improvement compared with the comparative example: the oxygen partial pressure of comparative example 1 was identical to that of the first semiconductor layer of example 1 (both at 0 Pa), comparative example 1 did not exhibit device performance, and the oxygen partial pressure of 7.5 × 10 was added to example 1 -2 Pa of the second semiconductor layer, device appearance characteristics and lower off-state current (10) -9 A) And higher saturation mobility (2.06 cm) 2 Vs); the oxygen partial pressure of comparative example 2 was the same as that of the second semiconductor layer of example 2 (both were 5.5X 10) -2 Pa) of the total weight of the composition, comparative example 2 although having a low off-state current (<10 -9 A) But only 6.87 x 10 at the expense of saturation mobility of the device -3 cm 2 Whereas example 2, in which the first semiconductor layer having an oxygen partial pressure of 0Pa was added, exhibited not only a low off-state current (<10 -9 A) And has high saturation mobility (1.63 cm) 2 Vs). The data can show that the invention provides a feasible scheme for preparing the oxide thin film transistor with high performance and low energy consumption at low cost.
Finally, it should be noted that the above embodiments are merely representative examples of the present invention. Obviously, the technical solution of the present invention is not limited to the above-described embodiments, and many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (9)
1. A method for preparing a low-temperature low-cost homogeneous double-semiconductor-layer thin film transistor is characterized by comprising the following steps of:
(1) Based on indium aluminum zinc oxide target, in the range of 0-3.5X 10 -2 Sputtering a film on the cleaned glass substrate by a radio frequency magnetron sputtering method under the oxygen partial pressure of Pa and the argon working pressure of 0.5-1.0 Pa to obtain a first semiconductor layer;
(2) Based on an indium aluminum zinc oxide target at 5.5X 10 -2 ～12×10 -2 Pa oxygen partial pressure and 0.5 to ESputtering to form a film on the first semiconductor layer obtained in the step (1) by a radio frequency magnetron sputtering method under the argon working pressure of 1.0Pa to obtain a second semiconductor layer and form a double-semiconductor-layer structure;
(3) Combining a mask, and preparing a source electrode and a drain electrode on the double-semiconductor layer obtained in the step (2) by using a vacuum thermal evaporation method;
(4) Preparing a PMMA insulating layer on the double semiconductor layer comprising the source electrode and the drain electrode by using an organic solution dissolved with polymethyl methacrylate by adopting a dip-coating process;
(5) And combining the mask, and preparing a gate electrode on the PMMA insulating layer by using a vacuum thermal evaporation method to obtain the thin film transistor with the double semiconductor layers.
2. The method for preparing a low-temperature low-cost homogeneous double semiconductor layer thin film transistor according to claim 1, wherein in the step (1), the purity of the target indium aluminum zinc oxide used is more than 99.99%.
3. The method for preparing a low-temperature low-cost homogeneous double semiconductor layer thin film transistor according to claim 1, wherein the step (1) is carried out by using an indium aluminum zinc oxide target with an indium aluminum zinc molar ratio of indium: aluminum: zinc = 1.
4. The method for manufacturing a low-temperature low-cost homogeneous double semiconductor layer thin film transistor according to claim 1, wherein the sputtering in the steps (1) and (2) is performed for 4 to 40 minutes.
5. The preparation method of the thin film transistor is characterized in that the method adopting vacuum thermal evaporation in the step (3) comprises the following specific operation steps: and preparing a source electrode and a drain electrode by using aluminum oxide as a mask, controlling the thermal evaporation current to be 40-50A and the thermal evaporation voltage to be 2.5-5.5V, and finally obtaining the source electrode and the drain electrode of the thin film transistor which are both metal aluminum electrodes.
6. The method for preparing the low-temperature low-cost homogeneous double semiconductor layer thin film transistor according to claim 1, wherein the organic solution dissolved with polymethyl methacrylate in the step (4) is prepared by dissolving polymethyl methacrylate in the organic solution, wherein the concentration of the polymethyl methacrylate is 35-65 mg/mL, and the organic solvent is acetone; in the dipping and pulling process, the pulling speed is controlled to be 0.5-1.5 mm/s, the dipping and pulling are carried out for 3-4 times, and the mixture is baked for 40 minutes at 100 ℃ after the dipping and pulling.
7. The method for preparing a low-temperature low-cost homogeneous double-semiconductor layer thin film transistor according to claim 1, wherein a gate electrode is prepared on the PMMA insulating layer by using a vacuum thermal evaporation method in the step (5), specifically, the gate electrode is prepared by using aluminum oxide as a mask, the thermal evaporation current is controlled to be 40-50A, the thermal evaporation voltage is controlled to be 2.5-5.5V, and the gate electrode of the prepared thin film transistor is a metal aluminum electrode.
8. The method for preparing the homogeneous double-semiconductor-layer thin film transistor at low temperature and low cost according to claim 1, wherein the finally obtained double semiconductor layers of the thin film transistor are controlled to be indium aluminum zinc oxide thin films with the thickness of 40-70 nm; the insulating layer is a polymethyl methacrylate film with the thickness of 200-260 nm; the source electrode, the drain electrode and the gate electrode are metal aluminum films with the thickness of 70-90 nm.
9. The thin film transistor with the double semiconductor layers is prepared by the method for preparing the low-temperature low-cost homogeneous double semiconductor layer thin film transistor as claimed in any one of claims 1 to 8.
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