CN115938439A - Nor Flash without inductive capacity expansion, sensing circuit and electronic equipment - Google Patents
Nor Flash without inductive capacity expansion, sensing circuit and electronic equipment Download PDFInfo
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- CN115938439A CN115938439A CN202310016992.6A CN202310016992A CN115938439A CN 115938439 A CN115938439 A CN 115938439A CN 202310016992 A CN202310016992 A CN 202310016992A CN 115938439 A CN115938439 A CN 115938439A
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Abstract
The invention relates to the technical field of integrated circuits, and particularly discloses a Nor Flash without inductive capacity expansion, a sensing circuit and electronic equipment, wherein the sensing circuit comprises: a plurality of open drain pads respectively connected to different sub-chips; a first end of the pull-up resistor is connected with the output ends of all the open-drain pads, and a second end of the pull-up resistor is connected with a power supply voltage; a first end of the transistor is connected with a first end of the pull-up resistor, a second end of the transistor is grounded, and a third end of the transistor is connected with the main chip; the input end of the NOT gate is connected with the first end of the pull-up resistor; the output end of the NAND gate of the selection control end of the first selector is connected, and the input end of the first selector inputs a high-level signal; the trigger input end of the register is connected with the output end of the first selector, and the output end of the register is connected with the other input end of the first selector; the sensing circuit can realize the online monitoring of the running states of all the memory chips without actively returning the states of all the memory chips.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a Nor Flash with noninductive capacity expansion, a sensing circuit and electronic equipment.
Background
The Nor Flash memory with the serial interface is a commonly used data storage component, and when a large capacity and a small package size are required, multiple Flash chips are generally adopted for stacking and packaging to enlarge the capacity, for example, two chips with the size of 256M can be changed into 512M Flash packaging chips. The adoption of the three-dimensional overlapping sealing scheme can reduce the packaging area to meet the requirement of miniaturization.
In order to solve the problem of accurately accessing different chips during overlapping sealing, the conventional Flash memory generally adopts a non-inductive capacity expansion mode to perform Nor Flash overlapping sealing to form a sealing sheet, the whole sealing sheet is not different from a large-capacity chip when viewed from the outside, only has one chip selection signal input end, and the applicable function is also not different from that of a common capacity expansion chip.
When an erase or program command is performed on Nor Flash, an external host needs to read a status register to check whether the Nor Flash is erased or programmed, and for the existing Nor Flash without inductive capacity expansion, the status register needs to be returned to the status by a memory chip which is being programmed and erased. However, in the reading process, if the Suspend instruction received by the memory chip originally executing the erase operation suspends and receives the program instruction, the memory chip cannot return the status to the status register, and the external host cannot accurately know whether the Nor Flash completes the erase or program operation.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The application aims to provide the Nor Flash with the non-inductive capacity expansion function, the sensing circuit and the electronic equipment, so that the running states of all the memory chips can be monitored on line under the condition that each memory chip does not need to return to the state actively.
In a first aspect, the present application provides a Nor Flash sensing circuit without inductive expansion, where the Nor Flash includes a main chip and a plurality of sub-chips, and the Nor Flash sensing circuit includes:
a plurality of open drain pads respectively connected to different sub-chips, each for outputting a low level signal when the corresponding sub-chip is in an erased or programmed state;
a first end of the pull-up resistor is connected with the output ends of all the open-drain pads, and a second end of the pull-up resistor is connected with a power supply voltage;
a transistor, the first end of which is connected with the first end of the pull-up resistor, the second end of which is grounded, and the third end of which is connected with the main chip and is used for monitoring the erasing state signal of the main chip;
the input end of the NOT gate is connected with the first end of the pull-up resistor;
the selection control end of the first selector is connected with the output end of the NOT gate, and the input end of the first selector inputs a high-level signal;
and the trigger input end of the register is connected with the output end of the first selector, the output end of the register is used for outputting a Nor Flash busy state signal, and the register is connected with the other input end of the first selector.
The Nor Flash sensing circuit capable of carrying out non-inductive capacity expansion monitors the execution states of the secondary chip and the main chip on line based on the open-drain pad and the transistor, and when the main chip or the secondary chip executes erasing or programming actions, a low level can be input into the NOT gate so that the first selector outputs a high level to trigger the register to generate a corresponding busy state signal.
The Nor Flash sensing circuit with the non-inductive capacity expansion function further comprises a follower, and the first end of the pull-up resistor is connected with the input end of the NOT gate through the follower.
The follower can buffer (buf) input signals, can prevent the change process of level signals, can perform primary filtering on the signals, and improves the anti-interference capability of the whole sensing circuit.
The Nor Flash sensing circuit with the non-inductive capacity expansion function further comprises a filter, and the follower is connected with the input end of the NOT gate through the filter.
The Nor Flash sensing circuit with the non-inductive capacity expansion function further comprises a first rising edge detection circuit, a second rising edge detection circuit and a second selector, wherein the output end of the first selector is connected with one input end of the second selector so as to be connected with the trigger input end of the register through the output end of the second selector, and a low level signal is input to the other input end of the second selector;
the input end of the first rising edge detection circuit is connected with the filter, the output end of the first rising edge detection circuit is connected with the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is connected with the selection control end of the second selector.
The Nor Flash sensing circuit with the non-inductive capacity expansion function further comprises a judging circuit, wherein the input end of the judging circuit is connected with the output end of the second rising edge detection circuit, and the output end of the judging circuit is used for outputting an error state signal.
The Nor Flash sensing circuit with non-inductive capacity expansion is characterized in that the first rising edge detection circuit and the second rising edge detection circuit are both delay signal generation circuits triggered based on rising edges.
The Nor Flash sensing circuit without inductive capacity expansion is characterized in that the register is a D trigger.
The Nor Flash sensing circuit without sensing and capacity expansion is characterized in that the transistor is an NMOS transistor.
In a second aspect, the application further provides a non-inductive capacity-expanding Nor Flash, where the non-inductive capacity-expanding Nor Flash includes a main chip and a plurality of sub-chips, which are stacked and sealed, and a sensing circuit of the non-inductive capacity-expanding Nor Flash provided in the first aspect is arranged in the main chip.
According to the non-inductive capacity-expansion Nor Flash, the sensing circuit of the non-inductive capacity-expansion Nor Flash provided by the first aspect is installed in the main chip, so that an external host can accurately know whether a storage chip executing an erasing or programming action exists in the Nor Flash or not based on a busy state signal output by the main chip.
In a third aspect, the application further provides an electronic device, where the electronic device includes the Nor Flash with noninductive capacity expansion provided in the second aspect.
From the above, the application provides a Nor Flash with non-inductive capacity expansion, a sensing circuit and an electronic device, wherein the sensing circuit monitors the execution states of a secondary chip and a main chip on line based on an open-drain pad and a transistor, when the main chip or the secondary chip executes an erasing or programming action, a low level can be input to a not gate so that a first selector outputs a high level to trigger a register to generate a corresponding busy state signal, the online monitoring of the operation states of all memory chips can be realized without actively returning the state of each memory chip, the state viewing efficiency can be effectively improved, and the problem that the memory chips fail to return to the state due to the fact that the states need to be switched is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a Nor Flash sensing circuit with no sense of expansion according to some embodiments of the present application.
Fig. 2 is a schematic structural diagram of a Nor Flash sensing circuit according to still other embodiments of the present application.
Fig. 3 is a schematic structural diagram of a Nor Flash sensing circuit without sensing capacity expansion according to another embodiment of the present application.
Fig. 4 is a schematic structural diagram of a Nor Flash sensing circuit with no inductive capacity expansion according to still other embodiments of the present application.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 1. opening a leakage pad; 2. a pull-up resistor; 3. a transistor; 4. a NOT gate; 5. a first selector; 6. a register; 7. a follower; 8. a filter; 9. a first rising edge detection circuit; 10. a second rising edge detection circuit; 11. a second selector; 12. a judgment circuit; 301. a processor; 302. a memory; 303. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; may be mechanically, electrically or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
In a first aspect, referring to fig. 1, some embodiments of the present application provide a Nor Flash sensing circuit with no inductive expansion, where the Nor Flash includes a main chip and a plurality of sub-chips, and the Nor Flash sensing circuit includes:
a plurality of open drain pads 1 respectively connected to different sub-chips, each for outputting a low level signal when the corresponding sub-chip is in an erased or programmed state;
a first end of the pull-up resistor 2 is connected with the output ends of all the open-drain pads 1, and a second end of the pull-up resistor is connected with a power supply voltage;
a transistor 3, a first end of which is connected with the first end of the pull-up resistor 2, a second end of which is grounded, and a third end of which is connected with the main chip and is used for monitoring the erasing and writing state signal of the main chip;
the input end of the NOT gate 4 is connected with the first end of the pull-up resistor 2;
the output end of the NAND gate 4 of the selection control end of the first selector 5 is connected, and the input end of the first selector inputs a high level signal;
and a register 6, the trigger input end of which is connected with the output end of the first selector 5, the output end of which is used for outputting a Nor Flash busy state signal, and the register is connected with the other input end of the first selector 5.
It should be understood that the Nor Flash sensing circuit without sensing and capacity expansion according to the embodiment of the present application is installed in a main chip, and is used for comprehensively reflecting whether all memory chips (including the main chip and a secondary chip) have a memory chip in an erasable state, but at the same time, the embodiment of the present application does not limit the installation positions of the main chip and the secondary chip, and therefore, the memory chip installed with the sensing circuit may also be considered as the main chip, and the remaining memory chips are considered as the secondary chips.
Specifically, the Nor Flash with non-inductive capacity expansion is integrated into an integral chip, the PAD is a pin of a silicon chip, and is packaged in the Nor Flash, and the open drain refers to open drain output, which can switch a level state according to an operating state of a corresponding memory chip (mainly referred to as a sub-chip in the embodiment of the present application); in the embodiment of the present application, the open drain PAD1 refers to a PAD terminal connected to an open drain output of the secondary chip; in the embodiment of the present application, when the sub-chip performs the erase or program operation, the corresponding open drain pad1 is at a low level (i.e. 0), otherwise it is at a high level (i.e. 1).
More specifically, the third terminal of the transistor 3 is used for monitoring the erasure status signal of the main chip, so that the conduction state between the first terminal and the second terminal of the transistor 3 is controlled based on the erasure status signal of the main chip, in the embodiment of the present application, when the main chip performs an erasing or programming action, the first terminal and the second terminal of the transistor 3 are conducted, so that the transistor 3 can be regarded as a switching tube for automatically switching the conduction state based on the operation state of the main chip; in the embodiment of the present application, the transistor 3, the pull-up resistor 2 and the supply voltage constitute an open-drain output with respect to the main chip.
More specifically, the output terminal of the not gate 4 is connected to the selection control terminal of the first selector 5, and two input terminals of the first selector 5 are respectively connected to the output terminal of the register 6 and a high-level signal (i.e. 1' b1 in the figure), i.e. the output state of the first selector 5 is changed by changing the output state of the not gate 4; in the embodiment of the present application, the input terminal 1 of the first selector 5 is connected to a high level signal, so that when the not gate 4 outputs a high level, the first selector 5 also outputs a high level.
More specifically, in the embodiment of the present application, there are one or more sub-chips, and only one schematic structure of the open drain pad1 is shown in the drawing, it should be understood that, if there are multiple sub-chips, the output terminals of the open drain pads 1 of the multiple sub-chips are connected in parallel.
More specifically, when the main chip performs an erasing or programming action, the transistor 3 is turned on, so that the point a in fig. 1 is pulled down to a low level; similarly, when the main chip performs the erasing or programming operation, the open-drain pad1 can pull down the point a in fig. 1 to a low level, so that in the whole Nor Flash without sensing capacity expansion, as long as the memory chip performs the erasing or programming operation, the voltage at the point a is in a low level state, so that the output of the not gate 4 is a high level, and further, the first selector 5 outputs a high level to trigger the register 6 to output a corresponding busy state signal.
More specifically, when all the memory chips are not performing the erasing and programming operations, the transistor 3 and the open drain pad1 are both turned off, the voltage at a in fig. 1 is pulled up to a high level by the pull-up resistor 2 and the power supply voltage, so that the output of the not gate 4 is a low level, and further the first selector 5 switches the output to trigger the register 6 to output the corresponding busy state signal, and since the 0 terminal of the first selector 5 is connected to the output terminal of the register 6, the output of the first selector 5 is gradually pulled down to a low level to change the output of the register 6.
More specifically, the Busy status signal (hereinafter abbreviated as Busy) is used to reflect whether the whole Nor Flash exists in the memory chip and is performing the erasing or programming action, in this embodiment, busy =1 (high level) indicates that the Nor Flash exists in the memory chip and is performing the erasing or programming action, and Busy =0 (low level) indicates that the Nor Flash does not exist in the memory chip and is performing the erasing or programming action, so that the sensing circuit does not increase the power consumption when the Nor Flash is in the idle state.
More specifically, in the Nor Flash without sensing the Flash, only one memory chip is generally used to perform the erasing or programming operation at the same time, and therefore, the embodiment of the present application can implement the whole Nor Flash erasing and writing operation sensing by using one sensing circuit.
The Nor Flash sensing circuit capable of carrying out non-inductive capacity expansion monitors the execution states of the secondary chip and the main chip on line based on the open-drain pad1 and the transistor 3, when the main chip or the secondary chip executes erasing or programming actions, a low level can be input into the NOT gate 4 so that the first selector 5 outputs a high level to trigger the register 6 to generate a corresponding busy state signal, the online monitoring of the running states of all the memory chips can be realized without actively returning the states of all the memory chips, the state checking efficiency can be effectively improved, and the problem that the memory chips fail to return the states due to the fact that the states of the memory chips need to be switched is solved.
In some preferred embodiments, referring to fig. 2, the Nor Flash sensing circuit without sensing capacity expansion further includes a follower 7, and a first end of the pull-up resistor 2 is connected to an input end of the nand gate 4 of the follower 7.
Specifically, the follower 7 is an in-phase buffer, and can buffer (buf) the input signal, so that the level signal can be prevented from changing too fast, and meanwhile, the signal can be subjected to preliminary filtering, so that the anti-interference capability of the whole sensing circuit is improved.
In some preferred embodiments, referring to fig. 2, the Nor Flash sensing circuit without sensing capacity further includes a filter 8, and the follower 7 is connected to the input terminal of the nand gate 4 of the filter 8.
Specifically, as shown in fig. 2, in the embodiment of the present application, the output end of the filter 8 is connected to the output end of the follower 7, the output end of the nand gate 4 of the output end of the filter 8 is connected, the filter 8 is used for filtering the glitch below a certain time period, so as to improve the stability of the whole sensing circuit, and the output accuracy of the busy state signal can be effectively ensured when the filter is used in cooperation with the follower 7.
In some preferred embodiments, referring to fig. 3, the Nor Flash sensing circuit with non-inductive capacity expansion further includes a first rising edge detection circuit 9, a second rising edge detection circuit 10, and a second selector 11, wherein an output terminal of the first selector 5 is connected to an input terminal of the second selector 11 to be connected to a trigger input terminal of the register 6 through an output terminal of the second selector 11, and another input terminal of the second selector 11 inputs a low level signal;
an input terminal of the first rising edge detection circuit 9 is connected to the filter 8, an output terminal of the first rising edge detection circuit 9 is connected to an input terminal of the second rising edge detection circuit 10, and an output terminal of the second rising edge detection circuit 10 is connected to a selection control terminal of the second selector 11.
Specifically, the memory chip may also be terminated accidentally when performing an erasing or programming action, and the sensing circuit of the embodiment of the present application adds the first rising edge detection circuit 9 and the second rising edge detection circuit 10 to perform error information acquisition; after the storage chip in Nor Flash finishes erasing or programming operation, a high level signal appears at a position a (the auxiliary chip is represented as an open-drain pad1 to output high voltage temporarily, and the main chip is represented as a transistor 3 to be cut off temporarily), nor Flash needs to wait for a certain time to perform the next erasing or programming action, during the period, the sensing circuit of the embodiment of the application utilizes the first rising edge detection circuit 9, the second rising edge detection circuit 10 and the second selector 11 to collect error information, and the process is as follows: when the memory chip finishes the erasing or programming action, a signal at the point a generates a rising edge to enter a high level signal, the first rising edge detection circuit 9 detects the rising edge and triggers the second rising edge detection circuit 10 to detect the signal at the point a, if the signal at the point a appears a square wave signal or falls to a low level and is pulled to a high level (an error execution action occurs) within a certain time (before the first rising edge detection circuit 9 is cut off), the second rising edge detection circuit 10 triggers the second selector 11 to switch and input a low level signal (1' b0 in the figure) based on the rising edge appearing at the point a for the second time so as to lock the output of the register 6, so that the Busy output of the register 6 is locked to be 0, and when the next memory chip executes the erasing or programming action, the Busy locked to be 0 can be known that an error occurs in the norflash operation, and thus the error information acquisition of norflash is realized.
More specifically, the input end of the first rising edge detection circuit 9 is connected to the filter 8, which can ensure that the rising edge detection process is a process of detecting based on the buffered and filtered input signal, and ensure that the rising edge capture is accurate.
In some preferred embodiments, referring to fig. 4, the Nor Flash sensing circuit without sensing capacity expansion further includes a determining circuit 12, an input terminal of the determining circuit 12 is connected to an output terminal of the second rising edge detecting circuit 10, and an output terminal of the determining circuit 12 is used for outputting an error state signal.
Specifically, in order to enable the external host to more directly know the Error information of Nor Flash, the sensing circuit in the embodiment of the present application adds the determining circuit 12 to the output end of the second rising edge detecting circuit 10, where the determining circuit 12 is configured to determine whether a difference between occurrence intervals of rising edges detected by the first rising edge detecting circuit 9 and the second rising edge detecting circuit 10 is smaller than a preset time window, and if the difference is smaller than the time window, it is determined that Nor Flash has an erroneous output, and output an Error state signal Error to 1, otherwise output to 0, so that the external host can sense whether an erasure or a programming action of Nor Flash has an accident according to the Error.
More specifically, in some other embodiments, the determining circuit 12 may further determine whether the program or erase operation has a problem according to whether a time interval between two rising edges is greater than a preset value when the Nor Flash performs a continuous program or continuous erase operation, and switch Error to 1 when the problem occurs.
In some preferred embodiments, the first rising edge detection circuit 9 and the second rising edge detection circuit 10 are both delay signal generation circuits triggered based on rising edges.
Specifically, the delay signal generating circuit is used for generating a delay signal according to the rising edge trigger of the clock, and in the embodiment of the present application, the delay signal is generated according to the level variation condition output by the filter 8, and the timing of generating the delay signal is the timing of the rising edge.
In some preferred embodiments, the register 6 is a D flip-flop.
Specifically, in the embodiment of the present application, the output terminal of the second selector 11 is connected to the D terminal of the D flip-flop, and the Q terminal of the D flip-flop outputs the Busy signal.
More specifically, the CP terminal of the D flip-flop may be connected to a CS # signal input from an external host.
In some preferred embodiments, the transistor 3 is an NMOS transistor.
Specifically, a first end of the transistor 3 is a drain electrode of an NMOS transistor, a second end of the transistor 3 is a source electrode of the NMOS transistor, and a third end of the transistor 3 is a gate electrode of the NMOS transistor; when the main chip executes the erasing or programming action, the grid electrode of the NMOS tube inputs high level, so that the source drain of the NMOS tube is conducted to pull down the point a to low level.
In a second aspect, some embodiments of the present application further provide a Nor Flash without inductive expansion, where the Nor Flash without inductive expansion includes a main chip and multiple sub-chips that are stacked and sealed, and a sensing circuit of the Nor Flash without inductive expansion provided in the first aspect is disposed in the main chip.
The non-inductive capacity-expansion Nor Flash provided by the embodiment of the application is provided with the non-inductive capacity-expansion Nor Flash sensing circuit provided by the first aspect in the main chip, so that an external host can accurately know whether a memory chip executing an erasing or programming action exists in the Nor Flash based on a busy state signal output by the main chip.
In a third aspect, some embodiments of the present application further provide an electronic device, where the electronic device includes the Nor Flash with noninductive capacity expansion provided in the second aspect.
Specifically, as shown in fig. 5, the electronic device of the embodiment of the present application includes: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and in communication with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 being Nor Flash providing the second aspect with noninductive expansion.
The processor 301 in the electronic device provided by the embodiment of the present application can obtain the Busy signal from the main chip in the memory 302 to determine whether there is a memory chip in Nor Flash that is performing an erasing or programming action.
To sum up, the embodiment of the present application provides a Nor Flash with non-inductive capacity expansion, a sensing circuit and an electronic device, wherein the sensing circuit monitors the execution states of a secondary chip and a primary chip on line based on an open-drain pad1 and a transistor 3, and when the primary chip or the secondary chip executes an erasing or programming action, a low level can be input to a not gate 4 so that a first selector 5 outputs a high level to trigger a register 6 to generate a corresponding busy state signal.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
What has been described above are merely some embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the inventive concept thereof, and these changes and modifications can be made without departing from the spirit and scope of the invention.
Claims (10)
1. The utility model provides a Nor Flash's of noninductive dilatation perception circuit, nor Flash of noninductive dilatation includes main chip and a plurality of vice chip of overlapping setting, its characterized in that, the perception circuit includes:
a plurality of open drain pads respectively connected to different sub-chips, each for outputting a low level signal when the corresponding sub-chip is in an erased or programmed state;
a first end of the pull-up resistor is connected with the output ends of all the open-drain pads, and a second end of the pull-up resistor is connected with a power supply voltage;
a transistor, the first end of which is connected with the first end of the pull-up resistor, the second end of which is grounded, and the third end of which is connected with the main chip and is used for monitoring the erasing state signal of the main chip;
the input end of the NOT gate is connected with the first end of the pull-up resistor;
the selection control end of the first selector is connected with the output end of the NOT gate, and the input end of the first selector inputs a high-level signal;
and the trigger input end of the register is connected with the output end of the first selector, the output end of the register is used for outputting a Nor Flash busy state signal, and the register is connected with the other input end of the first selector.
2. The Nor Flash sensing circuit of claim 1, wherein the Nor Flash sensing circuit further comprises a follower, and the first terminal of the pull-up resistor is connected to the input terminal of the not gate through the follower.
3. The Nor Flash sensing circuit of claim 2, wherein the Nor Flash sensing circuit further comprises a filter, and the follower is connected to the input terminal of the not gate through the filter.
4. The Nor Flash sensing circuit without sensing capacity expansion of claim 3, further comprising a first rising edge detection circuit, a second rising edge detection circuit and a second selector, wherein an output end of the first selector is connected with one input end of the second selector to be connected with the trigger input end of the register through an output end of the second selector, and the other input end of the second selector inputs a low level signal;
the input end of the first rising edge detection circuit is connected with the filter, the output end of the first rising edge detection circuit is connected with the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is connected with the selection control end of the second selector.
5. The Nor Flash sensing circuit with noninductive capacity expansion of claim 4, wherein the Nor Flash sensing circuit with noninductive capacity expansion further comprises a judgment circuit, an input end of the judgment circuit is connected with an output end of the second rising edge detection circuit, and an output end of the judgment circuit is used for outputting an error state signal.
6. The Nor Flash sensing circuit without sensing capacity expansion of claim 4 or 5, wherein the first rising edge detection circuit and the second rising edge detection circuit are both delay signal generation circuits based on rising edge triggering.
7. The Nor Flash sensing circuit of claim 1, wherein the register is a D flip-flop.
8. The Nor Flash sensing circuit of claim 1, wherein the transistor is an NMOS transistor.
9. A Nor Flash without inductive capacity expansion, which comprises a main chip and a plurality of secondary chips which are stacked and sealed, wherein the main chip is provided with a sensing circuit of the Nor Flash without inductive capacity expansion according to any one of claims 1 to 8.
10. An electronic device characterized in that the electronic device comprises Nor Flash with noninductive Flash as claimed in claim 9.
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