CN201017277Y - Action testing combine group buffer of embedded system - Google Patents
Action testing combine group buffer of embedded system Download PDFInfo
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- CN201017277Y CN201017277Y CNU2006201757448U CN200620175744U CN201017277Y CN 201017277 Y CN201017277 Y CN 201017277Y CN U2006201757448 U CNU2006201757448 U CN U2006201757448U CN 200620175744 U CN200620175744 U CN 200620175744U CN 201017277 Y CN201017277 Y CN 201017277Y
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Abstract
The utility model discloses a JTAG isolating circuit in an embedded system, which is connected to a processing unit and a logic chip with a JTAG interface, and comprises a monostable unit and a tristate output buffer, wherein, the tristate output buffer carries out buffered output of JTAG data and control signals between the processing unit and the logic chip with a JTAG interface; the monostable triggered input control pin of the monostable unit is connected to the processing unit, and the output control pin of the monostable unit is connected to the output enabling pin of the tristate output buffer. In the utility model, the tristate output buffer will be enabled only when the processing unit outputs a pulse signal, so that when the embedded system is used for the first time or if the processing unit of the embedded system fails, the tristate output buffer will be in high-impedance state, and thereby can avoid possible bus collision with a PC dock.
Description
Technical field
The utility model relates to embedded system, relates in particular to JTAG (JointTest Action Group, testing action the is united group) buffer circuit in a kind of embedded system.
Background technology
Some embedded system supports have the on-line loaded function of the logic chip of jtag interface, and provide (Personal Computer by PC, personal computer) machine loads the function that seat comes the load logic chip, so that can load the content that seat is revised logic chip, and the mistake of correction logic function by PC.
Processing unit in the embedded system and PC load the access conflict of seat to logic chip with jtag interface, the available technology adopting tristate output buffer makes up processing unit and has buffer circuit between the logic chip of jtag interface, keeps apart so that processing unit to the load path of the logic chip with jtag interface and PC loaded seat to the load path of the logic chip with jtag interface.A kind of example structure of tristate output buffer and place embedded system thereof as shown in Figure 1, the JTAG data of processing unit 110 and control signal are being connected to the logic chip 130 with jtag interface through behind the tristate output buffer 120, and JTAG data and control signal that PC loads seat also are connected to the logic chip 130 with jtag interface; An output terminal of processing unit 110 is as buffering control pin, GPIO (General Purpose Input Output normally, general input and output) pin is connected to OE (the Output Enable of tristate output buffer, output enable) pin, this buffering control pin is connected to Vcc through resistance R simultaneously.Logic chip with jtag interface can be EP2S15, EPM570 or EPM1270 etc.
The OE of general tristate output buffer 120 is that low level is effective, during processing unit 110 on-line loaded, control the pin output low level like this by this buffering, the OE pin level of tristate output buffer 120 is dragged down, the output of tristate output buffer 120 is effective, and 110 of processing units can conduct interviews to the logic chip 130 with jtag interface; When processing unit 110 during from this buffering control pin output high level, the OE pin of tristate output buffer 120 is a high level, this moment processing unit 110 with have jtag interface logic chip 130 and isolated by tristate output buffer 120, PC loads seat 140 can load the logic chip 130 with jtag interface.
When embedded system was used for the first time, the logic of its place veneer was blank usually, and Flash (flash memory) also is blank, and processing unit 110 can not move, and the pin of the buffering of processing unit 110 control at this moment is high level or a low level at random.Under the situation of its output low level, the output of tristate output buffer 120 is effective, be urged to the JTAG data and the control bus of logic chip 130 with jtag interface, can produce bus collision if load 130 of logic chips, may cause chip to damage or load and to carry out with jtag interface by PC loading seat 140.In addition, when some fault takes place processing unit 110, also may cause buffering control pin to continue output low level, at this moment also have same problem.
The utility model content
It is to be solved in the utility model that to be existing buffer circuit use or processing unit issuable bus collision problem when breaking down first in embedded system.
The JTAG buffer circuit of embedded system described in the utility model is connection processing unit and the logic chip with jtag interface respectively, comprises monostable unit and tristate output buffer, wherein:
Tristate output buffer cushions output to processing unit and the JTAG data and the control signal that have between the logic chip of jtag interface;
The monostable triggering input control pin connection processing unit of monostable unit, output control pin connects the output enable pin of tristate output buffer.
Alternatively, the monostable triggering input control pin connection processing unit of described monostable unit is specially:
The JTAG data of the monostable triggering input control pin connection processing unit of monostable unit and the clock pin in the control signal.
Alternatively, the monostable triggering input control pin connection processing unit of described monostable unit is specially:
The buffering control pin of the monostable triggering input control pin connection processing unit of monostable unit.
Preferably, described buffer circuit also comprises the steering logic unit, be connected between the monostable triggering input control pin and processing unit of monostable unit, its input end is JTAG data and the clock pin in the control signal and the buffering control pin of connection processing unit respectively, its output terminal connects the monostable triggering input control pin of monostable unit, and input end signal is carried out exporting after the logical operation.
Preferably, described steering logic unit comprises logical and unit, logical OR unit or logic XOR unit.
Alternatively, the monostable triggering input control pin of described monostable unit is for triggering input end A pin, and output control pin is inverse output terminal/Q pin.
Alternatively, the monostable triggering of described monostable unit input control pin is for triggering input end B pin, and output control pin is output terminal Q pin in the same way.
Preferably, described buffer circuit also comprises logic conversion unit, between the output control pin that is connected monostable unit and the output enable pin of three-state buffer, be used for the temporary steady-state signal that monostable unit is exported is converted to the output enable signal of tristate output buffer.
Preferably, the buffering of described processing unit control pin is general input and output GPIO pin.
Preferably, described monostable unit is for can heavily trigger monostable unit.
The utility model increases monostable unit between the output enable pin of processing unit and tristate output buffer, the processing unit output signal is controlled the output level of monostable unit, enables tristate output buffer by the output level of monostable unit.As seen, processing unit only just can enable tristate output buffer when output pulse signal, like this when the processing unit that uses for the first time embedded system or embedded system breaks down, no matter processing unit connects the level height of the pin of monostable unit, tristate output buffer is high-impedance state, avoided contingent bus collision, can not influence PC loading seat the logic chip with jtag interface is conducted interviews;
Further, the utility model makes processing unit can select different control signals to enable tristate output buffer by increase the steering logic unit between monostable unit and processing unit, has increased the control dirigibility of processing unit.
Description of drawings
Fig. 1 is the structural representation of the embedded system at JTAG buffer circuit and place thereof in the prior art;
Fig. 2 is the structural representation of the embedded system at JTAG buffer circuit embodiment one described in the utility model and place thereof;
Fig. 3 is the structural representation of the embedded system at JTAG buffer circuit embodiment two described in the utility model and place thereof;
Fig. 4 is the structural representation of the embedded system at JTAG buffer circuit embodiment three described in the utility model and place thereof.
Embodiment
In the utility model, the JTAG buffer circuit adopts the trigger action mode in processing unit one side, replaces level triggering mode of the prior art.Because processing unit usually only just can be in certain pin output pulse under normal operating condition, the JTAG buffer circuit can not opened because of the level at random of certain pin of processing unit like this, thereby can prevent that the level of exporting under the processing unit abnomal condition at random from driving jtag bus.
Embedded system described in the utility model and JTAG buffer circuit embodiment one wherein can have structure shown in Figure 2.The JTAG data of processing unit 110 and control signal are connected to the I/O pin of tristate output buffer 120, have the JTAG data of logic chip 130 of jtag interface and output/input pin that control signal is connected to three-state buffer 120 correspondences.When the output of tristate output buffer 120 is effective, processing unit 110 can be from the input pin of the tristate output buffer 120 of its connection to the logic chip 130 output JTAG signals with jtag interface, perhaps receive the output signal of the logic chip 130 with jtag interface from the output pin of the tristate output buffer 120 of its connection.
JTAG data and control signal that PC loads seat also are connected to the logic chip 130 with jtag interface, and when tristate output buffer 120 was output as high-impedance state, PC loads seat can carry out read and write access to the logic chip 130 with jtag interface.
An output terminal of processing unit 110 connects the monostable triggering input control pin of monostable unit 150 as buffering control pin, and the output control pin of monostable unit 150 is connected to the output enable pin OE of tristate output buffer 120.Monostable unit 150 can be a monostable chip, also can be the module with monostable function that is formed by several chip portfolios.
The function that one skilled in the art will appreciate that monostable unit 150 is the pulse signal of output certain width after receiving rising edge or negative edge trigger pip.Monostable unit comprises can not heavily trigger monostable unit and can heavily trigger monostable unit, wherein can not heavily trigger monostable unit after a trigger pip effect, and output enters temporary stable state, and before stable state did not finish temporarily, the trigger pip of coming again was inoperative.For can heavily triggering monostable unit, before the temporary stable state of output does not also finish, after the trigger pip of having again the effect, will respond this new trigger pip, also to postpone a temporary stable state time again, output just can be returned stable state.
In the circuit of Fig. 2, when processing unit 110 from the output of buffering control pin during greater than the pulse of monostable unit 150 preset frequencies, the signal of monostable unit 150 output enable tristate output buffers 120, processing unit 110 can conduct interviews by the logic chip 130 that 120 pairs of tristate output buffers have a jtag interface.
The monostable triggering input control pin of monostable unit 150 can be to trigger input end A pin, also can be to trigger input end B pin; Accordingly, output control pin can be inverse output terminal/Q pin, also can be output terminal Q pin in the same way.The user can select corresponding pin for use according to the tristate output buffer 120 required enable signals of its selection.In addition, processing unit 110 export the frequency of the pulse signal of monostable unit 150 to should be greater than the preset frequency of monostable unit 150.
When monostable unit 150 adopts can not heavily trigger monostable unit the time, width of its output pulse should guarantee that processing unit 110 finishes the JTAG visit.If adopting, monostable unit 150 can heavily trigger monostable unit, when the width of its output pulse signal can not satisfy processing unit 110 and finishes required time of JTAG visit, processing unit 110 can be exported a plurality of pulse signals and make the monostable during the visit unit 150 of the JTAG signal of output enable tristate output buffer 120 all the time.As seen, can heavily trigger monostable unit and have better dirigibility, so the utility model recommends employing can heavily trigger monostable unit.
Unless processing unit 110 output pulse signals are opened tristate output buffer 120 to monostable unit 150, tristate output buffer 120 is in high-impedance state in other cases.At this moment, PC loading seat 140 can conduct interviews to the logic chip 130 with jtag interface by JTAG data and control bus.
The embedded system at JTAG buffer circuit embodiment two described in the utility model and place thereof can have structure shown in Figure 3, for simplicity, only to describing with the difference of embodiment one among the embodiment two, all the other see also the description of embodiment one, no longer repeat.
In embodiment two, processing unit 110 does not adopt the buffering control pin among the embodiment one to be connected with monostable unit 150, and JTAG data that will be connected with tristate output buffer 120 and the clock signal TCK in the control signal export monostable unit 150 simultaneously to, and the pin that is about to processing unit 110 output JTAG tck signals is connected to the monostable triggering input control pin of monostable unit 150 simultaneously.
Make the preset frequency of monostable unit 150 be lower than the frequency of JTAG tck signal, then processing unit can be opened tristate output buffer 120 by output JTAG clock signal, and the logic chip 130 with jtag interface is carried out read-write operation.Present embodiment can be saved an output pin of processing unit 110.
The structure of the embedded system at JTAG buffer circuit embodiment three described in the utility model and place thereof as shown in Figure 4, and is same, herein only to describing with the difference of embodiment one among the embodiment three.
In embodiment three, processing unit 110 can be controlled monostable unit 150 by two signals at least.The buffering of processing unit 110 control pin is connected to an input end pin of steering logic unit 160 among Fig. 4, and the pin of clock signal TCK is connected to another input pin of steering logic unit 160 simultaneously in processing unit 110 output JTAG data and the control signal.The output terminal of steering logic unit 160 is connected to the monostable triggering input control pin of monostable unit 150, the result is exported to the monostable triggering input control end of monostable unit 150 after two input signals are carried out logical operation.
Steering logic unit 160 can be logical and, logical OR, logic XOR or other logical operation functional units, as long as the output signal of processing unit 110 gets final product to enable tristate output buffer 120 through satisfying the input pulse of its requirement after its computing to 150 outputs of monostable unit.From another angle, behind definite steering logic unit 160, processing unit 110 can make pulse signal that 160 outputs of steering logic unit meet the demands to monostable unit 150 by output and the corresponding buffer control signal of its steering logic and/or tck signal, enable tristate output buffer 120 by monostable unit 150, thereby finish accessing operation logic chip 130 with jtag interface.
For example, when steering logic unit 160 is during with door, no matter processing unit 110 exports tck signal, perhaps from buffering control pin output pulse signal, steering logic unit 160 all can output pulse signal to monostable unit 150.Those skilled in the art can require to realize steering logic unit 160 and monostable unit 150 in conjunction with the arithmetic logic of its selection, the level of concrete chip, repeat no more herein.
Like this, processing unit 110 can be controlled the output of monostable unit 150 by at least two signals, increases the dirigibility to buffer circuit control.
In above-mentioned three embodiment, relation according to the enable signal of the output signal of selected monostable unit 150 and tristate output buffer 120OE pin, the user may increase another logic conversion unit between the OE pin of the output terminal of monostable unit 150 and tristate output buffer 120, its input end connects the output control pin of monostable unit 150, and its output terminal connects the OE pin of tristate output buffer 120.Temporary steady-state signal is exported in monostable unit 150 when receiving processing unit 110 pulse signals.The temporary steady-state signal that logic conversion unit is exported monostable unit 150 is converted to the enable signal with tristate output buffer 120.Logic conversion unit both can carry out the logical transition of high-low level, also can carry out the level and the format conversion of signal, can also doublely do above-mentioned two kinds of conversions.
After using the utility model, when processing unit 110 is not visited the logic chip 130 with jtag interface, can guarantee that PC loads seat 140 and the jtag bus that has between the logic chip 130 of jtag interface can be used, can when processing unit 110 is in the abnormal running state, not produce electric conflict.
Above-described the utility model embodiment does not constitute the qualification to the utility model protection domain.Any modification of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the claim protection domain of the present utility model.
Claims (10)
1. the testing action of an embedded system is united group JTAG buffer circuit, and connection processing unit and the logic chip with jtag interface is characterized in that respectively, comprise monostable unit and tristate output buffer, wherein:
Tristate output buffer cushions output to processing unit and the JTAG data and the control signal that have between the logic chip of jtag interface;
The monostable triggering input control pin connection processing unit of monostable unit, output control pin connects the output enable pin of tristate output buffer.
2. the JTAG buffer circuit of embedded system according to claim 1, it is characterized in that the monostable triggering input control pin connection processing unit of described monostable unit is specially: the JTAG data of the monostable triggering input control pin connection processing unit of monostable unit and the clock pin in the control signal.
3. the JTAG buffer circuit of embedded system according to claim 1, it is characterized in that the monostable triggering input control pin connection processing unit of described monostable unit is specially: the buffering control pin of the monostable triggering input control pin connection processing unit of monostable unit.
4. the JTAG buffer circuit of embedded system according to claim 1, it is characterized in that, described buffer circuit also comprises the steering logic unit, be connected between the monostable triggering input control pin and processing unit of monostable unit, its input end is JTAG data and the clock pin in the control signal and the buffering control pin of connection processing unit respectively, its output terminal connects the monostable triggering input control pin of monostable unit, and input end signal is carried out exporting after the logical operation.
5. as the JTAG buffer circuit of embedded system as described in the claim 4, it is characterized in that described steering logic unit comprises logical and unit, logical OR unit or logic XOR unit.
6. as the JTAG buffer circuit of embedded system as described in any one of the claim 2 to 5, it is characterized in that: the monostable triggering input control pin of described monostable unit is for triggering input end A pin, and output control pin is inverse output terminal/Q pin.
7. as the JTAG buffer circuit of embedded system as described in any one of the claim 2 to 5, it is characterized in that: the monostable triggering input control pin of described monostable unit is for triggering input end B pin, and output control pin is output terminal Q pin in the same way.
8. as the JTAG buffer circuit of embedded system as described in any one of the claim 2 to 5, it is characterized in that: described buffer circuit also comprises logic conversion unit, between the output control pin that is connected monostable unit and the output enable pin of three-state buffer, be used for the temporary steady-state signal that monostable unit is exported is converted to the output enable signal of tristate output buffer.
9. the JTAG buffer circuit of embedded system according to claim 1, it is characterized in that: the buffering control pin of described processing unit is general input and output GPIO pin.
10. the JTAG buffer circuit of embedded system according to claim 1, it is characterized in that: described monostable unit is for can heavily trigger monostable unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201757448U CN201017277Y (en) | 2006-12-22 | 2006-12-22 | Action testing combine group buffer of embedded system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201757448U CN201017277Y (en) | 2006-12-22 | 2006-12-22 | Action testing combine group buffer of embedded system |
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| CN201017277Y true CN201017277Y (en) | 2008-02-06 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011009409A1 (en) * | 2009-07-23 | 2011-01-27 | 中兴通讯股份有限公司 | Jtag apparatus and method for implementing jtag data transmission |
| CN103019139A (en) * | 2012-12-04 | 2013-04-03 | 中国北方车辆研究所 | JTAG (Joint Test Action Group) isolation circuit used for DSP (Digital Signal Processor) |
| CN103761127A (en) * | 2014-01-08 | 2014-04-30 | 杭州华三通信技术有限公司 | Device and method for mounting CPLD (complex programmable logic device) chip |
| CN104750481A (en) * | 2015-03-10 | 2015-07-01 | 深圳大学 | FPGA output pin multiplex circuit, method and equipment |
| CN105487404A (en) * | 2015-11-28 | 2016-04-13 | 江苏宏宝电子有限公司 | DSP emulator based on magnetic isolation technology |
| CN103885848B (en) * | 2014-03-13 | 2016-08-31 | 南京科远驱动技术有限公司 | The deadlock of a kind of microprocessor, the protection circuit of program fleet fault and implementation method |
| US20210271593A1 (en) * | 2009-07-16 | 2021-09-02 | Netlist, Inc. | Memory module with distributed data buffers |
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2006
- 2006-12-22 CN CNU2006201757448U patent/CN201017277Y/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210271593A1 (en) * | 2009-07-16 | 2021-09-02 | Netlist, Inc. | Memory module with distributed data buffers |
| WO2011009409A1 (en) * | 2009-07-23 | 2011-01-27 | 中兴通讯股份有限公司 | Jtag apparatus and method for implementing jtag data transmission |
| US8689063B2 (en) | 2009-07-23 | 2014-04-01 | Zte Corporation | JTAG apparatus and method for implementing JTAG data transmission |
| CN103019139A (en) * | 2012-12-04 | 2013-04-03 | 中国北方车辆研究所 | JTAG (Joint Test Action Group) isolation circuit used for DSP (Digital Signal Processor) |
| CN103761127A (en) * | 2014-01-08 | 2014-04-30 | 杭州华三通信技术有限公司 | Device and method for mounting CPLD (complex programmable logic device) chip |
| CN103761127B (en) * | 2014-01-08 | 2017-03-08 | 杭州华三通信技术有限公司 | A kind of device and method of loading CPLD chip |
| CN103885848B (en) * | 2014-03-13 | 2016-08-31 | 南京科远驱动技术有限公司 | The deadlock of a kind of microprocessor, the protection circuit of program fleet fault and implementation method |
| CN104750481A (en) * | 2015-03-10 | 2015-07-01 | 深圳大学 | FPGA output pin multiplex circuit, method and equipment |
| CN104750481B (en) * | 2015-03-10 | 2018-04-17 | 深圳大学 | A kind of FPGA output pins multiplex circuit, method and apparatus |
| CN105487404A (en) * | 2015-11-28 | 2016-04-13 | 江苏宏宝电子有限公司 | DSP emulator based on magnetic isolation technology |
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