CN115933793B - Control method of voltage stabilizer circuit and voltage stabilizer circuit - Google Patents
Control method of voltage stabilizer circuit and voltage stabilizer circuit Download PDFInfo
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Abstract
The invention provides a control method of a voltage stabilizer circuit and the voltage stabilizer circuit. The voltage regulator circuit includes: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit; the voltage stabilizing circuit determines an error signal based on a preset reference voltage and the divided output voltage, and adjusts the output voltage based on the error signal; the sampling circuit accurately samples the current flowing through the load end; the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; the method realizes simultaneous adjustment of the main pole and the zero point based on the load current. In the mode, the main pole and the zero point can be adjusted simultaneously based on the load current, and the zero point and the main pole point can be changed together, so that the effect of dynamic zero point compensation is achieved.
Description
Technical Field
The invention relates to the technical field of dynamic zero compensation, in particular to a control method of a voltage stabilizer circuit and the voltage stabilizer circuit.
Background
With the development of semiconductor integrated circuits, portable electronic products mainly powered by batteries play an increasingly important role in daily life, and voltage regulation circuits are required in battery powered systems, so that LDO regulators (Low Dropout Regulator, low dropout regulators) are widely designed and used as one of the core units of the voltage regulation circuits due to their simple structure, fast response speed, strong power supply ripple suppression capability, etc. In LDO voltage regulator systems, the amount of current required by the load varies with the operating state of the load, and the impedance provided by the load varies due to the different load currents, which often results in unstable operation of the closed loop system formed by the LDO voltage regulator and its load.
At present, most of the technical schemes are to use a feedback coefficient reduction method and a zero point compensation scheme for stability compensation of an unstable system: the feedback coefficient reducing method is to reduce the feedback coefficient of the system to make the gain focus of the system move to the left side of the phase focus, so that the system becomes stable from unstable, but the feedback coefficient is reduced to greatly reduce the gain and bandwidth, so that the precision of the LDO voltage stabilizer is reduced; the zero compensation scheme generally uses an ESR (Equivalment SERIES RESISTANCE) zero compensation method, which can generate a compensation zero by utilizing an output capacitor and an equivalent series resistance thereof on the premise of not influencing the output precision of the LDO voltage stabilizer, and the zero is moved to a direction close to an original point by adjusting the output capacitor, so that the phase shift of a system at a unit gain is smaller than-180 degrees, the system is changed from unstable to stable, and the ESR zero compensation method cannot play the role of the system in the LDO voltage stabilizer with a large load variation range.
Most of the existing technical schemes have the following disadvantages:
(1) The load is compensated by a large capacitance, and the used capacitance value needs to be large, so that the system bandwidth of the whole LDO voltage regulator becomes narrow, and the response rate becomes slow;
(2) Zero compensation is carried out on the circuit by relying on the equivalent series resistance of the load capacitor, the equivalent series resistance value of the capacitor is excessively depended, the stability of a loop is influenced by excessively low and excessively high values, the method is influenced by factors such as temperature, load current and the like, and the compensation effect is unstable;
(3) In the traditional zero compensation circuit, the zero frequency of compensation is fixed, and in an LDO voltage stabilizer with large change of a load range, the compensation effect is unstable due to large change of the frequency of an output main pole point, and the circuit still can oscillate under certain conditions.
Disclosure of Invention
Accordingly, an object of the present invention is to provide a control method of a voltage regulator circuit and a voltage regulator circuit, so as to adjust a main pole and a zero point simultaneously based on a load current, wherein the zero point and the main pole can be changed together, and achieve a dynamic zero compensation effect.
In a first aspect, an embodiment of the present invention provides a control method of a voltage regulator circuit, where the voltage regulator circuit includes: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit; the voltage stabilizing circuit determines an error signal based on a preset reference voltage and the divided output voltage, and adjusts the output voltage based on the error signal; the sampling circuit accurately samples the current flowing through the load end; the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and realizing the dynamic compensation of the main pole point.
In a preferred embodiment of the present application, the zero compensation circuit includes: a compensation resistor and a compensation capacitor; the zero compensation circuit generates miller compensation to separate the primary and secondary poles of the voltage regulator circuit.
In a preferred embodiment of the present application, the voltage stabilizing circuit includes: the PMOS power tube MP1, a first voltage dividing resistor, a second voltage dividing resistor and an error amplifier; the external power supply is connected with the source electrode of the PMOS power tube MP1, the drain electrode of the PMOS power tube MP1, the first voltage dividing resistor and the second voltage dividing resistor are sequentially connected, and the second voltage dividing resistor is grounded; the second input end of the error amplifier is arranged between the first voltage dividing resistor and the second voltage dividing resistor.
In a preferred embodiment of the present application, the voltage stabilizing circuit determines an error signal based on a preset reference voltage and the divided output voltage, and adjusts the output voltage based on the error signal, including: the voltage signal input by an external power supply is subjected to PMOS power tube MP1 to obtain output voltage, and the output voltage is divided by a first voltage dividing resistor and a second voltage dividing resistor; the first input end of the error amplifier receives the reference voltage, and the second input end of the error amplifier receives the divided output voltage; the error amplifier takes the difference value between the reference voltage and the divided output voltage as an error signal, and negative feedback adjustment of the output voltage is realized based on the error signal.
In a preferred embodiment of the present application, the sampling circuit is connected to the gate of the PMOS power transistor MP 1; the sampling circuit comprises a PMOS sampling current tube MP2; the step of sampling circuit accurate sampling current flowing through load end includes: the sampling circuit accurately samples the current flowing through the load end based on the width-to-length ratio of the PMOS power tube MP1, the width-to-length ratio of the PMOS sampling current tube MP2 and the load current.
In a preferred embodiment of the present application, the voltage regulator circuit further includes: a current limiting circuit; the method further comprises the steps of: the current limiting circuit receives the sampling current output by the sampling circuit and controls the opening and closing of the voltage stabilizer circuit based on the sampling current and a preset current threshold value.
In a preferred embodiment of the present application, the step of controlling the opening and closing of the voltage regulator circuit based on the sampled current and a preset current threshold includes: if the sampling current is smaller than a preset current threshold value, controlling the voltage stabilizer circuit to be closed; and if the sampling current is greater than or equal to the current threshold value, controlling the voltage stabilizer circuit to be opened.
In a second aspect, an embodiment of the present invention further provides a voltage regulator circuit, which is used in the control method of the voltage regulator circuit; the voltage regulator circuit includes: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit; the zero compensation circuit is connected with the sampling circuit, the zero compensation circuit is also connected with the voltage stabilizing circuit, the sampling circuit is connected with the output end of the error amplifier of the voltage stabilizing circuit, and the PMOS sampling current tube MP2 of the sampling circuit is connected with the PMOS power tube MP 1.
In a preferred embodiment of the present application, the voltage regulator circuit further includes: a current limiting circuit: the current limiting circuit is connected with the sampling circuit, and the current limiting circuit is also connected with the grid electrode of the PMOS power tube MP1 of the voltage stabilizing circuit.
The embodiment of the invention has the following beneficial effects:
According to the control method of the voltage stabilizer circuit and the voltage stabilizer circuit provided by the embodiment of the invention, the voltage stabilizer circuit can determine an error signal based on the reference voltage and the divided output voltage, and adjust the output voltage based on the error signal; the sampling circuit can accurately sample the current flowing through the load end; the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and the load current is realized, and the main pole and the zero point are adjusted simultaneously. In the mode, the main pole and the zero point can be adjusted simultaneously based on the load current, and the zero point and the main pole point can be changed together, so that the effect of dynamic zero point compensation is achieved.
Additional features and advantages of the disclosure will be set forth in the description which follows, or in part will be obvious from the description, or may be learned by practice of the techniques of the disclosure.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a control method of a voltage regulator circuit according to an embodiment of the present invention;
FIG. 2 is a flowchart of another control method of a voltage regulator circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a small signal circuit of an LDO voltage regulator according to an embodiment of the present invention;
Fig. 5 is a schematic diagram of an internal structure of a sampling circuit, a dynamic zero compensation circuit and a current limiting circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an equivalent small signal circuit of a zero compensation circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a control device of a voltage regulator circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a voltage regulator circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Most of the technical schemes are to use a feedback coefficient reduction method and a zero point compensation scheme for stability compensation of an unstable system: the feedback coefficient reducing method is to reduce the feedback coefficient of the system to make the gain focus of the system move to the left side of the phase focus, so that the system becomes stable from unstable, but the feedback coefficient is reduced to greatly reduce the gain and bandwidth, so that the precision of the LDO voltage stabilizer is reduced; the zero compensation scheme generally uses an ESR (Equivalment SERIES RESISTANCE) zero compensation method, which can generate a compensation zero by utilizing an output capacitor and an equivalent series resistance thereof on the premise of not influencing the output precision of the LDO voltage stabilizer, and the zero is moved to a direction close to an original point by adjusting the output capacitor, so that the phase shift of a system at a unit gain is smaller than-180 degrees, the system is changed from unstable to stable, and the ESR zero compensation method cannot play the role of the system in the LDO voltage stabilizer with a large load variation range.
Most of the existing technical schemes have the following disadvantages:
(1) The load is compensated by a large capacitance, and the used capacitance value needs to be large, so that the system bandwidth of the whole LDO voltage regulator becomes narrow, and the response rate becomes slow;
(2) Zero compensation is carried out on the circuit by relying on the equivalent series resistance of the load capacitor, the equivalent series resistance value of the capacitor is excessively depended, the stability of a loop is influenced by excessively low and excessively high values, the method is influenced by factors such as temperature, load current and the like, and the compensation effect is unstable;
(3) In the traditional zero compensation circuit, the zero frequency of compensation is fixed, and in an LDO voltage stabilizer with large change of a load range, the compensation effect is unstable due to large change of the frequency of an output main pole point, and the circuit still can oscillate under certain conditions.
Based on the above, the control method of the voltage regulator circuit and the voltage regulator circuit provided by the embodiments of the present invention are applied to the dynamic zero compensation technology of the LDO, and in particular, provide a loop stability method suitable for the LDO voltage regulator, which can quickly, stably and flexibly perform current limiting and dynamic zero compensation on the load current on the premise of not affecting the output precision of the LDO voltage regulator, so that the LDO voltage regulator stably operates. In the mode, the transient response of the LDO voltage stabilizer can be proved; the LDO voltage stabilizer is ensured to run stably with high precision and does not oscillate; a compensation zero can be generated that follows the main pole.
For the sake of understanding the present embodiment, a detailed description will be given of a control method of a voltage regulator circuit disclosed in the present embodiment.
Embodiment one:
The embodiment of the invention provides a control method of a voltage stabilizer circuit, referring to a flow chart of the control method of the voltage stabilizer circuit shown in fig. 1, the control method of the voltage stabilizer circuit comprises the following steps:
in step S102, the voltage stabilizing circuit determines an error signal based on the preset reference voltage and the divided output voltage, and adjusts the output voltage based on the error signal.
The voltage regulator circuit of the present embodiment includes: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit. Wherein the main pole of the voltage regulator circuit is positively correlated with the load current. The voltage stabilizer of the voltage stabilizing circuit can be an LDO voltage stabilizer, and the LDO is a linear voltage stabilizer. Because the voltage in the circuit is unstable, the output voltage of the voltage stabilizing circuit also fluctuates, the output voltage can be divided by a plurality of voltage dividing resistors, the difference between the divided output voltage and the reference voltage is used as an error signal, and the output voltage can be regulated by the error signal so as to enable the divided output voltage to be close to the reference voltage.
In step S104, the sampling circuit accurately samples the current flowing through the load terminal.
The sampling circuit collects load current for the voltage stabilizing circuit, specifically, the sampling circuit can be connected with the grid electrode of the PMOS power tube, and the current output by the grid electrode of the PMOS power tube is used as load current. The sampling circuit can calculate and obtain sampling current according to the input load current and the width-to-length ratio of the PMOS power tube and the PMOS sampling current tube.
Step S106, the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and the load current is realized, and the main pole and the zero point are adjusted simultaneously.
Zero drift is a phenomenon that when an input signal of an amplifying circuit is zero, a static working point is changed due to the influence of factors such as temperature change, unstable power supply voltage and the like, and is amplified and transmitted step by step, so that the voltage of an output end of the circuit deviates from an original fixed value and floats up and down.
In order to solve the zero drift, a zero compensation circuit can be added into the circuit, and the zero drift can be compensated by the zero compensation circuit. The zero compensation circuit in this embodiment can generate miller compensation through the compensation resistor and the compensation capacitor, and separate the primary pole and the secondary pole of the voltage stabilizer circuit.
According to the control method of the voltage stabilizer circuit, the voltage stabilizer circuit can determine an error signal based on the reference voltage and the divided output voltage, and adjust the output voltage based on the error signal; the sampling circuit can accurately sample the current flowing through the load end; the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and the load current is realized, and the main pole and the zero point are adjusted simultaneously. In the mode, the main pole and the zero point can be adjusted simultaneously based on the load current, and the zero point and the main pole point can be changed together, so that the effect of dynamic zero point compensation is achieved.
Embodiment two:
The present embodiment provides another control method of a voltage regulator circuit, which is implemented on the basis of the above embodiment, referring to a flowchart of another control method of a voltage regulator circuit shown in fig. 2, the control method of a voltage regulator circuit includes the steps of:
in step S202, the voltage stabilizing circuit determines an error signal based on the preset reference voltage and the divided output voltage, and adjusts the output voltage based on the error signal.
Specifically, the voltage stabilizing circuit includes: the PMOS power tube, the first voltage dividing resistor, the second voltage dividing resistor and the error amplifier; the external power supply is connected with the source electrode of the PMOS power tube, the external power supply is also connected with the grid electrode of the PMOS power tube, the drain electrode of the PMOS power tube, the first voltage dividing resistor and the second voltage dividing resistor are sequentially connected, and the second voltage dividing resistor is grounded; the second input end of the error amplifier is arranged between the first voltage dividing resistor and the second voltage dividing resistor.
Referring to a schematic diagram of a voltage regulator circuit shown in fig. 3, GM is an error amplifier, MP1 is a PMOS power tube of an LDO voltage regulator, MP2 is a PMOS sampling current tube, and the percentages of RF2 and RF1 are a first voltage dividing resistor and a second voltage dividing resistor, where the PMOS sampling current tube MP2 is connected to a sampling current module through a port VO.
In step S204, the sampling circuit accurately samples the current flowing through the load terminal.
As shown in fig. 3, a voltage signal VDD input by an external power supply is obtained by passing through a PMOS power transistor, and the output voltage is divided by a first voltage dividing resistor RF1 and a second voltage dividing resistor RF 2; the first input end of the error amplifier receives the reference voltage VREF, and the second input end of the error amplifier receives the divided output voltage; the error amplifier takes the difference value between the reference voltage and the divided output voltage as an error signal, and realizes negative feedback adjustment of the output voltage based on the error signal, and the error signal can be input into the sampling circuit.
Referring to a schematic diagram of a small signal circuit of an LDO voltage regulator shown in fig. 4, where Rds is an equivalent resistance of a power transistor MP1, RF1 and RF2 are voltage dividing resistors, cout is a load capacitor, RESR is an equivalent resistance of the load capacitor, and Cb is an output bypass capacitor.
As shown in FIG. 4, the output dominant pole of the LDO regulator can be deducedThe method comprises the following steps: it can be seen that the output dominant pole of the LDO voltage regulator changes along with the change of the load current, and the dominant pole/>, of the voltage regulator circuit And load current/>Positive correlation.
In step S206, the current limiting circuit receives the sampling current output by the sampling circuit, and controls the voltage regulator circuit to be opened and closed based on the sampling current and a preset current threshold.
As shown in fig. 3, the voltage regulator circuit of the present embodiment further includes: a current limiting circuit. The current limiting circuit is used for limiting the current of the voltage stabilizer, and can control the opening and closing of the voltage stabilizer circuit according to the sampling current and the current threshold value. For example: if the sampling current is smaller than a preset current threshold value, controlling the voltage stabilizer circuit to be closed; and if the sampling current is greater than or equal to the current threshold value, controlling the voltage stabilizer circuit to be opened.
Wherein, the opening and closing of the voltage stabilizer circuit can be controlled by controlling the MOS tube of the voltage stabilizer circuit. Therefore, the load current can be limited on the premise of not affecting the output precision of the LDO voltage stabilizer.
As shown in fig. 3, the sampling circuit is connected with the gate of the PMOS power tube, and the load current output by the gate of the PMOS power tube can be collected by the sampling circuit.
Referring to an internal structure schematic diagram of a sampling circuit, a dynamic zero compensation circuit and a current limiting circuit shown in fig. 5, wherein the output end of V0 is connected with the drain electrode of the sampling tube MP2, and the output end of V1 is connected with the gate electrode of the power tube MP 1.
The sampling circuit can be composed of a MOS tube M1, a MOS tube M2, a MOS tube M3, a MOS tube M4, a MOS tube MP2, a transistor Q1, a transistor Q2, a resistor R1 and a resistor R2. The current limiting circuit receives the signal output by the current sampling circuit, and determines the turn-off of the MOS tube M5 according to the set current threshold value so as to achieve the function of controlling whether the subsequent circuit works.
Considering that the MOS tube is a voltage-controlled device, the drain, gate and source three-terminal voltages of the power tube M1P and the sampling tube MP2 are in mirror image equality, the source of the sampling current tube MP2 is directly connected with the power voltage through the resistor R1, and the resistance value of the R1 is far smaller than the equivalent resistance of MP2, so that the source voltage of the approximate MP2 is the power voltage.
Therefore, the sampling circuit can accurately sample the current flowing through the load terminal based on the width-to-length ratio of the PMOS power tube, the width-to-length ratio of the PMOS sampling current tube and the load current. Obtaining the current with load by controlling the width-to-length ratio of MP2 and MP1Proportional small sampling current/>. Sampling current/>The method comprises the following steps: /(I). Wherein/>、/>Is MP2 wide and long,/>、/>Is MP1 wide and long.
Assume that the current flowing through resistor R1 is: Collector current of Q1/> The method comprises the following steps:。
Therefore, the base current of Q1 Emitter current/>The method comprises the following steps:；/>。
M1, M2, M3, M4 tubes for accurate replication of reference currents independent of supply voltage, temperature Assume that M1, M2 replicates the reference current/>Is a multiple of A, M3, M4 replication reference current/>Is a multiple of B, the emitter current of Q2/>, assuming that the dimensions of transistors Q2 and Q1 are proportional KThe method comprises the following steps: /(I)。
Step S208, the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and the load current is realized, and the main pole and the zero point are adjusted simultaneously.
As shown in fig. 4, the zero compensation circuit is mainly composed of Q3, Q4. The base of the Q3 transistor takes the emitter current of the Q2 transistor. Base current of Q3The method comprises the following steps:。
Specifically, the zero compensation circuit includes: a compensation resistor and a compensation capacitor; the zero compensation circuit may produce miller compensation to separate the dominant and the subordinate poles of the voltage regulator circuit.
As shown in fig. 4, the compensation resistor R3 and the compensation capacitor C1 are utilized to generate the function of miller compensation, so that the main pole point and the secondary pole point of the circuit are separated, the secondary pole point is moved out of the bandwidth, and the Q4 transistor is an equivalent current source controlled by the current limiting module. Diffusion capacitance using Q3 transistorsAnd/>Diffusion resistance/>To form a zero compensation circuit.
Referring to a schematic diagram of an equivalent small signal circuit of a zero compensation circuit shown in figure 6,And/>Is the diffusion capacitance of transistor Q3,/>The zero generated by the zero compensation network can be obtained as the diffusion resistance of the transistor Q3The method comprises the following steps:。
Wherein, 、/>、/>In relation to the process, it can be seen that the compensation zero/>Collector current with transistor Q3In a proportional relationship, and the collector current of transistor Q3/>The method comprises the following steps:。
Thus, it can be seen that the compensation zero point Also with load current/>The zero point compensated by the zero point compensation network can be changed together with the main pole point to achieve the effect of dynamic zero point compensation.
According to the method provided by the embodiment, the sampling circuit, the current limiting circuit and the dynamic zero compensation circuit can be added into the LDO voltage stabilizer system, two input ends of the error amplifier in the LDO voltage stabilizer system are respectively connected with a reference voltage and a signal generated by dividing the output voltage of the LDO voltage stabilizer through the load resistor, the output signal of the error amplifier is connected with the dynamic zero compensation circuit, and the sampling circuit samples the current signal of the PMOS power tube and achieves the current limiting function.
Embodiment III:
Corresponding to the above method embodiment, the embodiment of the present invention provides a control device for a voltage regulator circuit, where the voltage regulator circuit includes: the voltage regulator circuit, the sampling circuit and the zero point compensation circuit, referring to a schematic structural diagram of a control device of the voltage regulator circuit shown in fig. 7, the control device of the voltage regulator circuit includes:
A voltage stabilizing circuit processing module 71 for determining an error signal based on a preset reference voltage and the divided output voltage by the voltage stabilizing circuit and adjusting the output voltage based on the error signal;
a sampling circuit processing module 72 for accurately sampling the current flowing through the load terminal;
the zero compensation circuit processing module 73 is configured to receive the sampling current output by the sampling circuit, and dynamically adjust the compensation zero position by the zero compensation circuit based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and the load current is realized, and the main pole and the zero point are adjusted simultaneously.
According to the control device of the voltage stabilizer circuit, the voltage stabilizer circuit can determine an error signal based on the reference voltage and the divided output voltage, and adjust the output voltage based on the error signal; the sampling circuit can accurately sample the current flowing through the load end; the zero compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero position based on the sampling current output by the sampling circuit, so that the variation direction of the compensation zero and the main pole position is consistent; and the load current is realized, and the main pole and the zero point are adjusted simultaneously. In the mode, the main pole and the zero point can be adjusted simultaneously based on the load current, and the zero point and the main pole point can be changed together, so that the effect of dynamic zero point compensation is achieved.
The zero compensation circuit includes: a compensation resistor and a compensation capacitor; the zero compensation circuit generates miller compensation to separate the primary and secondary poles of the voltage regulator circuit.
The voltage stabilizing circuit includes: the PMOS power tube MP1, a first voltage dividing resistor, a second voltage dividing resistor and an error amplifier; the external power supply is connected with the source electrode of the PMOS power tube MP1, the drain electrode of the PMOS power tube MP1, the first voltage dividing resistor and the second voltage dividing resistor are sequentially connected, and the second voltage dividing resistor is grounded; the second input end of the error amplifier is arranged between the first voltage dividing resistor and the second voltage dividing resistor.
The voltage stabilizing circuit processing module is used for obtaining output voltage after a voltage signal input by an external power supply passes through the PMOS power tube MP1, and the output voltage is divided by a first voltage dividing resistor and a second voltage dividing resistor; the first input end of the error amplifier receives the reference voltage, and the second input end of the error amplifier receives the divided output voltage; the error amplifier takes the difference value between the reference voltage and the divided output voltage as an error signal, and negative feedback adjustment of the output voltage is realized based on the error signal.
The sampling circuit is connected with the grid electrode of the PMOS power tube MP 1; and the sampling circuit processing module is used for accurately sampling the current flowing through the load end based on the width-to-length ratio of the PMOS power tube, the width-to-length ratio of the PMOS sampling current tube and the load current.
The current limiting circuit processing module is used for controlling the closing of the voltage stabilizer circuit if the sampling current is smaller than a preset current threshold value; and if the sampling current is greater than or equal to the current threshold value, controlling the voltage stabilizer circuit to be opened.
The above-mentioned voltage regulator circuit further includes: a current limiting circuit; the device further comprises: the current limiting circuit processing module is used for receiving the sampling current output by the sampling circuit by the current limiting circuit and controlling the opening and closing of the voltage stabilizer circuit based on the sampling current and a preset current threshold value.
The current limiting circuit processing module is used for controlling the closing of the voltage stabilizer circuit if the sampling current is smaller than a preset current threshold value; and if the sampling current is greater than or equal to the current threshold value, controlling the voltage stabilizer circuit to be opened.
It will be clear to those skilled in the art that, for convenience and brevity of description, the specific operation of the control device of the voltage regulator circuit described above may refer to the corresponding process in the foregoing embodiment of the control method of the voltage regulator circuit, which is not described herein again.
Embodiment four:
The embodiment of the invention also provides a voltage stabilizer circuit, which is used for executing the control method of the voltage stabilizer circuit, and referring to a schematic structure diagram of the voltage stabilizer circuit shown in fig. 8, the voltage stabilizer circuit comprises: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit;
The zero compensation circuit is connected with the sampling circuit, the zero compensation circuit is also connected with the voltage stabilizing circuit, the sampling circuit is connected with the output end of the error amplifier of the voltage stabilizing circuit, and the PMOS sampling current tube MP2 of the sampling circuit is connected with the PMOS power tube MP 1.
Specifically, as shown in fig. 8, the voltage regulator circuit further includes a zero point compensation circuit: a current limiting circuit: the current limiting circuit is connected with the sampling circuit, and the current limiting circuit is also connected with the grid electrode of the PMOS power tube MP1 of the voltage stabilizing circuit.
It will be clear to those skilled in the art that, for convenience and brevity of description, the specific operation of the voltage regulator circuit described above may refer to the corresponding process in the foregoing embodiment of the control method of the voltage regulator circuit, which is not described herein again.
Fifth embodiment:
the embodiment of the invention also provides electronic equipment, which is used for running the control method of the voltage stabilizer circuit; referring to a schematic structural diagram of an electronic device shown in fig. 9, the electronic device includes a memory 100 and a processor 101, where the memory 100 is configured to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the control method of the voltage regulator circuit described above.
Further, the electronic device shown in fig. 9 further includes a bus 102 and a communication interface 103, and the processor 101, the communication interface 103, and the memory 100 are connected through the bus 102.
The memory 100 may include a high-speed random access memory (RAM, random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the system network element and at least one other network element is implemented via at least one communication interface 103 (which may be wired or wireless), and may use the internet, a wide area network, a local network, a metropolitan area network, etc. Bus 102 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one bi-directional arrow is shown in fig. 9, but not only one bus or one type of bus.
The processor 101 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 101 or instructions in the form of software. The processor 101 may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), and the like; but may also be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application Specific Integrated Circuit (ASIC), field-Programmable gate array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 100 and the processor 101 reads information in the memory 100 and in combination with its hardware performs the steps of the method of the previous embodiments.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions that, when being called and executed by a processor, cause the processor to implement the control method of the voltage regulator circuit, and the specific implementation can be referred to the method embodiment and will not be described herein.
The control method of the voltage regulator circuit and the computer program product of the voltage regulator circuit provided by the embodiments of the present invention include a computer readable storage medium storing program codes, and instructions included in the program codes may be used to execute the method in the foregoing method embodiment, and specific implementation may refer to the method embodiment and will not be repeated herein.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and/or apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A control method of a voltage regulator circuit, the voltage regulator circuit comprising: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit;
the voltage stabilizing circuit determines an error signal based on a preset reference voltage and a divided output voltage, and adjusts the output voltage based on the error signal;
the sampling circuit accurately samples the current flowing through the load end;
the zero point compensation circuit receives the sampling current output by the sampling circuit, and dynamically adjusts the compensation zero point position based on the sampling current output by the sampling circuit so that the compensation zero point is consistent with the variation direction of the main polar point position; realizing dynamic compensation of the dominant pole;
The voltage stabilizing circuit includes: the PMOS power tube MP1, a first voltage dividing resistor, a second voltage dividing resistor and an error amplifier; the external power supply is connected with the source electrode of the PMOS power tube MP1, the drain electrode of the PMOS power tube MP1, the first voltage dividing resistor and the second voltage dividing resistor are sequentially connected, and the second voltage dividing resistor is grounded; the first input end of the error amplifier is connected with a reference voltage, the second input end of the error amplifier is arranged between the first voltage dividing resistor and the second voltage dividing resistor, and the output end of the error amplifier outputs an error signal;
The sampling circuit is connected with the grid electrode of the PMOS power tube MP 1; the sampling circuit comprises a PMOS sampling current tube MP2; the step of the sampling circuit accurately sampling the current flowing through the load end comprises the following steps: the sampling circuit accurately samples the current flowing through the load end based on the width-to-length ratio of the PMOS power tube MP1, the width-to-length ratio of the PMOS sampling current tube MP2 and the load current;
Obtaining a small sampling current in a proportional relation with the load current by controlling the width-to-length ratio of the PMOS sampling current tube MP2 and the PMOS power tube MP 1; the sampling current is as follows: ; wherein/> For the load current,/>For the sampling current,/>、/>For the width and length of the PMOS sampling current tube MP2,/>、The PMOS power tube MP1;
The sampling circuit comprises a MOS tube M1, a MOS tube M2, a MOS tube M3, a MOS tube M4, a MOS tube MP2, a transistor Q1, a transistor Q2, a resistor R1 and a resistor R2; the zero compensation circuit comprises a transistor Q3; the base electrode of the transistor Q3 takes the emitter current of the transistor Q2; base current of the transistor Q3 The method comprises the following steps:；
i b3 denotes a base current of the transistor Q3, I e2 denotes an emitter current of the transistor Q2, and I PIBI denotes a reference current;
The grid electrode of the PMOS power tube MP1 is connected with the emitter electrode of the transistor Q3; the MOS tube M2 and the MOS tube M1 are sequentially connected in series between the emitter of the transistor Q1 and the ground; the MOS tube M4 and the MOS tube M3 are sequentially connected in series between the emitter of the transistor Q2 and the ground;
The MOS transistor M1, the MOS transistor M2, the MOS transistor M3 and the MOS transistor M4 are used for copying a reference current I PIBI, the MOS transistor M1 and the MOS transistor M2 copy the reference current I PIBI by a multiple A, the MOS transistor M3 and the MOS transistor M4 copy the reference current I PIBI by a multiple B, and the sizes of the transistor Q2 and the transistor Q1 are in a proportion K;
one end of the resistor R1 is connected with the collector electrode of the transistor Q1 and the output end of the V0, and the other end of the resistor R is connected with the VDD; one end of the resistor R2 is connected with the collector electrode of the transistor Q2, and the other end of the resistor R2 is connected with the VDD; the base electrode and the emitter electrode of the transistor Q1 are connected with the base electrode of the transistor Q2; the source electrode of the MOS tube MP2 is connected with the V0 output end, the grid electrode is connected with the grid electrode of the PMOS power tube MP1, and the drain electrode is connected with the output voltage.
2. The method of claim 1, wherein the zero compensation circuit comprises: a compensation resistor and a compensation capacitor; the zero compensation circuit generates miller compensation to separate the dominant and the subordinate poles of the voltage regulator circuit.
3. The method of claim 1, wherein the voltage regulator circuit determines an error signal based on a predetermined reference voltage and the divided output voltage, and wherein the step of adjusting the output voltage based on the error signal comprises: the voltage signal input by the external power supply passes through the PMOS power tube MP1 to obtain output voltage, and the output voltage is divided by the first voltage dividing resistor and the second voltage dividing resistor; the first input end of the error amplifier receives the reference voltage, and the second input end of the error amplifier receives the divided output voltage;
And the error amplifier takes the difference value of the reference voltage and the divided output voltage as an error signal, and realizes negative feedback adjustment of the output voltage based on the error signal.
4. The method of claim 1, wherein the voltage regulator circuit further comprises: a current limiting circuit; the current limiting circuit receives the sampling current output by the sampling circuit and controls the opening and closing of the voltage stabilizer circuit based on the sampling current and a preset current threshold value.
5. The method of claim 4, wherein the step of controlling opening and closing of the voltage regulator circuit based on the sampled current and a preset current threshold comprises: if the sampling current is smaller than a preset current threshold value, the voltage stabilizer circuit is controlled to be closed; and if the sampling current is greater than or equal to the current threshold value, controlling the voltage stabilizer circuit to be disconnected.
6. A voltage regulator circuit, characterized by being configured to perform the control method of the voltage regulator circuit according to any one of claims 1 to 5; the voltage regulator circuit includes: the device comprises a voltage stabilizing circuit, a sampling circuit and a zero point compensation circuit; the zero compensation circuit is connected with the sampling circuit, the zero compensation circuit is also connected with the voltage stabilizing circuit, the sampling circuit is connected with the output end of the error amplifier of the voltage stabilizing circuit, and the PMOS sampling current tube MP2 of the sampling circuit is connected with the PMOS power tube MP 1.
7. The voltage regulator circuit of claim 6, wherein the voltage regulator circuit further comprises: a current limiting circuit: the current limiting circuit is connected with the sampling circuit, and is also connected with the grid electrode of the PMOS power tube MP1 of the voltage stabilizing circuit.
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| CN106094955A (en) * | 2016-07-20 | 2016-11-09 | 成都启英泰伦科技有限公司 | A kind of low-dropout linear voltage-regulating circuit of low-power consumption |
| CN106940579A (en) * | 2017-03-27 | 2017-07-11 | 北京松果电子有限公司 | Low pressure difference linear voltage regulator and its frequency compensation method |
| CN109116906A (en) * | 2018-10-31 | 2019-01-01 | 上海海栎创微电子有限公司 | A kind of low pressure difference linear voltage regulator based on adaptive antenna zero compensation |
| CN208848104U (en) * | 2018-10-31 | 2019-05-10 | 上海海栎创微电子有限公司 | A kind of low pressure difference linear voltage regulator of fast transient response |
| CN111367347B (en) * | 2020-05-26 | 2020-09-15 | 江苏长晶科技有限公司 | Line loss compensation method and circuit of linear voltage stabilizer |
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| CN101957628A (en) * | 2009-07-17 | 2011-01-26 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
| CN208477417U (en) * | 2018-08-06 | 2019-02-05 | 厦门安斯通微电子技术有限公司 | A kind of LDO flow restriction not increasing quiescent current |
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