CN115912893B - Megasonic power supply system based on DSP and FPGA - Google Patents
Megasonic power supply system based on DSP and FPGA Download PDFInfo
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- CN115912893B CN115912893B CN202211068438.4A CN202211068438A CN115912893B CN 115912893 B CN115912893 B CN 115912893B CN 202211068438 A CN202211068438 A CN 202211068438A CN 115912893 B CN115912893 B CN 115912893B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a megasonic power supply system based on a DSP and an FPGA, which comprises an EMI filter circuit, a PFC circuit, a silicon carbide driving circuit, an impedance matching circuit, a voltage feedback circuit, a current feedback circuit and a DSP circuit. The input end of the EMI filter circuit is connected with the mains supply, the mains supply is filtered through two fuses, a filter capacitor and a common mode inductor in sequence, then is slowly started through a relay, and finally outputs a first voltage V1 through a bridge rectifier circuit; the PFC circuit is used for correcting the power factor, is connected to the output end of the bridge rectifier circuit, and boosts the first voltage V1 to the second voltage V2; the silicon carbide driving circuit is connected to the output end of the PFC circuit. The megasonic power system based on the DSP and the FPGA integrates a DSP floating point algorithm, and an FPGA programmable hardware logic is added to realize a closed loop frequency tracking control architecture for high-frequency, high-speed and high-precision frequency execution.
Description
Technical Field
The invention relates to a power supply system, in particular to a megasonic power supply system based on a DSP and an FPGA.
Background
The megasonic wave is applied in a small field, and is well known in the cleaning field, and the megasonic wave is used as one of ultrasonic waves, so that the cleaning aspect is also prominent.
The generation of megasonic wave necessarily needs a power management system, but through searching, related documents and patents of a megasonic wave power system based on a DSP and an FPGA are not queried at home and abroad.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a megasonic power supply system based on a DSP and an FPGA.
In order to solve the technical problems, the invention is realized by the following scheme: the invention relates to a megasonic power supply system based on a DSP and an FPGA, which comprises:
the input end of the EMI filter circuit is connected with the mains supply, the mains supply is filtered through two fuses, a filter capacitor and a common mode inductor in sequence, then the filter circuit is slowly started through a relay, and finally the first voltage V1 is output through a bridge rectifier circuit;
the PFC circuit is used for carrying out power factor correction on the first voltage V1, is connected to the output end of the bridge rectifier circuit, and boosts the first voltage V1 to the second voltage V2;
the silicon carbide driving circuit is connected to the output end of the PFC circuit, the silicon carbide driving circuit is outwards output through a silicon carbide driving transformer, the transformer is an isolation transformer, the silicon carbide driving circuit is provided with an isolation silicon carbide driving module and a silicon carbide power tube, and the input end of the isolation silicon carbide driving module is connected with the silicon carbide power tube;
The input end of the impedance matching circuit is connected with the output end of the isolation transformer, and the output end of the impedance matching circuit is connected to the megasonic vibrating plate;
the voltage feedback circuit reads the output voltage and current phase of the isolation transformer, sends the output voltage and current phase to the FPGA module for logic analysis, analyzes the phase value, and detects the output voltage value in real time, and the output end of the voltage feedback circuit is connected to a signal waveform shaping module;
the current feedback circuit is connected to the output end of the impedance matching circuit, the output end of the current feedback circuit is connected to the signal waveform shaping module, and the signal waveform shaping module transmits a voltage signal and a current signal to the FPGA module;
the DSP circuit is connected with a DSP main control chip, and the DSP main control chip processes the incoming data signals and transmits the processed signals to a buffer area of the FPGA module;
the PFC circuit comprises an inductor L7, a resistor R28, a diode D8, a diode D7, a capacitor C16, a resistor R25, a capacitor C35, a capacitor C85, a capacitor C86, an NMOS transistor Q6, a resistor R73, a resistor R74, a resistor R75 and a diode D9, wherein one end of the inductor L7 is connected with 300V voltage, the other end of the inductor L7 is connected with the anode of the diode D7 in a connecting mode, the capacitor C16 and the resistor R25 are connected in series and then connected with the diode D7 in parallel, one end of the resistor R28 is connected with 300V voltage, the other end of the resistor R28 is connected with the diode D8 in series, and the cathode of the diode D8 is connected to the cathode of the diode D7;
The negative electrode of the diode D7 is respectively connected with the capacitor C35, the capacitor C85 and the capacitor C86, and the other ends of the capacitor C35, the capacitor C85 and the capacitor C86 are respectively connected with PGND ground;
the cathode of the diode D7 is also connected with a VA+ circuit, and the anode of the diode D is connected with a VPFCO circuit and the drain electrode of the NMOS transistor Q6;
the source electrode of the NMOS transistor Q6 is connected with one end of the resistor R75 in parallel connection with PGND, the grid electrode of the NMOS transistor Q is respectively connected with a resistor R73 and a resistor R74, the other end of the resistor R75 is connected with PV-ground, the other end of the resistor R74 is connected with the positive electrode of the diode D9, the negative electrode of the diode D9 is connected with the other end of the resistor R73, and the negative electrode of the diode D9 is also connected with a GATEOUT2 circuit;
the VA+ circuit is connected with a resistor R78, and the other end of the resistor R78 is connected with a resistor R79;
two ends of the resistor R83, the resistor R85 and the capacitor C91 which are connected in parallel are respectively connected to the other end of the resistor R79 and connected with the GND pin of the power management chip U10;
the ICOMP pin of the power management chip U10 is connected with a capacitor C90, the capacitor C90 pin is connected with the GND pin of the power management chip U10, the FREQ pin of the power management chip U10 is connected with a resistor R82, the other end of the resistor R82 is connected with the GND pin of the power management chip U10, the VSENSE pin of the power management chip U10 is connected with the voltage output end of the resistor R79, the GATE pin of the power management chip U10 is connected with a GATEOUT circuit, the ISENSE pin of the power management chip U10 is respectively connected with a resistor R77 and a capacitor C87, the other end of the resistor R77 is connected with PV-ground, the other end of the capacitor C87 is connected with PGND ground, the VCC pin of the power management chip U10 is respectively connected with a capacitor C88 and a capacitor C89, the capacitor C88 and the capacitor C89 are connected in parallel, the pin of the power management chip U10 is connected with the VCC circuit, and the GND pin and the PGND ground are connected;
The BOP/OVP pin of the power management chip U10 is respectively connected with a resistor R81 and a resistor R84, the resistor R84 and a capacitor C92 are connected in parallel and then connected with PGND, the other end of the resistor R81 is connected with a resistor R80, the other end of the resistor R80 is respectively connected with the cathode of a diode D12 and the cathode of a diode D13, the anode of the diode D12 is connected with an AC-LL circuit, and the anode of the diode D13 is connected with an AC-N circuit;
the silicon carbide driving circuit comprises a power management chip gate driver U11, a power management chip gate driver U13, a first switching power supply and a second switching power supply;
the two GND1 pins of the power management chip gate driver U11 are connected with each other and connected with GND ground, the ADJA pin of the power management chip gate driver U11 is connected with a resistor R99, and the other end of the resistor R99 is connected with the GND1 pin of the power management chip gate driver U11;
the ADJB pin of the power management chip gate driver U11 is connected with a resistor R100, and the other end of the resistor R100 is connected to the GND1 pin of the power management chip gate driver U11;
the RDYC pin of the power management chip gate driver U11 is respectively connected with a resistor R95 and a capacitor C98, the other end of the resistor R95 is connected with +5V voltage, and the other end of the capacitor C98 is connected to the GND1 pin of the power management chip gate driver U11;
The FLT_N pin of the power management chip gate driver U11 is respectively connected with a resistor R91 and a capacitor C99, the other end of the resistor R91 is connected with +5V voltage, and the other end of the capacitor C99 is connected to the GND1 pin of the power management chip gate driver U11;
the IN pin of the power management chip gate driver U11 is respectively connected with a resistor R89 and a capacitor C96, the other end of the resistor R89 is connected with a PWMUTA circuit, and the other end of the capacitor C96 is grounded;
the VCC1 pin of the power management chip gate driver U11 is connected with a capacitor C94 and is connected with +5V voltage, and the other end of the capacitor C94 is grounded;
two VEE2 pins of the power management chip gate driver U11 are connected with each other and connected with VEE2L1 ground in parallel;
the GND2 pin of the power management chip gate driver U11 is connected with the capacitor C102 and connected with GND2L1 in parallel, the other end of the capacitor C102 is connected to the DESAT pin of the power management chip gate driver U11 and a resistor R90, the other end of the resistor R90 is connected with the positive electrode of the diode D14, and the negative electrode of the diode D14 is connected with the VA+ circuit;
the CLAMPDRV pin of the power management chip gate driver U11 is respectively connected with a resistor R96 and the grid electrode of an NMOS transistor Q8, the other end of the resistor R96 is connected with the positive electrode of a zener diode D15, the source electrode of the NMOS transistor Q8 is connected with VEE2L1 ground and is connected with a DRV UPGND circuit, and the drain electrode of the NMOS transistor Q8 is connected with the DRV UP circuit;
The OFF pin of the power management chip gate driver U11 is connected with a resistor R94, and the other end of the resistor R94 is connected with a DRV UP circuit;
the ON pin of the power management chip gate driver U11 is connected with a resistor R92, and the other end of the resistor R92 is connected with a DRV UP circuit;
the VCC2 pin of the power management chip gate driver U11 is respectively connected with a capacitor C95, a capacitor C93 and a VCCL1 circuit, and the other ends of the capacitor C95 and the capacitor C93 are connected with each other in parallel with VEE2L1 ground;
the VIN pin of the first switching power supply is connected with 24V voltage, the GND pin of the first switching power supply is connected with a 12VM circuit, the-VO pin of the first switching power supply is connected with the negative electrode of a polar capacitor C103 in parallel connection with VEE2L1 ground, the 0V pin of the first switching power supply is connected with the positive electrode of the polar capacitor C103, the negative electrode of the polar capacitor C100 in parallel connection with GND2L1 ground, and the +VO pin of the first switching power supply is connected with the positive electrode of the polar capacitor C100 in parallel connection with the VCCL1 circuit;
the two GND1 pins of the power management chip gate driver U13 are connected with each other and connected with GND ground, the ADJA pin of the power management chip gate driver U13 is connected with a resistor R110, and the other end of the resistor R110 is connected with the GND1 pin of the power management chip gate driver U13;
the ADJB pin of the power management chip gate driver U13 is connected with a resistor R111, and the other end of the resistor R111 is connected to the GND1 pin of the power management chip gate driver U13;
The RDYC pin of the power management chip gate driver U13 is respectively connected with a resistor R108 and a capacitor C114, the other end of the resistor R108 is connected with +5V voltage, and the other end of the capacitor C114 is connected with the GND1 pin of the power management chip gate driver U13;
the FLT_N pin of the power management chip gate driver U13 is respectively connected with a resistor R104 and a capacitor C115, the other end of the resistor R104 is connected with +5V voltage, and the other end of the capacitor C115 is connected to the GND1 pin of the power management chip gate driver U13;
the IN pin of the power management chip gate driver U13 is respectively connected with a resistor R102 and a capacitor C112, the other end of the resistor R102 is connected with a PWMUTB circuit, and the other end of the capacitor C112 is grounded;
the VCC1 pin of the power management chip gate driver U13 is connected with a capacitor C110 and is connected with +5V voltage, and the other end of the capacitor C110 is grounded;
two VEE2 pins of the power management chip gate driver U13 are connected with each other and connected with VEE2L2 ground in parallel;
the GND2 pin of the power management chip gate driver U13 is connected with a capacitor C117 and connected with GND2L2 IN parallel, the other end of the capacitor C117 is connected to the DESAT pin of the power management chip gate driver U13 and a resistor R103, the other end of the resistor R103 is connected with the positive electrode of a diode D16, and the negative electrode of the diode D16 is connected with an IN2 circuit;
The CLAMPDRV pin of the power management chip gate driver U13 is respectively connected with a resistor R109 and the grid electrode of an NMOS transistor Q10, the other end of the resistor R109 is connected with the anode of a zener diode D17, the source electrode of the NMOS transistor Q10 is connected with VEE2L2 ground and PGND ground, and the drain electrode of the NMOS transistor Q10 is connected with a DRV DOWN circuit;
the OFF pin of the power management chip gate driver U13 is connected with a resistor R107, and the other end of the resistor R107 is connected with a DRV DOWN circuit;
the ON pin of the power management chip gate driver U13 is connected with a resistor R105, and the other end of the resistor R105 is connected with a DRV DOWN circuit;
the VCC2 pin of the power management chip gate driver U13 is respectively connected with a capacitor C108, a capacitor C111 and a VCCL2 circuit, and the other ends of the capacitor C108 and the capacitor C111 are connected with each other and connected with VEE2L2 ground in parallel;
the VIN pin of the second switching power supply is connected with 24V voltage, the GND pin of the second switching power supply is connected with a 12VM circuit, the-VO pin of the second switching power supply is connected with the negative electrode of a polar capacitor C118 in parallel connection with VEE2L2 ground, the 0V pin of the second switching power supply is connected with the positive electrode of the polar capacitor C118, the negative electrode of the polar capacitor C116 in parallel connection with GND2L2 ground, and the +VO pin of the second switching power supply is connected with the positive electrode of the polar capacitor C116 in parallel connection with the VCCL2 circuit;
the isolation silicon carbide driving module comprises a common mode inductor T3, a resistor R101 is connected between a first coil 1 pin of the common mode inductor T3 and a first coil 2 pin of the common mode inductor T3, a second coil 5 pin of the common mode inductor T3 is connected to a drain electrode of an NMOS transistor Q9, a source electrode of the NMOS transistor Q9 is connected with PGND, a resistor R106 is also connected between a grid electrode of the NMOS transistor Q9 and a source electrode of the NMOS transistor Q9, and a grid electrode of the NMOS transistor Q9 is connected with a DRV DOWN circuit;
The second coil 8 pin of the common-mode inductor T3 is respectively connected with a DRV UPGND circuit and the source electrode of an NMOS transistor Q7, the drain electrode of the NMOS transistor Q7 is connected with a VA+ circuit, the grid electrode of the NMOS transistor Q7 is connected with the DRV UP circuit, and a resistor R93 is also connected between the grid electrode of the NMOS transistor Q7 and the source electrode of the NMOS transistor Q7;
the second coil 7 pin and the second coil 6 pin of the common-mode inductor T3 are connected with each other and are respectively connected with a capacitor C97, a capacitor C101, a capacitor C104 and a capacitor C106, the capacitor C97, the capacitor C101 and the capacitor C104 are connected in parallel and then are connected with a first switch L10, and the other end of the capacitor C106 is connected with a second switch L13;
the other ends of the first switch L10 and the second switch L13 are connected to each other and to the impedance matching circuit.
Furthermore, the silicon carbide driving circuit is also provided with a protection circuit, and the output end of the protection circuit is connected to the FPGA module.
Furthermore, the communication interface of the DSP main control chip is communicated with a communication module.
Furthermore, a FLASH interface of the DSP main control chip is connected with a FLASH module.
Furthermore, the DSP main control chip is also connected with an HMI human-computer interface.
Further, the voltage feedback circuit is respectively connected to the OUTA_I_2 circuit, the OUTA_I_1 circuit and the VoOutFK circuit of the impedance matching circuit;
The other end of the resistor R54 is respectively connected with a capacitor C76 and the negative electrode of a voltage stabilizing diode D2, the other end of the capacitor C76 is connected to the base electrode of a triode Q2, a resistor R48 is connected between the collector electrode of the triode Q2 and the base electrode of the triode Q2, the collector electrode of the triode Q2 is connected with 12V voltage, the positive electrode of the voltage stabilizing diode D2 is connected with the positive electrode of the voltage stabilizing diode D3, the negative electrode of the voltage stabilizing diode D3 is grounded and connected to the circuit OUTA_I_1, the emitter electrode of the triode Q2 is respectively connected with a capacitor C77 and a resistor R58, the other end of the resistor R58 is grounded, the other end of the capacitor C77 is connected with a resistor R57, the other end of the resistor R57 is respectively connected with a capacitor C78, a capacitor C79, a resistor R59 and an inductor L5, the other end of the resistor R78 is respectively connected with the resistor R55, the other end of the resistor R60 and the base electrode of the triode Q3, the other end of the resistor R60 is respectively connected with the resistor R79, the other end of the resistor R61 and the other end of the resistor R5 is connected with the resistor R61;
the other end of the resistor R55 is connected with 12V voltage and a resistor R50, the other end of the resistor R50 is respectively connected with a capacitor C75 and a collector of a triode Q3, the other end of the capacitor C75 is respectively connected with a resistor R49 and a base of a triode Q1, and the other end of the resistor R49 is connected to the other end of the adjustable resistor VR 5;
The collector of the triode Q1 is connected with a resistor R45, the other end of the resistor R45 is connected with 12V voltage, the emitter of the triode Q1 is respectively connected with a capacitor C73 and a resistor R47, the other end of the capacitor C73 is connected with a resistor R46, the other end of the resistor R46 is respectively connected with a resistor R44 and an inverting input end of an operational amplifier U8B, the other end of the resistor R47 is grounded and is respectively connected with a capacitor C74 and a resistor R52, the capacitor C74 and the resistor R52 are respectively connected with an non-inverting input end of the operational amplifier U8B, a resistor R51 and a resistor R56 after being connected in parallel, the other end of the resistor R51 is connected with 12V voltage, the other end of the resistor R56 is respectively connected with a non-inverting input end of the operational amplifier U9B and a resistor R53, the other end of the resistor R53 is connected with an output end of the operational amplifier U9B and is connected with a CURFK circuit in parallel, and the other end of the resistor R44 is connected with an output end of the operational amplifier U8B and an inverting input end of the operational amplifier U9B;
the VoOutFK circuit is connected with a resistor R64, the other end of the resistor R64 is respectively connected with a capacitor C80 and the cathode of a voltage stabilizing diode D4, the anode of the voltage stabilizing diode D4 is connected with the anode of a voltage stabilizing diode D5, the cathode of the voltage stabilizing diode D5 is grounded, the other end of the capacitor C80 is respectively connected with a triode Q4 and a resistor R62, the collector of the triode Q4 is connected with the other end of the resistor R62 and is connected with 12V voltage, the emitter of the triode Q4 is respectively connected with a capacitor C81 and a resistor R67, the other end of the resistor R67 is grounded, the other end of the capacitor C81 is connected with a resistor R65, the other end of the resistor R65 is respectively connected with an inductor L6, a capacitor C83, a resistor R68 and a capacitor C82, the other end of the inductor L6 is grounded, the capacitor C83 and the resistor R68 are connected in parallel and then connected to the grounded end of the inductor L6, the other end of the capacitor C82 is connected with the resistor R66, the other end of the resistor R66 is connected to the inverting input end of the operational amplifier U8A and the resistor R63, the output end of the operational amplifier U8A is connected with the other end of the resistor R63, the 8 pin of the operational amplifier U8A is connected with 12V voltage, the 4 pin of the operational amplifier U8A is grounded, the grounded end of the inductor L6 is also connected with the capacitor C84 and the resistor R71 respectively, the capacitor C84 and the resistor R71 are connected in parallel and then connected to the non-inverting input end of the operational amplifier U8A, the resistor R70 and the resistor R72 respectively, and the other end of the resistor R70 is connected with 12V voltage;
The output end of the operational amplifier U8A is connected with the inverting input end of the operational amplifier U9A, the non-inverting input end of the operational amplifier U9A is respectively connected with the other end of the resistor R72 and the resistor R69, the other end of the resistor R69 is connected to the output end of the operational amplifier U9A and the VOLFK circuit, the 8 pin of the operational amplifier U9A is connected with 12V voltage, and the 4 pin of the operational amplifier U9A is connected with GND.
Compared with the prior art, the invention has the beneficial effects that: the megasonic power system based on the DSP and the FPGA integrates a DSP floating point algorithm, and an FPGA programmable hardware logic is added to realize a closed loop frequency tracking control architecture for high-frequency, high-speed and high-precision frequency execution.
Drawings
Fig. 1 is a diagram of the general circuit architecture of the megasonic power supply system of the present invention.
Fig. 2 is a diagram of an EMI filter circuit of the present invention.
Fig. 3-4 are circuit diagrams of PFC according to the present invention.
Fig. 5 to 8 are diagrams of driving circuits according to the present invention.
Fig. 9-11 are diagrams of silicon carbide driving circuits according to the present invention.
Fig. 12 is a circuit diagram of a DSP according to the present invention.
Fig. 13 is an enlarged view of the left side circuit of fig. 12.
Fig. 14 is an enlarged view of the upper circuit of fig. 12.
Fig. 15 is an enlarged view of the right circuit of fig. 12.
Fig. 16 is an enlarged view of the lower circuit of fig. 12.
Fig. 17-18 are feedback circuit diagrams of the present invention.
Fig. 19 is a diagram of an impedance matching circuit according to the present invention.
Fig. 20-21 are circuit diagrams of FPGAs of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and thus the protection scope of the present invention is more clearly and clearly defined. It should be apparent that the described embodiments of the invention are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1: the specific structure of the invention is as follows:
referring to fig. 1-21, a megasonic power supply system based on DSP and FPGA of the present invention includes:
the input end of the EMI filter circuit is connected with the mains supply, the mains supply is filtered through two fuses, a filter capacitor and a common mode inductor in sequence, then the filter circuit is slowly started through a relay, and finally the first voltage V1 is output through a bridge rectifier circuit;
The PFC circuit is used for carrying out power factor correction on the first voltage V1, is connected to the output end of the bridge rectifier circuit, and boosts the first voltage V1 to the second voltage V2;
the silicon carbide driving circuit is connected to the output end of the PFC circuit, the silicon carbide driving circuit is outwards output through a silicon carbide driving transformer, the transformer is an isolation transformer, the silicon carbide driving circuit is provided with an isolation silicon carbide driving module and a silicon carbide power tube, and the input end of the isolation silicon carbide driving module is connected with the silicon carbide power tube;
the input end of the impedance matching circuit is connected with the output end of the isolation transformer, and the output end of the impedance matching circuit is connected to the megasonic vibrating plate;
the voltage feedback circuit reads the output voltage and current phase of the isolation transformer, sends the output voltage and current phase to the FPGA module for logic analysis, analyzes the phase value, and detects the output voltage value in real time, and the output end of the voltage feedback circuit is connected to a signal waveform shaping module;
the current feedback circuit is connected to the output end of the impedance matching circuit, the output end of the current feedback circuit is connected to the signal waveform shaping module, and the signal waveform shaping module transmits a voltage signal and a current signal to the FPGA module;
The DSP circuit is connected with a DSP main control chip, and the DSP main control chip processes the incoming data signals and transmits the processed signals to a buffer area of the FPGA module;
the PFC circuit comprises an inductor L7, a resistor R28, a diode D8, a diode D7, a capacitor C16, a resistor R25, a capacitor C35, a capacitor C85, a capacitor C86, an NMOS transistor Q6, a resistor R73, a resistor R74, a resistor R75 and a diode D9, wherein one end of the inductor L7 is connected with 300V voltage, the other end of the inductor L7 is connected with the anode of the diode D7 in a connecting mode, the capacitor C16 and the resistor R25 are connected in series and then connected with the diode D7 in parallel, one end of the resistor R28 is connected with 300V voltage, the other end of the resistor R28 is connected with the diode D8 in series, and the cathode of the diode D8 is connected to the cathode of the diode D7;
the negative electrode of the diode D7 is respectively connected with the capacitor C35, the capacitor C85 and the capacitor C86, and the other ends of the capacitor C35, the capacitor C85 and the capacitor C86 are respectively connected with PGND ground;
the cathode of the diode D7 is also connected with a VA+ circuit, and the anode of the diode D is connected with a VPFCO circuit and the drain electrode of the NMOS transistor Q6;
the source electrode of the NMOS transistor Q6 is connected with one end of the resistor R75 in parallel connection with PGND, the grid electrode of the NMOS transistor Q is respectively connected with a resistor R73 and a resistor R74, the other end of the resistor R75 is connected with PV-ground, the other end of the resistor R74 is connected with the positive electrode of the diode D9, the negative electrode of the diode D9 is connected with the other end of the resistor R73, and the negative electrode of the diode D9 is also connected with a GATEOUT2 circuit;
The VA+ circuit is connected with a resistor R78, and the other end of the resistor R78 is connected with a resistor R79;
two ends of the resistor R83, the resistor R85 and the capacitor C91 which are connected in parallel are respectively connected to the other end of the resistor R79 and connected with the GND pin of the power management chip U10;
the ICOMP pin of the power management chip U10 is connected with a capacitor C90, the capacitor C90 pin is connected with the GND pin of the power management chip U10, the FREQ pin of the power management chip U10 is connected with a resistor R82, the other end of the resistor R82 is connected with the GND pin of the power management chip U10, the VSENSE pin of the power management chip U10 is connected with the voltage output end of the resistor R79, the GATE pin of the power management chip U10 is connected with a GATEOUT circuit, the ISENSE pin of the power management chip U10 is respectively connected with a resistor R77 and a capacitor C87, the other end of the resistor R77 is connected with PV-ground, the other end of the capacitor C87 is connected with PGND ground, the VCC pin of the power management chip U10 is respectively connected with a capacitor C88 and a capacitor C89, the capacitor C88 and the capacitor C89 are connected in parallel, the pin of the power management chip U10 is connected with the VCC circuit, and the GND pin and the PGND ground are connected;
the BOP/OVP pin of the power management chip U10 is respectively connected with a resistor R81 and a resistor R84, the resistor R84 and a capacitor C92 are connected in parallel and then connected with PGND, the other end of the resistor R81 is connected with a resistor R80, the other end of the resistor R80 is respectively connected with the cathode of a diode D12 and the cathode of a diode D13, the anode of the diode D12 is connected with an AC-LL circuit, and the anode of the diode D13 is connected with an AC-N circuit;
The silicon carbide driving circuit comprises a power management chip gate driver U11, a power management chip gate driver U13, a first switching power supply and a second switching power supply;
the two GND1 pins of the power management chip gate driver U11 are connected with each other and connected with GND ground, the ADJA pin of the power management chip gate driver U11 is connected with a resistor R99, and the other end of the resistor R99 is connected with the GND1 pin of the power management chip gate driver U11;
the ADJB pin of the power management chip gate driver U11 is connected with a resistor R100, and the other end of the resistor R100 is connected to the GND1 pin of the power management chip gate driver U11;
the RDYC pin of the power management chip gate driver U11 is respectively connected with a resistor R95 and a capacitor C98, the other end of the resistor R95 is connected with +5V voltage, and the other end of the capacitor C98 is connected to the GND1 pin of the power management chip gate driver U11;
the FLT_N pin of the power management chip gate driver U11 is respectively connected with a resistor R91 and a capacitor C99, the other end of the resistor R91 is connected with +5V voltage, and the other end of the capacitor C99 is connected to the GND1 pin of the power management chip gate driver U11;
the IN pin of the power management chip gate driver U11 is respectively connected with a resistor R89 and a capacitor C96, the other end of the resistor R89 is connected with a PWMUTA circuit, and the other end of the capacitor C96 is grounded;
The VCC1 pin of the power management chip gate driver U11 is connected with a capacitor C94 and is connected with +5V voltage, and the other end of the capacitor C94 is grounded;
two VEE2 pins of the power management chip gate driver U11 are connected with each other and connected with VEE2L1 ground in parallel;
the GND2 pin of the power management chip gate driver U11 is connected with the capacitor C102 and connected with GND2L1 in parallel, the other end of the capacitor C102 is connected to the DESAT pin of the power management chip gate driver U11 and a resistor R90, the other end of the resistor R90 is connected with the positive electrode of the diode D14, and the negative electrode of the diode D14 is connected with the VA+ circuit;
the CLAMPDRV pin of the power management chip gate driver U11 is respectively connected with a resistor R96 and the grid electrode of an NMOS transistor Q8, the other end of the resistor R96 is connected with the positive electrode of a zener diode D15, the source electrode of the NMOS transistor Q8 is connected with VEE2L1 ground and is connected with a DRV UPGND circuit, and the drain electrode of the NMOS transistor Q8 is connected with the DRV UP circuit;
the OFF pin of the power management chip gate driver U11 is connected with a resistor R94, and the other end of the resistor R94 is connected with a DRV UP circuit;
the ON pin of the power management chip gate driver U11 is connected with a resistor R92, and the other end of the resistor R92 is connected with a DRV UP circuit;
the VCC2 pin of the power management chip gate driver U11 is respectively connected with a capacitor C95, a capacitor C93 and a VCCL1 circuit, and the other ends of the capacitor C95 and the capacitor C93 are connected with each other in parallel with VEE2L1 ground;
The VIN pin of the first switching power supply is connected with 24V voltage, the GND pin of the first switching power supply is connected with a 12VM circuit, the-VO pin of the first switching power supply is connected with the negative electrode of a polar capacitor C103 in parallel connection with VEE2L1 ground, the 0V pin of the first switching power supply is connected with the positive electrode of the polar capacitor C103, the negative electrode of the polar capacitor C100 in parallel connection with GND2L1 ground, and the +VO pin of the first switching power supply is connected with the positive electrode of the polar capacitor C100 in parallel connection with the VCCL1 circuit;
the two GND1 pins of the power management chip gate driver U13 are connected with each other and connected with GND ground, the ADJA pin of the power management chip gate driver U13 is connected with a resistor R110, and the other end of the resistor R110 is connected with the GND1 pin of the power management chip gate driver U13;
the ADJB pin of the power management chip gate driver U13 is connected with a resistor R111, and the other end of the resistor R111 is connected to the GND1 pin of the power management chip gate driver U13;
the RDYC pin of the power management chip gate driver U13 is respectively connected with a resistor R108 and a capacitor C114, the other end of the resistor R108 is connected with +5V voltage, and the other end of the capacitor C114 is connected with the GND1 pin of the power management chip gate driver U13;
the FLT_N pin of the power management chip gate driver U13 is respectively connected with a resistor R104 and a capacitor C115, the other end of the resistor R104 is connected with +5V voltage, and the other end of the capacitor C115 is connected to the GND1 pin of the power management chip gate driver U13;
The IN pin of the power management chip gate driver U13 is respectively connected with a resistor R102 and a capacitor C112, the other end of the resistor R102 is connected with a PWMUTB circuit, and the other end of the capacitor C112 is grounded;
the VCC1 pin of the power management chip gate driver U13 is connected with a capacitor C110 and is connected with +5V voltage, and the other end of the capacitor C110 is grounded;
two VEE2 pins of the power management chip gate driver U13 are connected with each other and connected with VEE2L2 ground in parallel;
the GND2 pin of the power management chip gate driver U13 is connected with a capacitor C117 and connected with GND2L2 IN parallel, the other end of the capacitor C117 is connected to the DESAT pin of the power management chip gate driver U13 and a resistor R103, the other end of the resistor R103 is connected with the positive electrode of a diode D16, and the negative electrode of the diode D16 is connected with an IN2 circuit;
the CLAMPDRV pin of the power management chip gate driver U13 is respectively connected with a resistor R109 and the grid electrode of an NMOS transistor Q10, the other end of the resistor R109 is connected with the anode of a zener diode D17, the source electrode of the NMOS transistor Q10 is connected with VEE2L2 ground and PGND ground, and the drain electrode of the NMOS transistor Q10 is connected with a DRV DOWN circuit;
the OFF pin of the power management chip gate driver U13 is connected with a resistor R107, and the other end of the resistor R107 is connected with a DRV DOWN circuit;
The ON pin of the power management chip gate driver U13 is connected with a resistor R105, and the other end of the resistor R105 is connected with a DRV DOWN circuit;
the VCC2 pin of the power management chip gate driver U13 is respectively connected with a capacitor C108, a capacitor C111 and a VCCL2 circuit, and the other ends of the capacitor C108 and the capacitor C111 are connected with each other and connected with VEE2L2 ground in parallel;
the VIN pin of the second switching power supply is connected with 24V voltage, the GND pin of the second switching power supply is connected with a 12VM circuit, the-VO pin of the second switching power supply is connected with the negative electrode of a polar capacitor C118 in parallel connection with VEE2L2 ground, the 0V pin of the second switching power supply is connected with the positive electrode of the polar capacitor C118, the negative electrode of the polar capacitor C116 in parallel connection with GND2L2 ground, and the +VO pin of the second switching power supply is connected with the positive electrode of the polar capacitor C116 in parallel connection with the VCCL2 circuit;
the isolation silicon carbide driving module comprises a common mode inductor T3, a resistor R101 is connected between a first coil 1 pin of the common mode inductor T3 and a first coil 2 pin of the common mode inductor T3, a second coil 5 pin of the common mode inductor T3 is connected to a drain electrode of an NMOS transistor Q9, a source electrode of the NMOS transistor Q9 is connected with PGND, a resistor R106 is also connected between a grid electrode of the NMOS transistor Q9 and a source electrode of the NMOS transistor Q9, and a grid electrode of the NMOS transistor Q9 is connected with a DRV DOWN circuit;
the second coil 8 pin of the common-mode inductor T3 is respectively connected with a DRV UPGND circuit and the source electrode of an NMOS transistor Q7, the drain electrode of the NMOS transistor Q7 is connected with a VA+ circuit, the grid electrode of the NMOS transistor Q7 is connected with the DRV UP circuit, and a resistor R93 is also connected between the grid electrode of the NMOS transistor Q7 and the source electrode of the NMOS transistor Q7;
The second coil 7 pin and the second coil 6 pin of the common-mode inductor T3 are connected with each other and are respectively connected with a capacitor C97, a capacitor C101, a capacitor C104 and a capacitor C106, the capacitor C97, the capacitor C101 and the capacitor C104 are connected in parallel and then are connected with a first switch L10, and the other end of the capacitor C106 is connected with a second switch L13;
the other ends of the first switch L10 and the second switch L13 are connected to each other and to the impedance matching circuit.
A preferred technical scheme of the embodiment is as follows: the silicon carbide driving circuit is also provided with a protection circuit, and the output end of the protection circuit is connected to the FPGA module.
A preferred technical scheme of the embodiment is as follows: the communication interface of the DSP main control chip is communicated with the communication module.
A preferred technical scheme of the embodiment is as follows: and a FLASH interface of the DSP main control chip is connected with a FLASH module.
A preferred technical scheme of the embodiment is as follows: and the DSP main control chip is also connected with an HMI human-computer interface.
A preferred technical scheme of the embodiment is as follows: the voltage feedback circuit is respectively connected with the OUTA_I_2 circuit, the OUTA_I_1 circuit and the VoOutFK circuit of the impedance matching circuit;
the other end of the resistor R54 is respectively connected with a capacitor C76 and the negative electrode of a voltage stabilizing diode D2, the other end of the capacitor C76 is connected to the base electrode of a triode Q2, a resistor R48 is connected between the collector electrode of the triode Q2 and the base electrode of the triode Q2, the collector electrode of the triode Q2 is connected with 12V voltage, the positive electrode of the voltage stabilizing diode D2 is connected with the positive electrode of the voltage stabilizing diode D3, the negative electrode of the voltage stabilizing diode D3 is grounded and connected to the circuit OUTA_I_1, the emitter electrode of the triode Q2 is respectively connected with a capacitor C77 and a resistor R58, the other end of the resistor R58 is grounded, the other end of the capacitor C77 is connected with a resistor R57, the other end of the resistor R57 is respectively connected with a capacitor C78, a capacitor C79, a resistor R59 and an inductor L5, the other end of the resistor R78 is respectively connected with the resistor R55, the other end of the resistor R60 and the base electrode of the triode Q3, the other end of the resistor R60 is respectively connected with the resistor R79, the other end of the resistor R61 and the other end of the resistor R5 is connected with the resistor R61;
The other end of the resistor R55 is connected with 12V voltage and a resistor R50, the other end of the resistor R50 is respectively connected with a capacitor C75 and a collector of a triode Q3, the other end of the capacitor C75 is respectively connected with a resistor R49 and a base of a triode Q1, and the other end of the resistor R49 is connected to the other end of the adjustable resistor VR 5;
the collector of the triode Q1 is connected with a resistor R45, the other end of the resistor R45 is connected with 12V voltage, the emitter of the triode Q1 is respectively connected with a capacitor C73 and a resistor R47, the other end of the capacitor C73 is connected with a resistor R46, the other end of the resistor R46 is respectively connected with a resistor R44 and an inverting input end of an operational amplifier U8B, the other end of the resistor R47 is grounded and is respectively connected with a capacitor C74 and a resistor R52, the capacitor C74 and the resistor R52 are respectively connected with an non-inverting input end of the operational amplifier U8B, a resistor R51 and a resistor R56 after being connected in parallel, the other end of the resistor R51 is connected with 12V voltage, the other end of the resistor R56 is respectively connected with a non-inverting input end of the operational amplifier U9B and a resistor R53, the other end of the resistor R53 is connected with an output end of the operational amplifier U9B and is connected with a CURFK circuit in parallel, and the other end of the resistor R44 is connected with an output end of the operational amplifier U8B and an inverting input end of the operational amplifier U9B;
The VoOutFK circuit is connected with a resistor R64, the other end of the resistor R64 is respectively connected with a capacitor C80 and the cathode of a voltage stabilizing diode D4, the anode of the voltage stabilizing diode D4 is connected with the anode of a voltage stabilizing diode D5, the cathode of the voltage stabilizing diode D5 is grounded, the other end of the capacitor C80 is respectively connected with a triode Q4 and a resistor R62, the collector of the triode Q4 is connected with the other end of the resistor R62 and is connected with 12V voltage, the emitter of the triode Q4 is respectively connected with a capacitor C81 and a resistor R67, the other end of the resistor R67 is grounded, the other end of the capacitor C81 is connected with a resistor R65, the other end of the resistor R65 is respectively connected with an inductor L6, a capacitor C83, a resistor R68 and a capacitor C82, the other end of the inductor L6 is grounded, the capacitor C83 and the resistor R68 are connected in parallel and then connected to the grounded end of the inductor L6, the other end of the capacitor C82 is connected with the resistor R66, the other end of the resistor R66 is connected to the inverting input end of the operational amplifier U8A and the resistor R63, the output end of the operational amplifier U8A is connected with the other end of the resistor R63, the 8 pin of the operational amplifier U8A is connected with 12V voltage, the 4 pin of the operational amplifier U8A is grounded, the grounded end of the inductor L6 is also connected with the capacitor C84 and the resistor R71 respectively, the capacitor C84 and the resistor R71 are connected in parallel and then connected to the non-inverting input end of the operational amplifier U8A, the resistor R70 and the resistor R72 respectively, and the other end of the resistor R70 is connected with 12V voltage;
The output end of the operational amplifier U8A is connected with the inverting input end of the operational amplifier U9A, the non-inverting input end of the operational amplifier U9A is respectively connected with the other end of the resistor R72 and the resistor R69, the other end of the resistor R69 is connected to the output end of the operational amplifier U9A and the VOLFK circuit, the 8 pin of the operational amplifier U9A is connected with 12V voltage, and the 4 pin of the operational amplifier U9A is connected with GND.
In summary, the megasonic power system based on the DSP and the FPGA integrates the DSP floating point algorithm and adds FPGA programmable hardware logic to realize a closed-loop frequency tracking control architecture for high-frequency, high-speed and high-precision frequency execution.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the invention.
Claims (6)
1. A megasonic power supply system based on a DSP and an FPGA, comprising:
the input end of the EMI filter circuit is connected with the mains supply, the mains supply is filtered through two fuses, a filter capacitor and a common mode inductor in sequence, then the filter circuit is slowly started through a relay, and finally the first voltage V1 is output through a bridge rectifier circuit;
The PFC circuit is used for carrying out power factor correction on the first voltage V1, is connected to the output end of the bridge rectifier circuit, and boosts the first voltage V1 to the second voltage V2;
the silicon carbide driving circuit is connected to the output end of the PFC circuit, the silicon carbide driving circuit is outwards output through a silicon carbide driving transformer, the transformer is an isolation transformer, the silicon carbide driving circuit is provided with an isolation silicon carbide driving module and a silicon carbide power tube, and the input end of the isolation silicon carbide driving module is connected with the silicon carbide power tube;
the input end of the impedance matching circuit is connected with the output end of the isolation transformer, and the output end of the impedance matching circuit is connected to the megasonic vibrating plate;
the voltage feedback circuit reads the output voltage and current phase of the isolation transformer, sends the output voltage and current phase to the FPGA module for logic analysis, analyzes the phase value, and detects the output voltage value in real time, and the output end of the voltage feedback circuit is connected to a signal waveform shaping module;
the current feedback circuit is connected to the output end of the impedance matching circuit, the output end of the current feedback circuit is connected to the signal waveform shaping module, and the signal waveform shaping module transmits a voltage signal and a current signal to the FPGA module;
The DSP circuit is connected with a DSP main control chip, and the DSP main control chip processes the incoming data signals and transmits the processed signals to a buffer area of the FPGA module;
the PFC circuit comprises an inductor L7, a resistor R28, a diode D8, a diode D7, a capacitor C16, a resistor R25, a capacitor C35, a capacitor C85, a capacitor C86, an NMOS transistor Q6, a resistor R73, a resistor R74, a resistor R75 and a diode D9, wherein one end of the inductor L7 is connected with 300V voltage, the other end of the inductor L7 is connected with the anode of the diode D7 in a connecting mode, the capacitor C16 and the resistor R25 are connected in series and then connected with the diode D7 in parallel, one end of the resistor R28 is connected with 300V voltage, the other end of the resistor R28 is connected with the diode D8 in series, and the cathode of the diode D8 is connected to the cathode of the diode D7;
the negative electrode of the diode D7 is respectively connected with the capacitor C35, the capacitor C85 and the capacitor C86, and the other ends of the capacitor C35, the capacitor C85 and the capacitor C86 are respectively connected with PGND ground;
the cathode of the diode D7 is also connected with a VA+ circuit, and the anode of the diode D is connected with a VPFCO circuit and the drain electrode of the NMOS transistor Q6;
the source electrode of the NMOS transistor Q6 is connected with one end of the resistor R75 in parallel connection with PGND, the grid electrode of the NMOS transistor Q is respectively connected with a resistor R73 and a resistor R74, the other end of the resistor R75 is connected with PV-ground, the other end of the resistor R74 is connected with the positive electrode of the diode D9, the negative electrode of the diode D9 is connected with the other end of the resistor R73, and the negative electrode of the diode D9 is also connected with a GATEOUT2 circuit;
The VA+ circuit is connected with a resistor R78, and the other end of the resistor R78 is connected with a resistor R79;
two ends of the resistor R83, the resistor R85 and the capacitor C91 which are connected in parallel are respectively connected to the other end of the resistor R79 and connected with the GND pin of the power management chip U10;
the ICOMP pin of the power management chip U10 is connected with a capacitor C90, the capacitor C90 pin is connected with the GND pin of the power management chip U10, the FREQ pin of the power management chip U10 is connected with a resistor R82, the other end of the resistor R82 is connected with the GND pin of the power management chip U10, the VSENSE pin of the power management chip U10 is connected with the voltage output end of the resistor R79, the GATE pin of the power management chip U10 is connected with a GATEOUT circuit, the ISENSE pin of the power management chip U10 is respectively connected with a resistor R77 and a capacitor C87, the other end of the resistor R77 is connected with PV-ground, the other end of the capacitor C87 is connected with PGND ground, the VCC pin of the power management chip U10 is respectively connected with a capacitor C88 and a capacitor C89, the capacitor C88 and the capacitor C89 are connected in parallel, the pin of the power management chip U10 is connected with the VCC circuit, and the GND pin and the PGND ground are connected;
the BOP/OVP pin of the power management chip U10 is respectively connected with a resistor R81 and a resistor R84, the resistor R84 and a capacitor C92 are connected in parallel and then connected with PGND, the other end of the resistor R81 is connected with a resistor R80, the other end of the resistor R80 is respectively connected with the cathode of a diode D12 and the cathode of a diode D13, the anode of the diode D12 is connected with an AC-LL circuit, and the anode of the diode D13 is connected with an AC-N circuit;
The silicon carbide driving circuit comprises a power management chip gate driver U11, a power management chip gate driver U13, a first switching power supply and a second switching power supply;
the two GND1 pins of the power management chip gate driver U11 are connected with each other and connected with GND ground, the ADJA pin of the power management chip gate driver U11 is connected with a resistor R99, and the other end of the resistor R99 is connected with the GND1 pin of the power management chip gate driver U11;
the ADJB pin of the power management chip gate driver U11 is connected with a resistor R100, and the other end of the resistor R100 is connected to the GND1 pin of the power management chip gate driver U11;
the RDYC pin of the power management chip gate driver U11 is respectively connected with a resistor R95 and a capacitor C98, the other end of the resistor R95 is connected with +5V voltage, and the other end of the capacitor C98 is connected to the GND1 pin of the power management chip gate driver U11;
the FLT_N pin of the power management chip gate driver U11 is respectively connected with a resistor R91 and a capacitor C99, the other end of the resistor R91 is connected with +5V voltage, and the other end of the capacitor C99 is connected to the GND1 pin of the power management chip gate driver U11;
the IN pin of the power management chip gate driver U11 is respectively connected with a resistor R89 and a capacitor C96, the other end of the resistor R89 is connected with a PWMUTA circuit, and the other end of the capacitor C96 is grounded;
The VCC1 pin of the power management chip gate driver U11 is connected with a capacitor C94 and is connected with +5V voltage, and the other end of the capacitor C94 is grounded;
two VEE2 pins of the power management chip gate driver U11 are connected with each other and connected with VEE2L1 ground in parallel;
the GND2 pin of the power management chip gate driver U11 is connected with the capacitor C102 and connected with GND2L1 in parallel, the other end of the capacitor C102 is connected to the DESAT pin of the power management chip gate driver U11 and a resistor R90, the other end of the resistor R90 is connected with the positive electrode of the diode D14, and the negative electrode of the diode D14 is connected with the VA+ circuit;
the CLAMPDRV pin of the power management chip gate driver U11 is respectively connected with a resistor R96 and the grid electrode of an NMOS transistor Q8, the other end of the resistor R96 is connected with the positive electrode of a zener diode D15, the source electrode of the NMOS transistor Q8 is connected with VEE2L1 ground and is connected with a DRV UPGND circuit, and the drain electrode of the NMOS transistor Q8 is connected with the DRV UP circuit;
the OFF pin of the power management chip gate driver U11 is connected with a resistor R94, and the other end of the resistor R94 is connected with a DRV UP circuit;
the ON pin of the power management chip gate driver U11 is connected with a resistor R92, and the other end of the resistor R92 is connected with a DRV UP circuit;
the VCC2 pin of the power management chip gate driver U11 is respectively connected with a capacitor C95, a capacitor C93 and a VCCL1 circuit, and the other ends of the capacitor C95 and the capacitor C93 are connected with each other in parallel with VEE2L1 ground;
The VIN pin of the first switching power supply is connected with 24V voltage, the GND pin of the first switching power supply is connected with a 12VM circuit, the-VO pin of the first switching power supply is connected with the negative electrode of a polar capacitor C103 in parallel connection with VEE2L1 ground, the 0V pin of the first switching power supply is connected with the positive electrode of the polar capacitor C103, the negative electrode of the polar capacitor C100 in parallel connection with GND2L1 ground, and the +VO pin of the first switching power supply is connected with the positive electrode of the polar capacitor C100 in parallel connection with the VCCL1 circuit;
the two GND1 pins of the power management chip gate driver U13 are connected with each other and connected with GND ground, the ADJA pin of the power management chip gate driver U13 is connected with a resistor R110, and the other end of the resistor R110 is connected with the GND1 pin of the power management chip gate driver U13;
the ADJB pin of the power management chip gate driver U13 is connected with a resistor R111, and the other end of the resistor R111 is connected to the GND1 pin of the power management chip gate driver U13;
the RDYC pin of the power management chip gate driver U13 is respectively connected with a resistor R108 and a capacitor C114, the other end of the resistor R108 is connected with +5V voltage, and the other end of the capacitor C114 is connected with the GND1 pin of the power management chip gate driver U13;
the FLT_N pin of the power management chip gate driver U13 is respectively connected with a resistor R104 and a capacitor C115, the other end of the resistor R104 is connected with +5V voltage, and the other end of the capacitor C115 is connected to the GND1 pin of the power management chip gate driver U13;
The IN pin of the power management chip gate driver U13 is respectively connected with a resistor R102 and a capacitor C112, the other end of the resistor R102 is connected with a PWMUTB circuit, and the other end of the capacitor C112 is grounded;
the VCC1 pin of the power management chip gate driver U13 is connected with a capacitor C110 and is connected with +5V voltage, and the other end of the capacitor C110 is grounded;
two VEE2 pins of the power management chip gate driver U13 are connected with each other and connected with VEE2L2 ground in parallel;
the GND2 pin of the power management chip gate driver U13 is connected with a capacitor C117 and connected with GND2L2 IN parallel, the other end of the capacitor C117 is connected to the DESAT pin of the power management chip gate driver U13 and a resistor R103, the other end of the resistor R103 is connected with the positive electrode of a diode D16, and the negative electrode of the diode D16 is connected with an IN2 circuit;
the CLAMPDRV pin of the power management chip gate driver U13 is respectively connected with a resistor R109 and the grid electrode of an NMOS transistor Q10, the other end of the resistor R109 is connected with the anode of a zener diode D17, the source electrode of the NMOS transistor Q10 is connected with VEE2L2 ground and PGND ground, and the drain electrode of the NMOS transistor Q10 is connected with a DRV DOWN circuit;
the OFF pin of the power management chip gate driver U13 is connected with a resistor R107, and the other end of the resistor R107 is connected with a DRV DOWN circuit;
The ON pin of the power management chip gate driver U13 is connected with a resistor R105, and the other end of the resistor R105 is connected with a DRV DOWN circuit;
the VCC2 pin of the power management chip gate driver U13 is respectively connected with a capacitor C108, a capacitor C111 and a VCCL2 circuit, and the other ends of the capacitor C108 and the capacitor C111 are connected with each other and connected with VEE2L2 ground in parallel;
the VIN pin of the second switching power supply is connected with 24V voltage, the GND pin of the second switching power supply is connected with a 12VM circuit, the-VO pin of the second switching power supply is connected with the negative electrode of a polar capacitor C118 in parallel connection with VEE2L2 ground, the 0V pin of the second switching power supply is connected with the positive electrode of the polar capacitor C118, the negative electrode of the polar capacitor C116 in parallel connection with GND2L2 ground, and the +VO pin of the second switching power supply is connected with the positive electrode of the polar capacitor C116 in parallel connection with the VCCL2 circuit;
the isolation silicon carbide driving module comprises a common mode inductor T3, a resistor R101 is connected between a first coil 1 pin of the common mode inductor T3 and a first coil 2 pin of the common mode inductor T3, a second coil 5 pin of the common mode inductor T3 is connected to a drain electrode of an NMOS transistor Q9, a source electrode of the NMOS transistor Q9 is connected with PGND, a resistor R106 is also connected between a grid electrode of the NMOS transistor Q9 and a source electrode of the NMOS transistor Q9, and a grid electrode of the NMOS transistor Q9 is connected with a DRV DOWN circuit;
the second coil 8 pin of the common-mode inductor T3 is respectively connected with a DRV UPGND circuit and the source electrode of an NMOS transistor Q7, the drain electrode of the NMOS transistor Q7 is connected with a VA+ circuit, the grid electrode of the NMOS transistor Q7 is connected with the DRV UP circuit, and a resistor R93 is also connected between the grid electrode of the NMOS transistor Q7 and the source electrode of the NMOS transistor Q7;
The second coil 7 pin and the second coil 6 pin of the common-mode inductor T3 are connected with each other and are respectively connected with a capacitor C97, a capacitor C101, a capacitor C104 and a capacitor C106, the capacitor C97, the capacitor C101 and the capacitor C104 are connected in parallel and then are connected with a first switch L10, and the other end of the capacitor C106 is connected with a second switch L13;
the other ends of the first switch L10 and the second switch L13 are connected to each other and to the impedance matching circuit.
2. The megasonic power system of claim 1 wherein the silicon carbide driver circuit is further provided with a protection circuit having an output terminal connected to the FPGA module.
3. The megasonic power system of claim 1 wherein the communication interface of the DSP host control chip is connected to the communication module.
4. The megasonic power system based on the DSP and the FPGA as claimed in claim 1, wherein the FLASH interface of the DSP main control chip is connected with a FLASH module.
5. The megasonic power system based on the DSP and the FPGA as claimed in claim 1, wherein the DSP main control chip is also connected with an HMI human-machine interface.
6. The megasonic power supply system according to claim 1, wherein the voltage feedback circuit is connected to the outi_2 circuit, the outi_1 circuit and the voout fk circuit of the impedance matching circuit, respectively;
The other end of the resistor R54 is respectively connected with a capacitor C76 and the negative electrode of a voltage stabilizing diode D2, the other end of the capacitor C76 is connected to the base electrode of a triode Q2, a resistor R48 is connected between the collector electrode of the triode Q2 and the base electrode of the triode Q2, the collector electrode of the triode Q2 is connected with 12V voltage, the positive electrode of the voltage stabilizing diode D2 is connected with the positive electrode of the voltage stabilizing diode D3, the negative electrode of the voltage stabilizing diode D3 is grounded and connected to the circuit OUTA_I_1, the emitter electrode of the triode Q2 is respectively connected with a capacitor C77 and a resistor R58, the other end of the resistor R58 is grounded, the other end of the capacitor C77 is connected with a resistor R57, the other end of the resistor R57 is respectively connected with a capacitor C78, a capacitor C79, a resistor R59 and an inductor L5, the other end of the resistor R78 is respectively connected with the resistor R55, the other end of the resistor R60 and the base electrode of the triode Q3, the other end of the resistor R60 is respectively connected with the resistor R79, the other end of the resistor R61 and the other end of the resistor R5 is connected with the resistor R61;
the other end of the resistor R55 is connected with 12V voltage and a resistor R50, the other end of the resistor R50 is respectively connected with a capacitor C75 and a collector of a triode Q3, the other end of the capacitor C75 is respectively connected with a resistor R49 and a base of a triode Q1, and the other end of the resistor R49 is connected to the other end of the adjustable resistor VR 5;
The collector of the triode Q1 is connected with a resistor R45, the other end of the resistor R45 is connected with 12V voltage, the emitter of the triode Q1 is respectively connected with a capacitor C73 and a resistor R47, the other end of the capacitor C73 is connected with a resistor R46, the other end of the resistor R46 is respectively connected with a resistor R44 and an inverting input end of an operational amplifier U8B, the other end of the resistor R47 is grounded and is respectively connected with a capacitor C74 and a resistor R52, the capacitor C74 and the resistor R52 are respectively connected with an non-inverting input end of the operational amplifier U8B, a resistor R51 and a resistor R56 after being connected in parallel, the other end of the resistor R51 is connected with 12V voltage, the other end of the resistor R56 is respectively connected with a non-inverting input end of the operational amplifier U9B and a resistor R53, the other end of the resistor R53 is connected with an output end of the operational amplifier U9B and is connected with a CURFK circuit in parallel, and the other end of the resistor R44 is connected with an output end of the operational amplifier U8B and an inverting input end of the operational amplifier U9B;
the VoOutFK circuit is connected with a resistor R64, the other end of the resistor R64 is respectively connected with a capacitor C80 and the cathode of a voltage stabilizing diode D4, the anode of the voltage stabilizing diode D4 is connected with the anode of a voltage stabilizing diode D5, the cathode of the voltage stabilizing diode D5 is grounded, the other end of the capacitor C80 is respectively connected with a triode Q4 and a resistor R62, the collector of the triode Q4 is connected with the other end of the resistor R62 and is connected with 12V voltage, the emitter of the triode Q4 is respectively connected with a capacitor C81 and a resistor R67, the other end of the resistor R67 is grounded, the other end of the capacitor C81 is connected with a resistor R65, the other end of the resistor R65 is respectively connected with an inductor L6, a capacitor C83, a resistor R68 and a capacitor C82, the other end of the inductor L6 is grounded, the capacitor C83 and the resistor R68 are connected in parallel and then connected to the grounded end of the inductor L6, the other end of the capacitor C82 is connected with the resistor R66, the other end of the resistor R66 is connected to the inverting input end of the operational amplifier U8A and the resistor R63, the output end of the operational amplifier U8A is connected with the other end of the resistor R63, the 8 pin of the operational amplifier U8A is connected with 12V voltage, the 4 pin of the operational amplifier U8A is grounded, the grounded end of the inductor L6 is also connected with the capacitor C84 and the resistor R71 respectively, the capacitor C84 and the resistor R71 are connected in parallel and then connected to the non-inverting input end of the operational amplifier U8A, the resistor R70 and the resistor R72 respectively, and the other end of the resistor R70 is connected with 12V voltage;
The output end of the operational amplifier U8A is connected with the inverting input end of the operational amplifier U9A, the non-inverting input end of the operational amplifier U9A is respectively connected with the other end of the resistor R72 and the resistor R69, the other end of the resistor R69 is connected to the output end of the operational amplifier U9A and the VOLFK circuit, the 8 pin of the operational amplifier U9A is connected with 12V voltage, and the 4 pin of the operational amplifier U9A is connected with GND.
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| CN202211068438.4A CN115912893B (en) | 2022-09-02 | 2022-09-02 | Megasonic power supply system based on DSP and FPGA |
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| CN115912893A CN115912893A (en) | 2023-04-04 |
| CN115912893B true CN115912893B (en) | 2023-08-22 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110896284A (en) * | 2019-11-21 | 2020-03-20 | 新乡航空工业(集团)有限公司 | Aviation high-voltage high-power three-phase full-control rectifying device based on silicon carbide |
| CN113904566A (en) * | 2021-11-10 | 2022-01-07 | 华芯威半导体科技(北京)有限责任公司 | 200kW vehicle-mounted inverter controller based on SIC power module |
| CN217063572U (en) * | 2022-03-09 | 2022-07-26 | 易事特集团股份有限公司 | Drive circuit of silicon carbide device |
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| EP3849083A1 (en) * | 2020-01-07 | 2021-07-14 | Hamilton Sundstrand Corporation | Gate driver |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110896284A (en) * | 2019-11-21 | 2020-03-20 | 新乡航空工业(集团)有限公司 | Aviation high-voltage high-power three-phase full-control rectifying device based on silicon carbide |
| CN113904566A (en) * | 2021-11-10 | 2022-01-07 | 华芯威半导体科技(北京)有限责任公司 | 200kW vehicle-mounted inverter controller based on SIC power module |
| CN217063572U (en) * | 2022-03-09 | 2022-07-26 | 易事特集团股份有限公司 | Drive circuit of silicon carbide device |
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