CN115910928A

CN115910928A - Semiconductor structure and forming method thereof

Info

Publication number: CN115910928A
Application number: CN202111015497.0A
Authority: CN
Inventors: 刘达
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2023-04-04

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the steps of firstly forming a first well region and a first fin part material layer covering the first well region, and then forming a second well region and a second fin part material layer covering the second well region, so that accurate alignment between the first well region and the first fin part material layer and between the second well region and the second fin part material layer can be realized, and alignment between the first well region and the first fin part layer and alignment between the second well region and the second fin part layer can be accurately realized. Meanwhile, the first fin material layer is formed by first epitaxial growth and then etching, so that the bottom of the formed first fin material layer can be prevented from generating a fillet, and the top of the second area of the substrate is prevented from being damaged in the process of forming the first fin material layer by etching.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In order to better meet the requirement of scaling down the device size, the semiconductor process gradually starts to transition from planar MOSFET transistors to three-dimensional transistors with higher performance, such as Fin Field Effect transistors (finfets).

A finfet generally includes a fin protruding from a surface of a substrate, a gate structure covering a portion of a top and sidewalls of the fin, and a source region and a drain region in the fin on both sides of the gate structure.

However, the performance of the semiconductor structure manufactured by the conventional method for manufacturing the fin field effect transistor still needs to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the formed semiconductor structure.

In order to solve the above problem, the present invention provides a method for forming a semiconductor structure, the method comprising:

providing an initial substrate comprising a first region and a second region;

forming a first well region mask layer on the second region;

performing first well ion implantation on the first area by taking the first well mask layer as a mask to form a first well region in the first area;

forming a first fin material layer covering the first well region;

forming a second well region mask layer covering the first fin part material layer;

after the second well region mask layer is formed, removing the first well region mask layer;

performing second well ion implantation on the second area by taking the second well mask layer as a mask to form a second well region in the second area;

forming a second fin material layer covering the second well region;

after the second fin material layer is formed, removing the second well region mask layer;

after the second well region mask layer is removed, the first fin portion material layer and the second fin portion material layer are flattened, so that the top surfaces of the first fin portion material layer and the second fin portion material layer are flush, and a first fin portion layer and a second fin portion layer are formed;

and etching the first fin portion layer, the second fin portion layer and the initial substrate with partial thickness to form a substrate and a first fin portion and a second fin portion which are positioned on the substrate in a separated mode.

Optionally, the first well region mask layer is made of silicon nitride.

Optionally, the second well region mask layer is made of silicon oxide.

Optionally, the thickness of the first well region mask layer is 60nm to 200nm; the thickness of the first fin portion material layer is 40 nm-100 nm, and the thickness of the second well region mask layer is 60 nm-100 nm.

Optionally, before forming the second well region mask layer, the method further includes: and forming a protective layer covering the top of the first fin material layer and the side wall of the second well region mask layer.

Optionally, the protective layer comprises a first sub-protective layer and a second sub-protective layer located on the first sub-protective layer;

the step of forming the protective layer includes: forming a first sub-protection material layer which conformally covers the first well region mask layer and the first fin portion material layer; forming a second sub-protection material layer conformally covering the first sub-material protection layer; and after the second well region mask layer is formed, removing the first sub-protection material layer and the second sub-protection material layer which are positioned at the top of the first well region mask layer to form the protection layer.

Optionally, the thickness of the first sub-protection layer is 0.5nm to 10nm, and the thickness of the second sub-protection layer is 1nm to 20nm.

Optionally, before forming the first well region mask layer on the second region, the method further includes: forming a first pad oxide layer covering the second area;

the step of forming the first pad oxygen layer includes: forming a first pad oxygen material layer on the initial substrate; removing the first pad oxygen material layer on the first area to form the first pad oxygen layer;

and in the process of removing the first well region mask layer, the first pad oxygen layer is also removed.

Optionally, a first pad oxide material layer is formed by performing a first oxidation process on the initial substrate surface.

Optionally, before forming the second fin material layer, the method further includes: and forming a second pad oxide layer covering the side wall of the second fin material layer.

Optionally, the material of the second pad oxygen layer is silicon oxide.

Optionally, the step of forming the second pad oxygen layer comprises: performing a second oxidation treatment process on the top surface of the second region of the initial substrate and the side wall of the first fin material layer to form a second pad oxygen material layer; and removing the second pad oxygen material layer on the top surface of the second region of the initial substrate, and only remaining the second pad oxygen material layer covering the side wall of the first fin material layer to form the second pad oxygen layer.

Optionally, the second oxidation treatment process is an in-situ steam oxidation process.

Optionally, the step of removing the second well region mask layer includes: forming a sacrificial layer covering the second well region mask layer and the second fin material layer; after the sacrificial layer is formed, a planarization process is performed on the sacrificial layer and the second well region mask layer until the top surfaces of the first fin material layer and the second fin material layer are exposed.

Optionally, the material of the sacrificial layer comprises plasma enhanced silicon oxide, high density plasma silicon oxide or high aspect ratio filled silicon oxide.

Optionally, after the first fin layer and the second fin layer are formed, the method further includes: and forming an alignment mark of a subsequent patterning process by using the first fin portion layer and the second fin portion layer.

Optionally, forming a substrate and a first fin and a second fin on the substrate comprises: forming a hard mask material layer on the first fin portion layer and the second fin portion layer; forming a plurality of discrete mandrel layers on the layer of hard mask material; forming a side wall mask layer covering the side wall of the mandrel layer; removing the mandrel layer, and etching the hard mask material layer by taking the side wall mask layer as a mask to form a patterned hard mask layer; and removing the side wall mask layer, and etching the first fin part layer, the second fin part layer and the initial substrate with partial thickness by using the patterned hard mask layer as a mask to form the substrate and the first fin part and the second fin part which are positioned on the substrate in a separated mode.

Optionally, before forming the hard mask material layer, the method further comprises: forming a cap material layer covering the first fin portion layer and the second fin portion layer;

and in the process of etching the first fin part layer, the second fin part layer and the initial substrate with partial thickness by using the patterned hard mask layer, patterning the cap material layer to form cap layers positioned on the first fin part and the second fin part.

Optionally, the material of the cap layer is silicon.

Optionally, the cap layer has a thickness of 0.5nm to 5nm.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, where the semiconductor structure includes:

a substrate comprising a first region and a second region;

the first well region is positioned in the first region; the second well region is positioned in the second region; the doping type of the second well region is different from that of the first well region;

a first type of semiconductor material located over the first well region; a second type of semiconductor material located over the second well region; the first type of semiconductor material is of a different conductivity type than the second type of semiconductor material;

a first opening spaced apart from the first type of semiconductor material; a second opening spaced apart from said second type of semiconductor material;

a first fin portion protruding from a first region of the substrate; a second fin protruding from a second region of the substrate.

Optionally, the semiconductor structure further comprises:

the isolation layer covers the adjacent first fin portions, the adjacent second fin portions and the side walls of the adjacent first fin portions and the adjacent second fin portions, and the top surface of the isolation layer is lower than the top surfaces of the adjacent first fin portions, the adjacent second fin portions and the adjacent first fin portions and the adjacent second fin portions.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the method for forming the semiconductor structure, after a first well region and a first fin material layer covering the first well region are formed, a second well region and a second fin material layer covering the second well region are formed, and the first fin material layer is formed after the first well region and the second well region are formed. Meanwhile, the first fin material layer is formed in an etching mode after first epitaxial growth is not adopted, so that the bottom of the formed first fin material layer can be prevented from generating a fillet, and the top of the second area of the substrate is prevented from being damaged in the process of forming the first fin material layer through etching. Therefore, the method for forming the semiconductor structure provided by the embodiment of the invention can improve the performance of the formed semiconductor structure.

Drawings

Fig. 1 to 9 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;

fig. 10 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed Description

As can be seen from the background, the performance of the semiconductor structure formed by the conventional method for forming a semiconductor structure still needs to be improved. An analysis is now performed in conjunction with a method of forming a semiconductor structure.

Fig. 1 to 9 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, an initial substrate 100 is provided, the initial substrate 100 including a first region I and a second region II.

Referring to fig. 2, a first well region mask 110 is formed on the second region I, and a first well ion implantation is performed on the first region I using the first well region mask 110 as a mask to form a first well region 101 in the first region. Before forming the first well mask 110, a pad oxide layer 105 is further formed on the initial substrate 100 to reduce stress between the initial substrate 100 and the first well mask 110 and to reduce implantation damage to the initial substrate 100 in a subsequent well implantation process.

Referring to fig. 3, after the first well region 101 is formed, the first well region mask 110 is removed; after removing the first well region mask 110, forming a second well region mask 120 on the first region I; second well ion implantation is performed on the second region using the second well mask 120 as a mask, and a second well region 102 is formed in the second region.

Referring to fig. 4, after the second well region 102 is formed, the second well region mask 120 is removed; after removing the second well region mask 120, an epitaxial growth process is used to form an initial fin material layer 130 covering the first well region 101 and the second well region 102.

Referring to fig. 5, after forming the initial fin material layer 130, a patterned etch mask layer 150 is formed on the initial fin material layer 130. Before forming the patterned etching mask layer 150, a step of forming a protective material layer 140 on the initial fin material layer 130 is further included to protect the top of the first fin material layer 130 in a subsequent process.

Referring to fig. 6, after forming an etching mask layer 150, the initial fin material layer 130 is mask-etched by using the etching mask layer 150, the first fin material layer 130 on the second region is removed, only the first fin material layer 130 covering the first well region 101 is remained, and a first fin material layer 135 is formed. During the etching of the initial fin material layer 130, the protection material layer 140 is also etched to form a protection layer 145. The protection layer 145 is used to protect the top surface of the first fin material layer 135 in subsequent processes.

Referring to fig. 7, after the first fin material layer 135 is formed, an epitaxial growth process is performed to form a second fin material layer 160 covering the second region II.

Referring to fig. 8, after the second fin material layer is formed, the second fin material layer, the etching mask layer, the protection layer, and the first fin material layer are planarized until the top surface of the second fin material layer is flush with the top surface of the first fin material layer, thereby forming a first fin layer 135' and a second fin layer 165.

Referring to fig. 9, after forming the first fin layer and the second fin layer, the first fin layer and the second fin layer and the initial base with a partial thickness are etched, and a substrate 100' and a first fin 135 ″ and a second fin 165' located separately on the substrate 100' are formed.

In the above method for forming the semiconductor structure, the first well region 101 and the second well region 102 are formed first, then the initial fin material layer 130 is etched to expose the top surface of the second well region 102 of the initial substrate 100, only the first fin material layer 130 located on the first well region 101 is remained to form the first fin material layer 135, and the second fin material layer 165 is formed on the top surface of the second region exposed from the initial substrate 100. However, since the initial fin material layer 130 is made of the same material as the initial substrate 100, the etching position cannot be accurately stopped at the boundary between the first well region 101 and the second well region 102 during the etching process of the initial fin material layer 130, so that the first well region 101 and the first fin material layer 135 are misaligned, and further the second well region 105 and the second fin material layer 165 are misaligned accordingly. Meanwhile, the initial fin material layer 130 is etched, so that a rounded corner appears at the bottom of the finally formed first fin material layer 135', which easily causes the boundary problem between the N region and the P region. In addition, the etching of the initial fin material layer 130 may also cause damage to the top surface of the second well region 102, which affects the quality of the subsequently formed second fin material layer, and thus the quality of the subsequently formed second fin.

In summary, the semiconductor structure formed by the above method has a problem of low performance.

In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing an initial substrate comprising a first region and a second region; forming a first well region mask layer on the second region; performing first well ion implantation on the first area by taking the first well mask layer as a mask to form a first well region in the first area; forming a first fin material layer covering the first well region; forming a second well region mask layer covering the first fin portion material layer; after the second well region mask layer is formed, removing the first well region mask layer, performing second well ion implantation on the second region by taking the second well region mask layer as a mask, and forming a second well region in the second region; forming a second fin material layer covering the second well region; after the second fin material layer is formed, removing the second well region mask layer; after the second well region mask layer is removed, the first fin portion material layer and the second fin portion material layer are flattened, so that the top surfaces of the first fin portion material layer and the second fin portion material layer are flush, and a first fin portion layer and a second fin portion layer are formed; and etching the first fin part layer, the second fin part layer and the initial substrate with partial thickness to form a substrate and a first fin part and a second fin part which are positioned on the substrate and separated.

In the method for forming the semiconductor structure provided in the embodiment of the invention, after the first well region is formed, the first fin portion material layer covering the first well region is formed, and after the first fin portion material layer is formed, the well region and the second fin portion material layer covering the second well region are formed. Meanwhile, the first fin material layer is formed in an etching mode after first epitaxial growth is not adopted, so that the bottom of the formed first fin material layer can be prevented from generating a fillet, and the top of the second area of the substrate is prevented from being damaged in the process of forming the first fin material layer through etching. Therefore, the method for forming the semiconductor structure provided by the embodiment of the invention can improve the performance of the formed semiconductor structure.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 10 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 10, an initial substrate 200 is provided, the initial substrate 200 including a first region I and a second region II.

The initial substrate 200 is used to provide a process platform for subsequent processes.

In this embodiment, the initial substrate 200 is made of silicon. In other embodiments, the material of the initial substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the initial substrate may also be a silicon-on-insulator initial substrate or another type of initial substrate such as a germanium-on-insulator initial substrate. In still other embodiments, the initial substrate may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process foundation for the subsequent formation of the initial substrate, and the second semiconductor layer is used to provide a process foundation for the subsequent formation of the fin portion. In other embodiments, the initial substrate may further include other functional layers to be etched, and the target pattern is formed by etching the functional layers to be etched subsequently. For example, the functional layer to be etched is a gate material layer for forming a gate layer and the like.

The initial substrate 200 may include a first region I and a second region II, the first region I may be an N-Metal Oxide Semiconductor (NMOS) region or a P-Metal Oxide Semiconductor (PMOS) region, and correspondingly, the second region II may be an NMOS region or a PMOS region.

In this embodiment, taking the formed FinFET as a Complementary Metal Oxide Semiconductor (CMOS) device as an example, the first region I may be set to be used for forming an NMOS device subsequently, the second region II may be set to be used for forming a PMOS device subsequently, and the first region I and the second region II are adjacent regions.

In other embodiments, the first region I may also be a PMOS region, and correspondingly, the second region II is an NMOS region. Or, the first region I and the second region II are both NMOS regions, and the correspondingly formed FinFET is an NMOS device. Or, the first region I and the second region II are both PMOS regions, and the correspondingly formed FinFET is a PMOS device.

Referring to fig. 11, a first well mask layer 210 is formed on the second region II.

The first well region mask layer 210 is a mask for performing a first well ion implantation on the first region I.

In this embodiment, the first well mask layer 210 is made of silicon nitride (SiN). In other embodiments, the material of the first well mask layer can also be silicon carbide (SiC), silicon carbonitride (SiCN), or the like.

The step of forming the first well region mask layer 210 includes: forming a first well region mask material layer covering the initial substrate 200; and patterning the first well region mask material layer, and forming a first groove positioned on the first region I in the first well region mask material layer to enable the first well region mask material layer to form the first well region mask layer.

The process for forming the first well region mask material layer is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the first well mask material layer is formed by a chemical vapor deposition process.

The step of patterning the first well region mask material layer includes: forming a patterned mask layer on the first well region mask material layer; etching the first well region mask material layer by taking the patterned mask layer as a mask to form a first well region mask layer; and after the first well region mask layer is formed, removing the mask layer.

In this embodiment, the mask layer is made of photoresist. Accordingly, the process for removing the mask layer is an ashing process or the like.

In this embodiment, before forming the first well region mask material layer, a step of forming a first pad oxide layer (pad oxide) 203 on the surface of the initial substrate 200 may be further included.

The first pad oxide layer 203 is used to reduce stress between the initial substrate 200 and the first well region mask material layer 210, enhance adhesion between the initial substrate 200 and the first well region mask material layer 210, and reduce implantation damage to the initial substrate 200 during the first well ion implantation process.

In this embodiment, the first pad oxide layer 203 may be obtained by performing a first oxidation process on the initial substrate 200. In other embodiments, the first pad oxide layer may also be formed in other suitable manners, which are not limited herein.

Specifically, the process of the first oxidation treatment includes a thermal oxidation process. In other embodiments, the first oxidation process can be an In-Situ Steam oxidation process (ISSG).

Referring to fig. 12, a first well ion implantation is performed on the first region I by using the first well mask layer 210 as a mask, and a first well 201 is formed in the first region I.

The first well region 201 is formed by performing first well ion implantation to dope different types of impurity ions into the initial substrate 200.

In this embodiment, the MOS transistor to be formed in the first region I is an NMOS device, and accordingly, the impurity ions implanted by the first well ion implantation are P-type impurity ions. Wherein, the P-type impurity ions are one or more of boron ions, gallium ions and indium ions.

In other embodiments, the MOS device to be formed on the first region I can also be a PMOS device, and accordingly, the impurity ions implanted by the first well ion implantation are N-type impurity ions. Wherein, the N-type impurity ions are one or more of phosphorus ions, arsenic ions and gallium ions.

In this embodiment, after the first well 201 is formed in the first region I, a first annealing process is performed on the initial substrate 200. The first annealing process is performed on the initial substrate 200, so that the implanted impurity ions are uniformly diffused to the initial substrate 200.

Referring to fig. 13, after the first well region 201 is formed, a first fin material layer 220 is formed over the first well region 201.

The first fin material layer 220 is used for subsequent etching to form a first fin layer, and the first fin layer is used for subsequent etching of discrete first fin portions located on the first well region 201.

In this embodiment, the first fin material layer 220 is made of silicon.

In this embodiment, the process of forming the first fin material layer 220 is an epitaxial growth process. In other embodiments, the first fin material layer may be formed in other suitable manners, which are not limited herein.

In this embodiment, the top surface of the first fin material layer 220 is lower than the top surface of the first well mask layer 210, so as to form a second well mask layer on the first well mask layer 210 in a subsequent step. Specifically, the thickness of the first well region mask layer 210 is 60nm to 200nm, and the thickness of the first fin material layer 220 is 40nm to 100nm.

Referring to fig. 14, after the first fin material layer 220 is formed, a second well mask layer 230 is formed to cover the first fin material layer 220.

The second well region mask layer 230 is used as a mask for performing second well ion implantation on the second region II, so as to block and protect the covered region.

In this embodiment, the second well mask layer 230 is made of silicon oxide (SiO). In other embodiments, the material of the second well mask layer 230 can also be silicon nitride, silicon carbide, silicon carbonitride, or the like.

The step of forming the second well mask layer 230 includes: forming a second well region mask material layer covering the first well region mask layer and the first fin material layer; the second well region mask material layer is planarized until the top surface of the first well region mask layer is exposed, forming the second well region mask layer 230.

The process for forming the second well region mask material layer is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the second well mask material layer is formed by a chemical vapor deposition process.

In this embodiment, the process of planarizing the second well mask material layer is a chemical mechanical polishing process. In other embodiments, the process of planarizing the second well region mask material layer can also be an etch-back process, etc.

In this embodiment, the thickness of the first well region mask layer 210 is 60nm to 2000nm, the thickness of the first fin material layer 220 is 40nm to 100nm, and correspondingly, the thickness of the second well region mask layer is 60nm to 100nm.

In this embodiment, before forming the second well mask layer 230, the method further includes: a protection layer 204 is formed covering the top of the first fin material layer 220 and the sidewalls of the second well mask layer.

The protection layer 204 is used to protect the first fin material layer 220 in subsequent processes.

In this embodiment, the protection layer 204 is a stacked structure. Specifically, the protection layer 204 includes a first sub-protection layer (not shown) and a second sub-protection layer (not shown) on the first sub-protection layer. In other embodiments, the protective layer can also be a single layer structure, which is not limited herein.

In this embodiment, the first sub-protection layer is made of silicon oxide, and the second sub-protection layer is made of silicon nitride.

The thickness of the protective layer 204 should not be too large or too small. When the thickness of the protection layer 204 is too small, the protection layer 204 cannot protect the first fin material layer 204 well in the subsequent process; when the thickness of the protection layer 125 is too large, the subsequent etching to remove the protection layer 204 is not facilitated. Therefore, in the present embodiment, the thickness of the protection layer 204 is 1.5nm to 30nm, and specifically, when the protection layer 204 has a stacked structure, the thickness of the first sub-protection layer is 0.5nm to 10nm, and the thickness of the second sub-protection layer is 1nm to 20nm.

The step of forming the protective layer 204 includes: forming a first sub-protection material layer conformally covering the first well region mask layer 210 and the first fin material layer 220; after the first sub-protection material layer is formed, forming a second sub-protection material layer which conformally covers the first sub-material protection layer; the first sub-protection material layer and the second sub-protection material layer on the first well region mask layer 210 are removed to form the protection layer 204.

After forming the second sub-protection material layer, a second well region mask material layer covering the second sub-protection material layer is formed, the second well region mask material layer is planarized, only the second well region mask material layer on the first fin material layer is remained, and the second well region mask layer 230 is formed.

And in the process of flattening the second well region mask layer executing process, the second sub-protection material layer is used as a stop layer, so that the top surface of the second well region mask layer is flush with the top surface of the second sub-protection material layer positioned at the top of the first well region mask layer.

After the second well mask layer is formed, the second sub-protection material layer covers the sidewalls of the second well mask layer 230.

After the second well region mask layer is formed, the first sub-protection material layer and the second sub-protection material layer on the top of the first well region mask layer 210 are removed to form the protection layer 204.

The process for forming the first sub-protection material layer is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the second sub-protection material layer is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a second sub-protective material layer of a desired thickness. By selecting the atomic layer deposition process, the thickness uniformity of the second sub-protection material layer is improved, and the thickness of the second sub-protection material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the second sub-protection material layer is correspondingly improved.

The process for forming the second sub-protection material layer is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the second sub-protection material layer is formed by using an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a second sub-protective material layer of a desired thickness. The atomic layer deposition process is selected, so that the thickness uniformity of the second sub-protection material layer is improved, and the thickness of the second sub-protection material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the second sub-protection material layer is correspondingly improved.

The process of removing the first sub-protection material layer and the second sub-protection material layer on the top of the first well region mask layer 210 includes a dry etching process, a wet etching process, and the like. In this embodiment, a dry etching process is used to remove the first sub-protection material layer and the second sub-protection material layer on the top of the first well mask layer 210.

Referring to fig. 15, after the second well mask layer 230 is formed, the first well mask layer 210 is removed.

The first well region mask layer 210 is removed to expose the second region II of the initial substrate 200, thereby preparing for performing a second well ion implantation on the second region II.

The process of removing the first well region mask layer 210 is a dry etching process, a wet etching process, or the like. In this embodiment, the first well mask layer 210 is removed by a dry etching process.

In this embodiment, the first pad oxide layer 203 is further formed at the bottom of the first well region mask layer 210, and during the process of removing the first well region mask layer 210, the method further includes a step of removing the first pad oxide layer 203 to expose the second region II of the initial substrate 200.

The process for removing the first pad oxide layer 203 is a dry etching process, a wet etching process, or the like. In this embodiment, the first pad oxide layer 203 is removed by a dry etching process.

Referring to fig. 16, after removing the first well region mask layer 210, a second well ion implantation is performed on the second region II using the second well region mask layer 230 as a mask, and a second well region 202 is formed in the second region II.

A second well ion implantation is performed to dope different types of impurity ions into the initial substrate 200, thereby forming a second well region 202 in a second region II of the initial substrate.

In this embodiment, the MOS transistor to be formed in the second region II is a PMOS device, and accordingly, the impurity ions implanted by the second well ion implantation are N-type impurity ions. Wherein, the N-type impurity ions are one or more of phosphorus ions, arsenic ions and gallium ions.

In other embodiments, the MOS device to be formed on the second region II can also be an NMOS device, and accordingly, the impurity ions implanted by the second well ion implantation are P-type impurity ions. Wherein, the P-type impurity ions are one or more of boron ions, gallium ions and indium ions.

In this embodiment, after the second well region 202 is formed in the second region II, a step of performing a second annealing process on the initial substrate 200 is further included. The second annealing process is performed on the initial substrate 200, so that the P-type impurity ions are uniformly diffused to the second region II.

Referring to fig. 17, after the second well region 202 is formed, a second fin material layer 240 is formed overlying the second well region 202.

The second fin material layer 240 is used for forming a second fin layer in a subsequent step, so as to form a second fin portion in a subsequent etching step.

In this embodiment, the second fin material layer 240 is silicon germanium (SiGe).

In this embodiment, the process of forming the second fin material layer 240 is an epitaxial growth process. In other embodiments, the process of forming the second fin material layer 240 can be other suitable processes, and is not limited herein.

In this embodiment, before forming the second fin material layer 240, the method further includes: a second pad oxide layer 205 is formed covering the sidewalls of the second fin material layer.

In this embodiment, the second pad oxide layer 205 is formed by performing a second oxidation process on the sidewalls of the second fin material layer.

The step of forming the second pad oxide layer 205 includes: performing a second oxidation treatment process on the top surface of the second region II of the initial substrate 200 and the sidewall of the first fin material layer to form a second pad oxygen material layer; after forming the second pad oxide material layer, the second pad oxide material layer on the top surface of the second region II of the initial substrate 200 is removed, and only the second pad oxide material layer covering the sidewalls of the first fin material layer remains, so as to form the second pad oxide layer 205.

Specifically, the process of the second oxidation treatment includes a thermal oxidation process or an in-situ steam oxidation process. In this embodiment, an in-situ steam oxidation process is employed. By selecting the in-situ steam oxidation process, the uniformity of the oxidation rate of the initial pad oxygen layer at the top of the second region II and on the sidewall of the first fin material layer 220 is favorably high, so that the second pad oxygen layer 205 has high density and thickness uniformity; moreover, the process temperature of the in-situ steam oxidation process is generally low (the process temperature is generally lower than that of the furnace tube process), so that the thermal stress is favorably reduced, and the damage to the substrate is reduced.

The second pad oxide material layer covering the top of the second region II of the initial substrate 200 is removed, so that the damaged portion of the top of the second region II of the initial substrate 200 in the previous process is removed, thereby preventing the damaged portion of the top of the initial substrate 200 from affecting the second fin material layer formed thereon, improving the quality of the second fin formed subsequently, and further improving the performance of the formed semiconductor structure.

The material of the second pad oxide layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride. In this embodiment, the material of the initial substrate 200 and the first fin material layer is silicon, and correspondingly, the material of the second pad oxide layer 205 is silicon oxide.

Referring to fig. 18, after the second fin material layer 240 is formed, the second well region mask layer 230 is removed, and the first fin material layer 220 and the second fin material layer 240 are planarized, so that top surfaces of the remaining first fin material layer 220 and the remaining second fin material layer 240 are flush, and a first fin layer 225 and a second fin layer 245 are formed.

The step of removing the second well mask layer 230 includes: forming a sacrificial layer covering the second well mask layer 230 and the second fin material layer 240; after the sacrificial layer is formed, a planarization process is performed on the sacrificial layer and the second well region mask layer 230 until the top surfaces of the first fin material layer 210 and the second fin material layer 240 are exposed.

The material of the sacrificial layer comprises: plasma enhanced silicon oxide (PEOX), high density plasma silicon oxide (HDP oxide) layer.

In this embodiment, the process of forming the sacrificial layer is a Chemical Vapor Deposition (CVD) process. In other embodiments, the sacrificial layer may be formed by other suitable processes such as a High Aspect Ratio Process (HARP).

In this embodiment, the planarization process performed on the sacrificial layer and the second well mask layer is a chemical mechanical polishing process. In other embodiments, the planarization process may be other suitable processes, and is not limited herein.

When the protective layers 204 are formed on the top of the first fin portion material layer and the side walls of the second well region mask layer, the planarization process is further performed on the protective layers 204 on the top of the first fin portion material layer and the side walls of the second well region mask layer in the process of performing the planarization process on the sacrificial layer and the second well region mask layer.

In this embodiment, the process of planarizing the first fin material layer and the second fin material layer is a chemical mechanical polishing process.

In this embodiment, in the process of performing the planarization process on the sacrificial layer and the second well region mask layer, the first fin material layer 220 and the second fin material layer 240 are planarized, which is beneficial to simplifying process steps, improving process manufacturing efficiency, and improving process compatibility.

Referring to fig. 19, the first fin layer, the second fin layer and the initial base with a partial thickness are etched to form a substrate 200 'and a first fin 225' and a second fin 245 'on the substrate 200'.

Forming a substrate 200 'and first and second fins 225', 245 'on the substrate 200' comprises: forming a hard mask material layer on the first fin portion layer and the second fin portion layer; forming a plurality of discrete mandrel layers on the layer of hard mask material; forming a side wall mask layer covering the side wall of the mandrel layer; removing the mandrel layer, and etching the hard mask material layer by taking the side wall mask layer as a mask to form a patterned hard mask layer; after forming a patterned hard mask layer, removing the sidewall mask layer, and etching the first fin layer, the second fin layer, and the initial base with a partial thickness by using the patterned hard mask layer to form the substrate 200 'and a first fin portion 225' and a second fin portion 245 'on the substrate 200'.

In this embodiment, the material of the hard mask material layer includes silicon dioxide. In other embodiments, the material of the hard mask material layer may also be silicon carbide, silicon carbonitride, or the like.

The process for forming the hard mask material layer includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like. In this embodiment, the hard mask material layer is formed by a chemical vapor deposition process.

In this embodiment, after the sidewall mask layer on the sidewall of the mandrel layer is formed, the mandrel layer needs to be removed, so the mandrel layer is a material that is easy to remove, and the process for removing the mandrel layer has less damage to other film layers. In this embodiment, the mandrel layer is made of amorphous silicon. In other embodiments, the mandrel layer is made of silicon nitride. In other embodiments, the material of the mandrel Layer may also be amorphous carbon, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or Organic Dielectric Layer (ODL) material.

The step of forming the mandrel layer comprises: forming a mandrel material layer on the hard mask material layer; forming a patterned mask layer on the mandrel material layer; and etching the mandrel material layer by taking the patterned mask layer as a mask to form the mandrel layer.

In this embodiment, the material of the sidewall mask layer is silicon nitride.

In the embodiment, in order to improve the uniformity of the thickness of the side wall mask layer and reduce the difficulty in controlling the thickness of the side wall mask layer, the atomic layer deposition process is adopted to form the first side wall mask material layer. In other embodiments, the sidewall mask layer may also be formed by a chemical vapor deposition process.

In this embodiment, the process of removing the mandrel layer is a wet etching process. In other embodiments, the mandrel layer can also be removed using a dry etching process.

In this embodiment, the process of removing the side wall mask layer is a wet etching process. In other embodiments, the sidewall mask layer can also be removed by a dry etching process.

In this embodiment, before forming the hard mask material layer, a step of forming a cap material layer on the first fin layer 225 and the second fin layer 245 is further included; in the process of etching the first fin layer, the second fin layer and the initial substrate with a partial thickness by using the patterned hard mask layer, the capping material layer is further patterned to form capping layers on the first fin portion 225 'and the second fin portion 245'.

The cap layer is used for protecting the tops of the first fin portion and the second fin portion in a subsequent process.

In this embodiment, the cap layer is made of silicon and has a thickness of 0.5nm to 5nm.

Correspondingly, the embodiment of the invention also provides a semiconductor structure.

With continued reference to fig. 19, a semiconductor structure comprises: a substrate 200', said substrate 200' comprising a first region I and a second region II; a first well region (not labeled) located in the first region I and a second well region (not labeled) located in the second region II; the doping type of the second well region is different from that of the first well region; a first type of semiconductor material (not labeled) located over the first well region and a second type of semiconductor material (not labeled) located over the second well region; the first type of semiconductor material is of a different conductivity type than the second type of semiconductor material; a first fin 225 'protruding from the substrate 200' on the first region I; a second fin 245 'protruding from the substrate 200' over the second region II.

In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET).

In this embodiment, the MOS transistor to be formed in the first region I is an NMOS device; the MOS transistor to be formed in the second region II is a PMOS device. Correspondingly, the impurity ions injected into the first well region are P-type impurity ions, and the impurity ions injected into the second well region are N-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions and indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions and gallium ions.

In this embodiment, the first fin portion 225 'is made of the same material as the substrate 200', and the second fin portion 245 'is made of a different material from the substrate 200'. Specifically, the substrate 200' and the first fin portion 225' are both made of silicon, and the second fin portion 245' is silicon germanium.

In this embodiment, the semiconductor structure further includes an isolation layer (not labeled); the isolation layer covers sidewalls of the adjacent first fin portion 225', the adjacent second fin portion 245' and the adjacent first fin portion 225 'and second fin portion 245', and a top surface of the isolation layer is lower than top surfaces of the adjacent first fin portion 225', the adjacent second fin portion 245' and the adjacent first fin portion 225 'and second fin portion 245'.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing an initial substrate comprising a first region and a second region;

forming a first well region mask layer on the second region;

forming a first fin material layer covering the first well region;

forming a second well region mask layer covering the first fin portion material layer;

performing second well ion implantation on the second region by taking the second well mask layer as a mask, and forming a second well region in the second region;

forming a second fin material layer covering the second well region;

and etching the first fin portion layer, the second fin portion layer and the initial substrate with partial thickness to form a substrate and a first fin portion and a second fin portion which are located on the substrate in a separated mode.

2. The method as claimed in claim 1, wherein the first well mask layer is made of silicon nitride.

3. The method as claimed in claim 1, wherein the material of the second well mask layer is silicon oxide.

4. The method of claim 1, wherein the first well mask layer has a thickness of 60nm to 200nm; the thickness of the first fin portion material layer is 40 nm-100 nm, and the thickness of the second well region mask layer is 60 nm-100 nm.

5. The method of claim 1, further comprising, before forming the second well mask layer: and forming a protective layer covering the top of the first fin material layer and the side wall of the second well region mask layer.

6. The method for forming the semiconductor structure according to claim 5, wherein the protective layer comprises a first sub protective layer and a second sub protective layer located on the first sub protective layer;

7. The method as claimed in claim 6, wherein the first sub-protection layer has a thickness of 0.5nm to 10nm, and the second sub-protection layer has a thickness of 1nm to 20nm.

8. The method of claim 1, further comprising, before forming the first well mask layer over the second region: forming a first pad oxide layer covering the second area;

the step of forming the first pad oxygen layer includes: forming a first pad oxide material layer on the initial substrate;

removing the first pad oxygen material layer on the first area to form the first pad oxygen layer;

9. The method as claimed in claim 8, wherein the first pad oxide material layer is formed by performing a first oxidation process on the initial substrate surface.

10. The method of claim 1, further comprising, prior to forming the second layer of fin material: and forming a second pad oxide layer covering the side wall of the second fin material layer.

11. The method as claimed in claim 10, wherein the second pad oxide layer is made of silicon oxide.

12. The method of claim 10, wherein the step of forming the second pad oxide layer comprises: performing a second oxidation treatment process on the top surface of the second region of the initial substrate and the side wall of the first fin material layer to form a second pad oxygen material layer; and removing the second pad oxygen material layer on the top surface of the second region of the initial substrate, and only remaining the second pad oxygen material layer covering the side wall of the first fin material layer to form the second pad oxygen layer.

13. The method of claim 12, wherein the second oxidation process is an in-situ steam oxidation process.

14. The method of claim 1, wherein the removing the second well mask layer comprises: forming a sacrificial layer covering the second well region mask layer and the second fin material layer; after the sacrificial layer is formed, a planarization process is performed on the sacrificial layer and the second well region mask layer until the top surfaces of the first fin material layer and the second fin material layer are exposed.

15. The method as claimed in claim 14, wherein the material of the sacrificial layer comprises plasma enhanced silicon oxide, high density plasma silicon oxide or high aspect ratio filled silicon oxide.

16. The method of claim 1, wherein forming a substrate and first and second fins on the substrate comprises: forming a hard mask material layer on the first fin portion layer and the second fin portion layer; forming a plurality of discrete mandrel layers on the layer of hard mask material; forming a side wall mask layer covering the side wall of the mandrel layer; removing the mandrel layer, and etching the hard mask material layer by taking the side wall mask layer as a mask to form a patterned hard mask layer; and removing the side wall mask layer, and etching the first fin part layer, the second fin part layer and the initial substrate with partial thickness by using the patterned hard mask layer as a mask to form the substrate and a first fin part and a second fin part which are positioned on the substrate and separated.

17. The method of claim 16, further comprising, prior to forming the layer of hard mask material: forming a cap material layer covering the first fin portion layer and the second fin portion layer;

18. The method for forming a semiconductor structure according to claim 17, wherein the material of the cap layer is silicon.

19. The method of claim 17, wherein the cap layer has a thickness of 0.5nm to 5nm.

20. A semiconductor structure, comprising:

a substrate comprising a first region and a second region;

the first well region is positioned in the first region; the second well region is positioned in the second region; the above-mentioned

The doping type of the second well region is different from that of the first well region;

a first opening spaced apart from the first type of semiconductor material; a second opening spaced apart from the second type of semiconductor material;

a first fin portion protruding from the substrate on the first region; a second fin protruding from the substrate over the second region.

21. The semiconductor structure of claim 20, further comprising:

the isolation layer covers the adjacent first fin parts, the adjacent second fin parts and the side walls of the adjacent first fin parts and the adjacent second fin parts, and the top surface of the isolation layer is lower than the top surfaces of the adjacent first fin parts, the adjacent second fin parts and the adjacent first fin parts and the adjacent second fin parts.