CN115906191A - Physical unclonable function circuit and signature information generation device - Google Patents

Abstract

The application discloses a physical unclonable function circuit and a signature information generation device, relates to the field of encryption, and is used for improving the stability of response signals generated by PUF circuits. The PUF circuit includes: the circuit comprises a first comparison circuit, N first delay circuits connected in series and N second delay circuits connected in series; for the first delay circuit, a first delay device is coupled to the first capacitive device and the first terminal of the first selector, and a second delay device is coupled to the second capacitive device and the second terminal of the first selector; for the second delay circuit, a third delay device is coupled to the third capacitive device and the first terminal of the second selector, and a fourth delay device is coupled to the fourth capacitive device and the second terminal of the second selector; the N first delay circuits input excitation signals and output first signals; the N second delay circuits input the excitation signals and output second signals; the first comparison circuit outputs a response signal according to a delay difference between the first signal and the second signal.

Description

Physical unclonable function circuit and signature information generation device

Technical Field

The present invention relates to the field of encryption, and more particularly, to a Physically Unclonable Function (PUF) circuit and a signature information generation device.

Background

Storing the signature information (e.g. identity authentication information or encryption key) of the chip in a non-volatile memory (NVM) risks being tampered or stolen. One improvement is that the uncertainty of the manufacturing process of the PUF circuit can be exploited to generate a response signal based on the stimulus signal to generate unique signature information for each chip, so that the resulting signature information is unpredictable, unclonable and tamper-proof.

However, most of the existing PUF circuits generate response signals based on delay differences of active devices or differences of certain characteristic parameters (for example, static Random Access Memory (SRAM) PUFs are based on threshold voltage differences), and these differences are easily changed by the influence of factors such as voltage and temperature, so that the response signals generated by the PUF circuits are easily changed, and there is a problem of low stability.

Disclosure of Invention

The embodiment of the application provides a PUF circuit and a signature information generation device, which are used for improving the stability of a response signal generated by the PUF circuit.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, there is provided a PUF circuit comprising: the circuit comprises a first comparison circuit, N first delay circuits connected in series and N second delay circuits connected in series; the first delay circuit comprises a first delay device, a first capacitive device, a second delay device, a second capacitive device and a first selector; the second delay circuit comprises a third delay device, a third capacitive device, a fourth delay device, a fourth capacitive device and a second selector; n is a positive integer; for each first delay circuit, a first delay device is coupled to the first capacitive device and a first terminal of the first selector, and a second delay device is coupled to the second capacitive device and a second terminal of the first selector; for each second delay circuit, a third delay device is coupled to the third capacitive device and the first terminal of the second selector, and a fourth delay device is coupled to the fourth capacitive device and the second terminal of the second selector; the N first delay circuits are connected in series and used for inputting an excitation signal and outputting a first signal; the N second delay circuits are connected in series and used for inputting the excitation signals and outputting second signals; and a first comparison circuit for outputting a response signal according to a time delay difference between the first signal and the second signal, the response signal indicating that the first signal is earlier or later than the second signal.

The PUF circuit provided by the embodiment of the application includes N first delay circuits connected in series, N second delay circuits connected in series, and a comparison circuit, and for each of the first delay circuit and the second delay circuit, each of the first delay circuit and the second delay circuit includes a selector, two delay devices, and two sets of capacitive devices, each of the delay devices is coupled to one set of capacitive device, and the selector selects one of the delay devices to transmit an excitation signal. Because the time delay generated by the load capacitor of the transmission path of the capacitive device as the delay device is far larger than the time delay generated by the transmission signal of the delay device, and the influence of the voltage, the temperature and other factors on the capacitance parameter of the capacitive device is small, the influence of the voltage, the temperature and other factors on the overall time delay of the N first delay circuits and the N second delay circuits is small. And comparing the time delay difference between the transmission of the excitation signal through the Nth first time delay circuit and the transmission of the excitation signal through the Nth second time delay circuit by using a comparison circuit to output a response signal. The stability of the response signal is less affected by voltage, temperature, etc., thereby improving the stability of the response signal generated by the PUF circuit.

In one possible embodiment, the PUF circuit further includes a fifth delay device and a second comparison circuit; an output end of an nth first delay circuit in the N first delay circuits is coupled to a first input end of the second comparison circuit through a fifth delay device, an output end of an nth second delay circuit in the N second delay circuits is coupled to a second input end of the second comparison circuit, the second comparison circuit is used for outputting a first indication signal, the first indication signal is used for indicating whether a delay difference of the first signal earlier than the second signal is larger than a first threshold value, and at the moment, the first threshold value is equal to a delay generated by the fifth delay device. When the time delay difference of the first signal earlier than the second signal is greater than a first threshold, the time delay difference can be stably maintained along with the lapse of the use time, so that the value 0 of the response signal can also be stably maintained, and the reliability of the response signal is higher; otherwise, it is said that such a delay difference is difficult to stably maintain, so that the value 0 of the response signal is also difficult to stably maintain, and thus the reliability of the response signal is low.

In a possible embodiment, the PUF circuit further includes a seventh delay device, the delay generated by the seventh delay device being less than the delay generated by the fifth delay device; the output terminal of the nth second delay circuit is coupled to the second input terminal of the second comparator circuit through the seventh delay device, and the first threshold is equal to the time delay generated by the fifth delay device minus the time delay generated by the seventh delay device. When the delay difference of the first signal is larger than the first threshold value earlier than that of the second signal, the delay difference can be stably maintained along with the lapse of the use time, so that the value 0 of the response signal can also be stably maintained, and the reliability of the response signal is higher; otherwise, it is said that such a delay difference is difficult to stably maintain, so that the value 0 of the response signal is also difficult to stably maintain, and thus the reliability of the response signal is low.

In one possible implementation, the second comparison circuit comprises a nand gate latch, or alternatively, a nor gate latch. The nand gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the rising edges of the two signals, and the nor gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the falling edges of the two signals.

In one possible embodiment, the PUF circuit further includes a sixth delay device and a third comparison circuit; the output end of the nth second delay circuit in the N second delay circuits is coupled to the first input end of the third comparison circuit through the sixth delay device, the output end of the nth first delay circuit in the N first delay circuits is coupled to the second input end of the third comparison circuit, the third comparison circuit is used for outputting a second indication signal, the second indication signal is used for indicating whether the delay difference of the second signal earlier than the first signal is larger than a second threshold value, and at this time, the second threshold value is equal to the delay generated by the sixth delay device. When the delay difference of the second signal, which is earlier than the first signal, is greater than a second threshold, it is indicated that the delay difference can be stably maintained along with the lapse of the use time, so that the value 1 of the response signal can also be stably maintained, and the reliability of the response signal is higher; otherwise, it is described that such a delay difference is difficult to stably maintain, so that it is difficult to stably maintain the value 1 of the response signal, and thus the reliability of the response signal is low.

In a possible embodiment, the PUF circuit further includes an eighth delay device, a delay time produced by the eighth delay device is less than a delay time produced by the sixth delay device; the output end of the nth first delay circuit is coupled to the second input end of the third comparison circuit through an eighth delay device, and at this time, the second threshold is equal to the time delay generated by the sixth delay device minus the time delay generated by the eighth delay device. When the delay difference of the second signal is larger than the second threshold value earlier than that of the first signal, the delay difference can be stably maintained along with the lapse of the use time, so that the value 1 of the response signal can also be stably maintained, and the reliability of the response signal is higher; otherwise, it is said that such a delay difference is difficult to stably maintain, so that the value 1 of the response signal is also difficult to stably maintain, and thus the reliability of the response signal is low.

In one possible implementation, the third comparison circuit includes a nand gate latch, or a nor gate latch. The nand gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the rising edges of the two signals, and the nor gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the falling edges of the two signals.

In one possible embodiment, the first comparison circuit comprises a nand gate latch, or alternatively, a nor gate latch. The nand gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the rising edges of the two signals, and the nor gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the falling edges of the two signals.

In one possible implementation, for the nth first delay circuit and the nth second delay circuit, 1 ≦ N ≦ N, and N is a positive integer: when the first selector selects the first delay device to transmit the excitation signal, the second selector selects the third delay device to transmit the excitation signal; the first delay device and the third delay device are the same, and the first capacitive device and the third capacitive device are the same. When the first selector selects the second delay device to transmit the excitation signal, the second selector selects the fourth delay device to transmit the excitation signal; the second delay device and the fourth delay device are the same, and the second capacitive device and the fourth capacitive device are the same. The device identity may include at least one of the same type, number, parameters, etc. of the device. Since the control signals of each bit are independent from each other, the randomness of the delay differences generated by the nth first delay circuit and the nth second delay circuit is independent from each other. Therefore, the N first delay circuits connected in series and the N second delay circuits connected in series also generate a delay difference due to process variations when transmitting the excitation signal, and the larger the number of the first delay circuits and the second delay circuits is, the larger the randomness of such a delay difference is, the more difficult it is to predict, copy, or tamper with.

In one possible embodiment, for any two of the N first delay circuits in series: the devices adopted by the first delay devices are mutually independent, the devices adopted by the second delay devices are mutually independent, the devices adopted by the first capacitive devices are mutually independent, and the devices adopted by the second capacitive devices are mutually independent. In the embodiments of the present application, the devices are independent of each other, which means that the devices may be the same or different. The device identity may include that at least one of the type, number, parameters, etc. of the device is the same, and the device identity may include that at least one of the type, number, parameters, etc. of the device is different.

In one possible embodiment, for any two of the N second delay circuits connected in series: the devices adopted by the third delay device are mutually independent, the devices adopted by the fourth delay device are mutually independent, the devices adopted by the third capacitive device are mutually independent, and the devices adopted by the fourth capacitive device are mutually independent. In the embodiments of the present application, the devices are independent of each other, and it means that the devices may be the same or different. The device identity may include that at least one of the type, number, parameters, and the like of the device is the same, and the device identity may include that at least one of the type, number, parameters, and the like of the device is different.

In a second aspect, there is provided a signature information generating apparatus comprising a PUF circuit and a processor as described in the first aspect and any one of the embodiments thereof; the processor is used for outputting the excitation signal to the PUF circuit; the processor is further configured to receive a response signal from the PUF circuit corresponding to the stimulus signal; the processor is further configured to output signature information based on the response signal, the signature information being used to encrypt the processor output information. As described above, the PUF circuit employed in the signature information generating apparatus according to the embodiment of the present invention improves the stability of the generated response signal, and the signature information generating apparatus generates the signature information based on the response signal, thereby improving the reliability of the signature information. In addition, the PUF circuit can generate one bit of the response signal in each clock cycle, and the bit can be used as one bit of the signature information, thereby improving the efficiency of the signature information generation device in generating the signature information.

In one possible implementation, the processor is further configured to: receiving a first indication signal or a second indication signal from the PUF circuit, the first indication signal indicating whether a delay difference of the first signal before the second signal is larger than a first threshold, the second indication signal indicating whether a delay difference of the second signal before the first signal is larger than a second threshold; obtaining signature information according to one of the first indication signal or the second indication signal and the response signal, wherein each bit of the signature information is taken from a valid bit in the response signal, and the valid bit in the response signal refers to: a bit in the response signal when the first indicator signal indicates that the delay difference of the first signal earlier than the second signal is greater than a first threshold, or when the second indicator signal indicates that the delay difference of the second signal earlier than the first signal is greater than a second threshold. For each bit of the response signal, the first indication signal or the second indication information may further output an indication of the stability of the bit, so that a stable bit of the response signal may be used as a bit of the signature information, thereby improving the stability of the signature information.

In one possible implementation, the processor is further configured to: and obtaining a third indication signal according to one of the first indication signal or the second indication signal, wherein the third indication signal is used for indicating whether each bit of the response signal is valid or not, and when the response signal has M bits, the third indication signal also has M bits. When the third indication signal indicates that one bit of the response signal is valid, the one bit of the response signal can be used as one bit of the signature information. Otherwise, the one bit of the response signal cannot be used as one bit of the signature information.

Drawings

Fig. 1 is a schematic circuit diagram of a signature information generation apparatus according to an embodiment of the present application;

fig. 2 is a schematic circuit diagram of a PUF circuit according to an embodiment of the present disclosure;

fig. 3 is a circuit schematic diagram of another PUF circuit provided in an embodiment of the present application;

fig. 4 is a circuit schematic diagram of another PUF circuit provided in an embodiment of the present application;

fig. 5 is a circuit diagram of another PUF circuit provided in an embodiment of the present application.

Detailed Description

In encryption chips such as passport chips, identification card chips, subscriber Identity Modules (SIMs), and the like, signature information needs to be stored, and the conventional way of storing signature information in NVM is at risk of being tampered or stolen. At present, an improvement mode is that a response signal is generated based on a stimulus signal by utilizing the uncertainty of a PUF circuit in the manufacturing process, so as to generate unique signature information for each chip. Therefore, the signature information obtained based on the PUF circuit has the characteristics of being unpredictable, not reproducible and not falsifiable.

One way to obtain signature information by means of a PUF circuit is to: the method comprises the steps that a plurality of delay circuits are connected in series, each delay circuit selects different delay devices to transmit an excitation signal, the output end of the last delay circuit is fed back to the input end of the first delay circuit, the delay circuits output oscillation signals, the oscillation numbers of two transmission paths in the same time window are compared through a counter to generate signature information of one bit, and the signature information of multiple bits can be obtained by changing the excitation signal. This approach suffers mainly from the following disadvantages:

firstly, the time delay generated by the time delay device is easily changed under the influence of factors such as voltage and temperature, so that the response signal generated by the PUF circuit is easily changed, and the problem of low stability exists. Secondly, the PUF circuit described above consumes a long time to generate one bit of signature information, and depending on the difference in the degree of dispersion of the time delay produced by each delay device, generating one bit of signature information may need to be as long as 2 ¹⁵ To 2 ¹⁷ One clock cycle.

The PUF circuit that this application embodiment provided drives capacitive device through the time delay device, utilizes capacitive device to introduce the stability that time delay is difficult for receiving factors such as voltage, temperature to promote whole time delay to improve PUF circuit output response signal's stability. In addition, according to the signature information generating apparatus provided by the embodiment of the present application, the PUF circuit improves the stability of the generated response signal, and the signature information generating apparatus generates the signature information from the response signal, thereby improving the reliability of the signature information. In addition, the PUF circuit can generate one bit of the response signal in each clock cycle, and the bit can be used as one bit of the signature information, so that the efficiency of generating the signature information is improved. Further, for each bit of the response signal, the PUF circuit may further output a signal indicating the stability of the bit, so that one stable bit of the response signal may serve as one bit of the signature information, thereby improving the efficiency of the signature information generation apparatus to generate the signature information.

As shown in fig. 1, an embodiment of the present application provides a signature information generating apparatus based on a PUF circuit, and the signature information generating apparatus may be an apparatus for implementing identity authentication and key management, for example, an encryption chip such as a passport chip, an identity card chip, and a SIM card, or an electronic device such as an Internet of things (IoT) device and a wearable device. The signature information generation device includes a processor 11, a PUF circuit 12, a nonvolatile memory 13, an interface circuit 14, and a random sequence generator 15.

The processor 11 may be a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a system on chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a Digital Signal Processing (DSP), a Micro Controller Unit (MCU), a Programmable Logic Device (PLD), or the like.

The nonvolatile memory 13 may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory.

The interface circuit 14 may provide power for the signature information generating apparatus or be used for communication with an external device, and may include a power interface, a wired communication interface (e.g., an internet interface, a USB interface, a serial interface, etc.), or a wireless communication interface (e.g., a Radio Frequency Identification (RFID), etc.) and the like.

The random sequence generator 15 is configured to generate M N-bit control signals (control signal 1 to control signal N) based on the random seed and output the M N control signals to the PUF circuit 12, where M and N are positive integers. Exemplarily, M =256, n =10. The random seed may be a fixed value or from the processor 11 or non-volatile memory 13. The random sequence generator 15 may be a Linear Feedback Shift Register (LFSR).

The processor 11 may load and run a program from the nonvolatile memory 13, output a stimulus signal to the PUF circuit 12, receive an M-bit response signal from the PUF circuit 12, generate signature information from the response signal, and output the signature information (which may be encrypted for processor 11 output information) and a validation signal (indicating that the signature information is valid); optionally, the processor 11 may further receive the M-bit first indication signal or the M-bit second indication signal from the PUF circuit 12, generate signature information according to one of the first indication signal or the second indication signal and the response signal, obtain a third indication signal according to one of the first indication signal or the second indication signal, and output the third indication signal. The processor 11 may output such information or signals to the nonvolatile memory 13, the interface circuit 14, and the like. When the processor 11 outputs the information or signals to the nonvolatile memory 13, the information or signals are not lost when power is lost, and the information or signals can be directly obtained from the nonvolatile memory 13 when the processor 11 is started next time; when the processor 11 outputs such information or signals to the interface circuit 14, such information or signals may be output to other devices through the interface circuit 14. Processor 11 may also output an enable signal to random sequence generator 15 to control whether random sequence generator 15 outputs a control signal. These signals referred to above are described in detail later.

It should be noted that the figure shows only an exemplary structure of the PUF circuit-based signature information generation apparatus, and the signature information generation apparatus may further include more or less devices.

The structure and the operation principle of the PUF circuit are described below with reference to fig. 2-4.

As shown in fig. 2 to 4, the PUF circuit includes N first delay circuits 21 connected in series, N second delay circuits 22 connected in series, and a first comparison circuit 23. Here N is the same as N in fig. 1.

A first one 21 of the N first delay circuits 21 in series and a first one 22 of the N second delay circuits 22 in series are configured to receive an excitation signal, where the excitation signal may be a pulse signal, such as a clock signal, a clock division signal, and the like. One path of excitation signal is transmitted by the N first delay circuits 21 connected in series and then output by the nth first delay circuit 21, and this transmission path may be referred to as a first transmission path; the other excitation signal is transmitted through N second delay circuits 22 connected in series and then output through the nth second delay circuit 22, and this transmission path may be referred to as a second transmission path.

The first delay circuit 21 includes a first delay device D1, a first capacitive device L1, a second delay device D2, a second capacitive device L2, and a first selector S1. The second delay circuit 22 includes a third delay device D3, a third capacitive device L3, a fourth delay device D4, a fourth capacitive device L4, and a second selector S2. The form of the delay device and the capacitive device is not limited in the present application, for example, the delay device may be an active device, an inverter, etc., and the capacitive device may be an active device, a passive capacitor, an inverter, etc. Delay devices differ from capacitive devices in that: the time delay device is used for transmitting the excitation signal and providing smaller transmission time delay for the transmission of the excitation signal; the capacitive device is used as a load capacitor of a transmission path where the coupled delay device is located, and provides larger transmission delay for transmission of the excitation signal on the transmission path. In addition, the delay device or the capacitive device is not limited to one device, and may be obtained by coupling a plurality of devices.

For each first delay circuit 21, the first delay device D1 is coupled to a first end of the first capacitive device L1 and the first selector S1, the second delay device D2 is coupled to a second end of the second capacitive device L2 and the second selector S2, and the first selector S1 is configured to select one of the first delay device D1 or the second delay device D2 to transmit the excitation signal. Wherein, for the nth (1 ≦ N, and N is a positive integer) first delay circuit 21, the first selector S1 is configured to select one of the first delay device D1 or the second delay device D2 to transmit the driving signal based on the nth bit control signal of the N bit control signals. For example, as shown in fig. 2, when the input control signal of the control terminal of the first selector S1 is 0, the first delay device D1 is selected to transmit the excitation signal, and when the input control signal is 1, the second delay device D2 is selected to transmit the excitation signal. Or, when the control signal input by the control end of the first selector S1 is 1, the first delay device D1 is selected to transmit the excitation signal, and when the control signal input by the control end of the first selector S1 is 0, the second delay device D2 is selected to transmit the excitation signal.

The present application does not limit the coupling relationship between the first selector S1 and the first delay device D1, the first capacitive device L1, the second delay device D2, and the second capacitive device L2, as long as there is no direct coupling between the first capacitive device L1 and the second capacitive device L2. Illustratively, as shown in fig. 2, an input terminal of the first delay device D1 and an input terminal of the second delay device D2 are configured to receive the excitation signal, an output terminal of the first delay device D1 and the first capacitive device L1 are coupled to one input terminal of the first selector S1, and an output terminal of the second delay device D2 and the second capacitive device L2 are coupled to the other input terminal of the first selector S1. Alternatively, as shown in fig. 3, an input terminal of the first selector S1 is configured to receive the excitation signal, one output terminal of the first selector S1 is coupled to an input terminal of the first delay device D1 and the first capacitive device L1, another output terminal of the first selector S1 is coupled to an input terminal of the second delay device D2 and the second capacitive device L2, and an output terminal of the first delay device D1 is coupled to an output terminal of the second delay device D2.

For each second delay circuit 22, the third delay device D3 is coupled to the third capacitive device L3 and a first end of the second selector S2, the fourth delay device D4 is coupled to the fourth capacitive device L4 and a second end of the second selector S2, and the second selector S2 is configured to select one of the third delay device D3 or the fourth delay device D4 to transmit the excitation signal. Wherein, for the nth (1 ≦ N, and N is a positive integer) second delay circuit 22, the second selector S2 is configured to select one of the third delay device D3 and the fourth delay device D4 to transmit the driving signal based on the nth bit control signal of the N bit control signals. For example, as shown in fig. 2, when the input control signal of the control terminal of the second selector S2 is 0, the third delay device D3 is selected to transmit the excitation signal, and when the input control signal is 1, the fourth delay device D4 is selected to transmit the excitation signal. Or, when the control signal input by the control end of the second selector S2 is 1, the third delay device D3 is selected to transmit the excitation signal, and when the control signal input by the control end of the second selector S2 is 0, the fourth delay device D4 is selected to transmit the excitation signal.

The present application does not limit the coupling relationship between the second selector S2 and the third delay device D3, the third capacitive device L3, the fourth delay device D4 and the fourth capacitive device L4, as long as there is no direct coupling between the third capacitive device L3 and the fourth capacitive device L4. Illustratively, as shown in fig. 2, an input terminal of the third delay device D3 and an input terminal of the fourth delay device D4 are configured to receive the excitation signal, an output terminal of the third delay device D3 and the third capacitive device L3 are coupled to one input terminal of the second selector S2, and an output terminal of the fourth delay device D4 and the fourth capacitive device L4 are coupled to the other input terminal of the second selector S2. Alternatively, as shown in fig. 3, an input terminal of the second selector S2 is used for receiving the excitation signal, one output terminal of the second selector S2 is coupled to an input terminal of the third delay device D3 and the third capacitive device L3, another output terminal of the second selector S2 is coupled to an input terminal of the fourth delay device D4 and the second capacitive device L2, and an output terminal of the third delay device D3 is coupled to an output terminal of the fourth delay device D4.

It should be noted that, in the M N-bit control signals, each control signal and each bit control signal of the same control signal are independent from each other. Each control signal will select a unique pair of first and second transmission paths, M control signals will select M pairs of first and second transmission paths, each pair of first and second transmission paths will cause the PUF circuit to output a one-bit response signal, so the M control signals will cause the PUF circuit to output M-bits of response signal.

The capacitive device and the delay device in each delay circuit are used to generate a delay, but the two delay circuits have different principles for generating the delay. The delay device itself generates a delay (i.e., conduction delay) when conducting a transmission electrical signal. The capacitive device is coupled with the delay device, when an excitation signal transmitted by the delay device jumps, the capacitive device presents a capacitance characteristic (namely representing as a load capacitance of a transmission path where the delay device is located) to block the excitation signal from jumping, so that the capacitive device can also generate time delay, and the time delay generated by the capacitive device is far larger than the time delay generated by the delay device in signal transmission by increasing the number of the capacitive devices. Because the capacitance parameters of the capacitive device are less influenced by factors such as voltage, temperature and the like, the time delay generated by the capacitive device is stable. Even though the time delay generated by the time delay device is easily influenced by factors such as voltage, temperature and the like, the time delay generated by the time delay device accounts for a small proportion compared with the time delay generated by the capacitive device, the time delay generated by the capacitive device is a main factor for determining the time delay of the time delay circuit, and the time delay of each time delay circuit is slightly influenced by the factors such as voltage, temperature and the like.

For the nth first delay circuit and the nth second delay circuit, when the first selector S1 selects the first delay device D1 to transmit the excitation signal, the second selector S2 selects the third delay device D3 to transmit the excitation signal; when the first selector S1 selects the second delay device D2 to transmit the excitation signal, the second selector S2 selects the fourth delay device D4 to transmit the excitation signal. At this time, the first delay device D1 and the third delay device D3 employ the same device, the second delay device D2 and the fourth delay device D4 employ the same device, the first capacitive device L1 and the third capacitive device L3 employ the same device, and the second capacitive device L2 and the fourth capacitive device L4 employ the same device. Namely, for the nth first delay circuit and the nth second delay circuit, the selected delay devices are the same, and the selected capacitive devices are also the same, so as to prevent the first transmission path and the second transmission path from generating systematic delay differences due to different devices, so that the delay differences of the first transmission path and the second transmission path are mainly generated by process deviations of the same devices, and the delay differences are large in randomness and difficult to predict, copy or tamper.

For any two first delay circuits 21 of the N first delay circuits 21 connected in series: the devices adopted by the first delay device D1 are mutually independent, the devices adopted by the second delay device D2 are mutually independent, the devices adopted by the first capacitive device L1 are mutually independent, and the devices adopted by the second capacitive device L2 are mutually independent, that is, the devices adopted by the first delay circuits 21 are mutually independent. For any two second delay circuits 22 of the N second delay circuits 22 in series: the devices adopted by the third delay device D3 are independent of each other, the devices adopted by the fourth delay device D4 are independent of each other, the devices adopted by the third capacitive device L3 are independent of each other, and the devices adopted by the fourth capacitive device L4 are independent of each other, that is, the devices adopted by the second delay circuits 22 are independent of each other.

In the embodiments of the present application, the devices are independent of each other, which means that the devices may be the same or different. The device identity may include that at least one of the type, number, parameters, and the like of the device is the same, and the device identity may include that at least one of the type, number, parameters, and the like of the device is different.

Since the bit control signals are independent of each other, the randomness of the delay differences generated by the nth first delay circuit 21 and the nth second delay circuit 22 is independent of each other. Therefore, the N first delay circuits 21 connected in series and the N second delay circuits 22 connected in series also generate a delay difference due to process variations when transmitting the excitation signal, and the larger the number of the first delay circuits 21 and the second delay circuits 22 is, the larger the randomness of such a delay difference is, the more difficult it is to predict, copy, or tamper.

The first comparison circuit 23 is configured to output a response signal according to a time delay difference between the first signal and the second signal. The first signal is a signal obtained by transmitting an excitation signal through N first delay circuits 21 (i.e., first transmission paths), that is, the N first delay circuits 21 connected in series input the excitation signal and output the first signal; the second signal is a signal obtained by transmitting the excitation signal through the N second delay circuits 22 (i.e., the second transmission paths), that is, the N second delay circuits 22 connected in series input the excitation signal and output the second signal. The response signal is used to indicate that the first signal is earlier or later than the second signal. It should be noted that the first comparison circuit referred to in this application may implement comparison of the delay difference between two signals through a nand gate latch or a nor gate latch. The nand gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the rising edges of the two signals, and the nor gate latch can compare the time delay difference of the two signals by comparing the arrival speed of the falling edges of the two signals. For example, the present application is described with a nand gate latch as an example, but is not intended to be limited thereto.

Illustratively, as shown in fig. 2 to 4, the first comparison circuit 23 includes a first NAND gate latch NAND-SR1, and optionally, may further include a first Flip Flop (FF) FF1. The first NAND gate latch NAND-SR1 includes a first NAND gate NAND1 and a second NAND gate NAND2.

The output end of the nth first delay circuit 21 is coupled to the first input end of the first NAND gate NAND1, and the output end of the second NAND gate NAND2 is coupled to the second input end of the first NAND gate NAND 1; the output terminal of the nth second delay circuit 22 is coupled to the first input terminal of the second NAND gate NAND2, and the output terminal of the first NAND gate NAND1 is coupled to the second input terminal of the second NAND gate NAND2, wherein the output terminal of the first NAND gate NAND1 is configured to output the response signal. The first NAND gate NAND1 and the second NAND gate NAND2 form an interlock, thereby forming a NAND gate latch.

Optionally, the output of the first NAND gate NAND1 may be further coupled to a data input D of the first flip-flop FF1, and a data output Q of the first flip-flop FF1 is configured to output a response signal synchronized with the clock signal. That is, the data output terminal Q of the first flip-flop FF1 outputs a response signal of one bit every time the clock signal terminal CLK of the first flip-flop FF1 inputs one pulse of the clock signal.

The principle that the first NAND gate latch NAND-SR1 outputs the response signal according to the delay difference between the first signal and the second signal is as follows:

assuming that in the initial state, the nth first delay circuit 21 and the nth second delay circuit 22 both output 0, the first NAND gate NAND1 and the second NAND gate NAND2 both output 1, forming a stable interlocking state. The excitation signal is a signal that changes from a low level (or digital 0) to a high level (or digital 1). In addition, it is assumed that the excitation signal is transmitted through N first delay circuits 21 (i.e., first transmission paths) to obtain a first signal, and the excitation signal is transmitted through N second delay circuits 22 (i.e., second transmission paths) to obtain a second signal.

When the first signal is earlier than the second signal, the nth first delay circuit 21 outputs 1, the nth second delay circuit 22 still outputs 0, and then the first input terminal and the second input terminal of the first NAND gate NAND1 both input 1, so the first NAND gate NAND1 outputs 0, so the first input terminal and the second input terminal of the second NAND gate NAND2 both input 0, so the second NAND gate NAND2 outputs 1, and a stable interlocking state is also formed. At this time, the response signal output by the first NAND gate NAND1 is 0.

When the first signal is later than the second signal, the nth first delay circuit 21 still outputs 0, the nth second delay circuit 22 outputs 1, and then the first input end and the second input end of the second NAND gate NAND2 both input 1, so the second NAND gate NAND2 outputs 0, so that the first input end and the second input end of the first NAND gate NAND1 both input 0, so the first NAND gate NAND1 outputs 1, and a stable interlocking state is also formed. At this time, the response signal output by the first NAND gate NAND1 is 1.

That is, the response signal is 0 when the first signal after the stimulus signal is transmitted through the first transmission path is faster than the second signal after the stimulus signal is transmitted through the second transmission path, and is 1 when the stimulus signal is transmitted through the first transmission path is slower than the second transmission path.

In summary, the PUF circuit and the signature information generation apparatus provided in the embodiments of the present application include N first delay circuits connected in series, N second delay circuits connected in series, and a comparison circuit, and for each of the first delay circuits or the second delay circuits, each of the first delay circuits or the second delay circuits includes a selector, two delay devices, and two sets of capacitive devices, where each delay device is coupled to one set of capacitive devices, and the selector selects one delay device to transmit an excitation signal. Because the time delay generated by the load capacitor of the transmission path of the capacitive device as the delay device is far larger than the time delay generated by the transmission signal of the delay device, and the influence of the voltage, the temperature and other factors on the capacitance parameter of the capacitive device is small, the influence of the voltage, the temperature and other factors on the overall time delay of the N first delay circuits and the N second delay circuits is small. And comparing the time delay difference between the transmission of the excitation signal through the Nth first time delay circuit and the transmission of the excitation signal through the Nth second time delay circuit by using a comparison circuit to output a response signal. The stability of the response signal is less affected by voltage, temperature, etc., thereby improving the stability of the response signal generated by the PUF circuit.

As shown in fig. 4, on the basis of fig. 2, the PUF circuit may further include a fifth delay device D5, a sixth delay device D6, a second comparison circuit 24, and a third comparison circuit 25. Optionally, as shown in fig. 5, based on fig. 4, the PUF circuit may further include at least one of a seventh delay device D7 and an eighth delay device D8, where a delay generated by the seventh delay device D7 is smaller than a delay generated by the fifth delay device D5, and a delay generated by the eighth delay device D8 is smaller than a delay generated by the sixth delay device D6. It should be noted that the devices added to fig. 2 in fig. 4 or fig. 5 can also be applied to fig. 3.

As shown in fig. 4, an output terminal of the nth first delay circuit 21 of the N first delay circuits 21 is coupled to a first input terminal of the second comparison circuit 24 through the fifth delay device D5, an output terminal of the nth second delay circuit 22 of the N second delay circuits 22 is coupled to a second input terminal of the second comparison circuit 24, and the second comparison circuit 24 is configured to output a first indication signal, where the first indication signal is used to indicate whether a delay difference of the first signal earlier than the second signal is greater than a first threshold, where the first threshold is equal to a delay generated by the fifth delay device D5. Optionally, as shown in fig. 5, the output terminal of the nth second delay circuit 22 of the N second delay circuits 22 may be further coupled to the second input terminal of the second comparing circuit 24 through a seventh delay device D7, where the first threshold is equal to the delay generated by the fifth delay device D5 minus the delay generated by the seventh delay device D7. When the delay difference of the first signal is larger than the first threshold value earlier than that of the second signal, the delay difference can be stably maintained along with the lapse of the use time, so that the value 0 of the response signal can also be stably maintained, and the reliability of the response signal is higher; otherwise, it is described that such a delay difference is difficult to stably maintain, so that it is difficult to stably maintain the value 0 of the response signal, and thus the reliability of the response signal is low.

As shown in fig. 4, an output terminal of the nth second delay circuit 22 of the N second delay circuits 22 is coupled to a first input terminal of the third comparison circuit 25 through the sixth delay device D6, an output terminal of the nth first delay circuit 22 of the N first delay circuits 22 is coupled to a second input terminal of the third comparison circuit 25, and the third comparison circuit 25 is configured to output a second indication signal, where the second indication signal is used to indicate whether a delay difference of the second signal earlier than the first signal is greater than a second threshold, where the second threshold is equal to a delay generated by the sixth delay device D6. Optionally, as shown in fig. 5, the output terminal of the nth first delay circuit 21 of the N first delay circuits 21 may be further coupled to the second input terminal of the third comparing circuit 25 through an eighth delay device D8, where the second threshold is equal to the time delay generated by the sixth delay device D6 minus the time delay generated by the eighth delay device D8. When the delay difference of the second signal, which is earlier than the first signal, is greater than a second threshold, it is indicated that the delay difference can be stably maintained along with the lapse of the use time, so that the value 1 of the response signal can also be stably maintained, and the reliability of the response signal is higher; otherwise, it is said that such a delay difference is difficult to stably maintain, so that the value 1 of the response signal is also difficult to stably maintain, and thus the reliability of the response signal is low.

It should be noted that, similarly to the first comparison circuit 23, the second comparison circuit 24 and the third comparison circuit 25 involved in the present application may also implement comparison of the delay difference of two signals by a nand gate latch or a nor gate latch. For example, the present application is described with a nand gate latch as an example, but is not intended to be limited thereto. In addition, the PUF circuit shown in fig. 4 will be described as an example, but the PUF circuit is not limited to this, and the PUF circuit shown in fig. 5 can be applied similarly.

Illustratively, the second comparing circuit 24 includes a second NAND gate latch NAND-SR2, and optionally, may further include a second flip-flop FF2. The second NAND gate latch NAND-SR2 includes a third NAND gate NAND3 and a fourth NAND gate NAND4. The third comparison circuit 25 comprises a third NAND gate latch NAND-SR2 and, optionally, a third flip-flop FF3. The third NAND gate latch NAND-SR3 includes a fifth NAND gate NAND5 and a sixth NAND gate NAND6.

The output end of the nth first delay circuit 21 is coupled to the first input end of the third NAND gate NAND3 through the fifth delay device D5, and the output end of the fourth NAND gate NAND4 is coupled to the second input end of the third NAND gate NAND 3; the output end of the nth second delay circuit 22 is coupled to the first input end of the fourth NAND gate NAND4, and the output end of the third NAND gate NAND3 is coupled to the second input end of the fourth NAND gate NAND 4; the output end of the third NAND gate NAND3 is used for outputting the first indication signal. The third NAND gate NAND3 and the fourth NAND gate NAND4 form an interlock, thereby forming a NAND gate latch.

Optionally, the output of the third NAND gate NAND3 may be further coupled to a data input D of the second flip-flop FF2, and a data output Q of the second flip-flop FF2 is configured to output a first indication signal synchronized with the clock signal. That is, the data output terminal Q of the second flip-flop FF2 outputs the first indication signal of one bit every time the clock signal terminal CLK of the second flip-flop FF2 inputs one pulse of the clock signal.

An output end of the nth second delay circuit 22 is coupled to a first input end of a fifth NAND gate NAND5 through a sixth delay device D6, and an output end of the sixth NAND gate NAND6 is coupled to a second input end of the fifth NAND gate NAND 5; the output terminal of the nth first delay circuit 21 is coupled to the first input terminal of the sixth NAND gate NAND6, and the output terminal of the fifth NAND gate NAND5 is coupled to the second input terminal of the sixth NAND gate NAND 6; the output end of the fifth NAND gate NAND5 is used for outputting a second indication signal. The fifth NAND gate NAND5 and the sixth NAND gate NAND6 form an interlock, thereby forming a NAND gate latch.

Optionally, the output of the fifth NAND gate NAND5 may be further coupled to the data input D of the third flip-flop FF3. The data output terminal Q of the third flip-flop FF3 is used for outputting a second indication signal synchronized with the clock signal. That is, the data output terminal Q of the third flip-flop FF3 outputs the second indication signal of one bit every time the clock signal terminal CLK of the third flip-flop FF3 inputs one pulse of the clock signal.

The principle that the second NAND gate latch NAND-SR2 outputs the first indication signal and the third NAND gate latch NAND-SR3 outputs the second indication signal is as follows:

assuming that in the initial state, the nth first delay circuit 21 and the nth second delay circuit 22 each output 0, the third NAND gate NAND3, the fourth NAND gate NAND4, the fifth NAND gate NAND5 and the sixth NAND gate NAND6 each output 1, forming a stable interlocking state. The excitation signal is a signal changing from a low level (or digital 0) to a high level (or digital 1). In addition, it is assumed that the excitation signal is transmitted through N first delay circuits 21 (i.e., first transmission paths) to obtain a first signal, and the excitation signal is transmitted through N second delay circuits 22 (i.e., second transmission paths) to obtain a second signal.

As described above, when the first signal is earlier than the second signal, the response signal is 0. Under such conditions:

the first condition is as follows: when the delay difference of the first signal is earlier than the delay difference of the second signal and is greater than the first threshold, after the first signal is delayed by the fifth delay device D5, the nth second delay circuit 22 still outputs 0, then the first input terminal and the second input terminal of the third NAND gate NAND3 both input 1, so the output terminal of the third NAND gate NAND3 outputs 0, so the first input terminal and the second input terminal of the fourth NAND gate NAND4 both input 0, so the fourth NAND gate NAND4 outputs 1, and a stable interlocking state is also formed. At this time, the first indication signal output by the third NAND gate NAND3 is 0.

And a second condition: when the delay difference of the first signal is smaller than the first threshold earlier than the delay difference of the second signal, the first signal is delayed by the fifth delay device D5, the nth second delay circuit 22 outputs 1 first, and then the first input end and the second input end of the fourth NAND gate NAND4 both input 1, so the output end of the fourth NAND gate NAND4 outputs 0, so the first input end and the second input end of the third NAND gate NAND3 both input 0, so the third NAND gate NAND3 outputs 1, and a stable interlocking state is also formed. At this time, the first indication signal output by the third NAND gate NAND1 is 1.

In either case, the first input terminal of the fifth NAND gate NAND5 inputs 0, so the second indication signal output by the output terminal of the fifth NAND gate NAND5 is always 1, and is not used for indicating whether the value of the response signal is 0 or not.

To sum up, when the response signal is 0, the value 0 of the response signal is valid when the first indication information is 0, and the value 0 of the response signal is invalid when the first indication information is 1.

As described above, when the second signal is earlier than the first signal, the response signal is 1. Under such conditions:

and a third situation: when the delay difference of the second signal is greater than the second threshold earlier than the first signal, the second signal is delayed by the sixth delay device D6, and the nth first delay circuit 21 still outputs 0, then the first input end and the second input end of the fifth NAND gate NAND5 both input 1, so the output end of the fifth NAND gate NAND5 outputs 0, so the first input end and the second input end of the sixth NAND gate NAND6 both input 0, so the sixth NAND gate NAND6 outputs 1, and a stable interlocking state is also formed. At this time, the second indication signal output by the fifth NAND gate NAND5 is 0.

Case four: when the delay difference of the second signal is smaller than the second threshold value earlier than the first signal, the second signal is delayed by the sixth delay device D6, the nth first delay circuit 21 outputs 1 first, and then the first input end and the second input end of the sixth NAND gate NAND6 both input 1, so the output end of the sixth NAND gate NAND6 outputs 0, so the first input end and the second input end of the fifth NAND gate NAND5 both input 0, so the fifth NAND gate NAND5 outputs 1, and a stable interlocking state is also formed. At this time, the second indication signal output by the fifth NAND gate NAND5 is 1.

In both cases three and four, the first input terminal of the third NAND gate NAND3 inputs 0, so the first indication signal output by the output terminal of the third NAND gate NAND3 is always 1, and is not used for indicating whether the value 1 of the response signal is valid or not.

In summary, when the response signal is 1, the value 1 of the response signal is valid when the second indication information is 0, and the value 1 of the response signal is invalid when the second indication information is 1.

In addition, the clock signal terminal CLK of the first flip-flop FF1, the second flip-flop FF2 and the third flip-flop FF3 inputs the same clock signal, and as described above, the data output terminal Q of the first flip-flop FF1 outputs a bit response signal every time the clock signal terminal CLK of the first flip-flop FF1 inputs a pulse of the clock signal; when a clock signal end CLK of the second flip-flop FF2 inputs a pulse of a clock signal, a data output end Q of the second flip-flop FF2 outputs a first indication signal with a bit; the data output terminal Q of the third flip-flop FF3 outputs a second indication signal of one bit for every input of one pulse of the clock signal from the clock signal terminal CLK of the third flip-flop FF3. That is, the response signal, the first indication signal and the second indication signal correspond to each other by bits, and when the response signal has M bits, the first indication signal and the second indication signal also have M bits, and each bit of the first indication signal and the second indication signal indicates the reliability of one bit of the response signal.

In summary, the PUF circuit shown in fig. 4 may further output a first indication signal and a second indication signal, where the first indication signal is used to indicate whether a delay difference of the first signal before the second signal is greater than a first threshold, the second indication signal is used to indicate whether a delay difference of the second signal before the first signal is greater than a second threshold, the first signal is a signal obtained by transmitting the excitation signal through N first delay circuits connected in series in the PUF circuit, and the second signal is a signal obtained by transmitting the excitation signal through N second delay circuits connected in series in the PUF circuit. The two pieces of indication information actually indicate whether the value of the corresponding bit of the response signal is stable or not, so that each stable bit of the response signal can be used as one bit of the signature information, and the efficiency of generating the signature information is improved.

The following describes how the processor 11 obtains the signature information from the response signal, wherein each bit of the signature information is taken from one bit of the response signal.

In one possible embodiment, the processor 11 may select any bit of the response signal to obtain the signature information, for example, when the response signal output by the PUF circuit has M bits, the first M/2 bits may be combined to obtain the signature information, and when M =256, the signature information may have 128 bits.

In another possible embodiment, the processor 11 may derive the signature information from one of the first indication signal or the second indication signal and the response signal. In addition, the processor 11 may obtain a third indication signal according to one of the first indication signal or the second indication signal, where the third indication signal is used to indicate whether each bit of the response signal is valid, and when the response signal has M bits, the third indication signal also has M bits.

As described above, when the first signal is earlier than the second signal, the response signal is 0. Further, for the first case, when the first indication signal indicates that the delay difference of the first signal before the second signal is greater than the first threshold, the first indication signal is 0, the second indication signal is 1, and the third indication signal indicates that the one bit of the response signal is valid (for example, the third indication signal takes a value of 1), and the one bit of the response signal may be used as one bit of the signature information. Otherwise, for the second case, when the first indication signal indicates that the delay difference of the first signal earlier than the second signal is not greater than the first threshold, the first indication signal is 1, the second indication signal is 1, and the third indication signal indicates that the one bit of the response signal is invalid (for example, the third indication signal takes a value of 0), and the one bit of the response signal cannot be used as one bit of the signature information.

As described above, when the second signal is earlier than the first signal, the response signal is 1. Further, for the case three, when the second indication signal indicates that the delay difference of the second signal before the first signal is greater than the second threshold, the second indication signal is 0, and the first indication signal is 1, the third indication signal indicates that the one bit of the response signal is valid (for example, the third indication signal takes a value of 1), and the one bit of the response signal may be used as one bit of the signature information; otherwise, for the fourth case, when the second indication signal indicates that the delay difference of the second signal earlier than the first signal is not greater than the second threshold, the second indication signal is 1, and the first indication signal is 1, the third indication signal indicates that the one bit of the response signal is invalid (for example, the third indication signal takes a value of 0), and the one bit of the response signal cannot be used as one bit of the signature information.

When the response signal output by the PUF circuit has M bits, the first M/2 effective bit combinations can be taken to obtain signature information. For example, when M =256, the signature information may have 128 bits.

The value of each bit of the response signal, the first indication signal, the second indication signal, the third indication signal and the signature information may refer to a truth table shown in table 1. Wherein X indicates that the bit of the response signal is not a bit of the signature information.

TABLE 1

	Response signal	A first indication signal	Second indication signal	Third indication signal	Signature information
						Situation one	0	0	1	1 (effective)	0
Situation two	0	1	1	0 (invalid)	X
						Situation three	1	1	0	1 (effective)	1
Situation four	1	1	1	0 (invalid)	X

The division of the modules is only one logical function division, and other division manners may be available in actual implementation, for example, a plurality of modules or components may be combined or integrated into another device, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some interfaces, and may be in an electrical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one device, or may be distributed on a plurality of devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, functional modules in the embodiments of the present application may be integrated into one device, or each module may exist alone physically, or two or more modules may be integrated into one device.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A Physically Unclonable Function (PUF) circuit, comprising: the circuit comprises a first comparison circuit, N first delay circuits connected in series and N second delay circuits connected in series; the first delay circuit comprises a first delay device, a first capacitive device, a second delay device, a second capacitive device and a first selector; the second delay circuit comprises a third delay device, a third capacitive device, a fourth delay device, a fourth capacitive device and a second selector; n is a positive integer;

for each first delay circuit, the first delay device is coupled to the first capacitive device and the first terminal of the first selector, and the second delay device is coupled to the second capacitive device and the second terminal of the first selector;

for each second delay circuit, the third delay device is coupled to the third capacitive device and the first end of the second selector, and the fourth delay device is coupled to the fourth capacitive device and the second end of the second selector;

the N series first delay circuits are used for inputting excitation signals and outputting first signals;

the N second delay circuits connected in series are used for inputting the excitation signals and outputting second signals;

the first comparison circuit is used for outputting a response signal according to the time delay difference between the first signal and the second signal, and the response signal is used for indicating that the first signal is earlier or later than the second signal.

2. The PUF circuit of claim 1, further comprising a fifth delay device and a second comparison circuit;

an output end of an nth first delay circuit of the N first delay circuits is coupled to a first input end of the second comparison circuit through the fifth delay device, an output end of an nth second delay circuit of the N second delay circuits is coupled to a second input end of the second comparison circuit, the second comparison circuit is configured to output a first indication signal, and the first indication signal is configured to indicate whether a delay difference of the first signal earlier than the second signal is greater than a first threshold value.

3. The PUF circuit of claim 2, further comprising a seventh delay device, the delay produced by the seventh delay device being less than the delay produced by the fifth delay device; an output terminal of the nth second delay circuit is coupled to a second input terminal of the second comparison circuit through the seventh delay device.

4. The PUF circuit of any one of claims 1-3, further comprising a sixth time delay device and a third comparison circuit;

an output end of an nth second delay circuit of the N second delay circuits is coupled to a first input end of the third comparison circuit through the sixth delay device, an output end of an nth first delay circuit of the N first delay circuits is coupled to a second input end of the third comparison circuit, the third comparison circuit is configured to output a second indication signal, and the second indication signal is configured to indicate whether a delay difference of the second signal earlier than the first signal is greater than a second threshold value.

5. The PUF circuit of claim 4, further comprising an eighth delay device, wherein a delay generated by the eighth delay device is less than a delay generated by the sixth delay device; the output end of the nth first delay circuit is coupled to the second input end of the third comparison circuit through the eighth delay device.

6. The PUF circuit of any one of claims 1 to 5, wherein the first comparison circuit comprises a nand gate latch, or a nor gate latch.

7. The PUF circuit according to any of claims 1-6, wherein for the nth first delay circuit and the nth second delay circuit, 1 ≦ N ≦ N, and N is a positive integer:

when the first selector selects the first delay device to transmit the excitation signal, the second selector selects the third delay device to transmit the excitation signal; the first delay device and the third delay device are the same, and the first capacitive device and the third capacitive device are the same;

when the first selector selects the second delay device to transmit the excitation signal, the second selector selects the fourth delay device to transmit the excitation signal; the second delay device and the fourth delay device are the same, and the second capacitive device and the fourth capacitive device are the same.

8. The PUF circuit of any one of claims 1 to 7, wherein for any two first delay circuits of the series of N first delay circuits: the devices adopted by the first delay devices are mutually independent, the devices adopted by the second delay devices are mutually independent, the devices adopted by the first capacitive devices are mutually independent, and the devices adopted by the second capacitive devices are mutually independent.

9. The PUF circuit of any one of claims 1 to 8, wherein for any two of the N second delay circuits in the series: the devices adopted by the third time delay device are mutually independent, the devices adopted by the fourth time delay device are mutually independent, the devices adopted by the third capacitive device are mutually independent, and the devices adopted by the fourth capacitive device are mutually independent.

10. A signature information generating device comprising a Physically Unclonable Function (PUF) circuit according to any one of claims 1 to 9 and a processor;

the processor is configured to output a stimulus signal to the PUF circuit;

the processor is further configured to receive a response signal from the PUF circuit corresponding to the stimulus signal;

the processor is further configured to output signature information according to the response signal, the signature information being used to encrypt the processor output information.

11. The signature information generating apparatus according to claim 10, wherein the processor is further configured to:

receiving a first indication signal or a second indication signal from the PUF circuit, the first indication signal indicating whether a delay difference of the first signal earlier than the second signal is greater than a first threshold, the second indication signal indicating whether a delay difference of the second signal earlier than the first signal is greater than a second threshold;

obtaining the signature information according to the response signal and one of the first indication signal or the second indication signal, where each bit of the signature information is taken from a valid bit in the response signal, and the valid bit in the response signal refers to: a bit in the response signal when the first indication signal indicates that the delay difference of the first signal earlier than the second signal is greater than a first threshold, or when the second indication signal indicates that the delay difference of the second signal earlier than the first signal is greater than a second threshold.

12. The signature information generating apparatus according to claim 11, wherein the processor is further configured to:

obtaining a third indication signal according to one of the first indication signal or the second indication signal, wherein the third indication signal is used for indicating whether each bit of the response signal is valid or not.

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